Re: E1 line debug L1/L2

Hi Ivan, from your config: timeslot 0 phys_chan_config CCCH+SDCCH4 e1 line 0 timeslot 2 sub-slot full timeslot 1 phys_chan_config SDCCH8 e1 line 0 timeslot 2 sub-slot 1 timeslot 2 phys_chan_config TCH/F e1 line 0 timeslot 2 sub-slot 2 timeslot 3 phys_chan_config TCH/F e1 line 0 timeslot 2 sub-slot 3 timeslot 4 phys_chan_config TCH/F you cannot use e1 line 0 timeslot 2 as a full slot for signaling, and at the same time use it as 16k channelized sub-slots. That's clearly wrong. I just realized that the example config also does that. I guess we simply never use the 'e1 line ...' setting for a CCCH+SDCCH slot, as they always go via the RSL link configured in the TRX. -- - Harald Welte <laforge(a)gnumonks.org> http://laforge.gnumonks.org/ ============================================================================ "Privacy in residential applications is a desirable marketing option." (ETSI EN 300 175-7 Ch. A6)