Hi!
due to work overloead I've asked Martin to take over doing the various design changes of osmo-clock-gen towards v2. As the work progresses, we have some questions about your preference.
The major changes performed so far in the design:
1) switch from SAMD11 to SAMD21 processor (more flash/ram) https://osmocom.org/issues/3856
We also used the opportunity of having more UARTs available to use a different UART on the UEXT than on the 2.5mm console port.
There are no questions here.
2) allow different output voltages for two of the four banks of the Silabs chip https://osmocom.org/issues/3905
* have jumpers in-line of two of the four output banks of the PLL chipc * jumper closed: reference is drawn from one (shared) "other voltage" LDO onboard * jumper open: reference voltage can be provided/injected by user from external reference
What's still open to discuss is whether or not the LDO will be fixed (you have to change resistors to change the voltage) or adjustable. In the latter case, we'd apply the DAC output of the SAMD21 as an input to the tracking input of the LDO. However, this would mean that we'd no longer have the DAC output for driving a VCTCXO.
Which brings us to
3) should we keep the VCTCXO?
I really only placed it in v1 as PCB space was available. Note that while v1 can drive the VCTCXO Control voltrage from the microcontroller, there is no circuitry on board to acually measure/compare/count the output frequency and hence it's not possible to really have a control *loop* as the feedback is missing. That makes it rather useless.
So for the v2, we can either
a) remove the VCTCXO altogether and use the DAC output for software-modifiable output voltage levels of [some of] the clocks, or
b) try to come up with a way to actually count the clock cycles and compare it against some reference. I'm not sure the SAMD21 could do a very good job of that, as I'm assuming that all inputs are sampled to some internal clock and hence experience jitter.
I personally would go for 'a', as to me this board/module was always only about the PLL, and not about providing a stable reference itself. I'd much rather have a separate board/module with a GPS-DO, which then provides a 10MHz reference into any number of osmo-clk-gen boards to derive any number of other clocks. Sort of like the good old unix philosophy of doing only one thing in one program and chaining them together.
Any thoughts?
There's also still to be done:
4) Use SAMD XOSC / PLL / GCLK to allow lower reference frequencies https://osmocom.org/issues/3857 Where we'd actually use one of the SAMD GCLK outputs as one of the intputs to the Si5351C, and expose a GCLK input of the SAMD on an external header. This way, much lower frequencies can be used to driver the Si5351C. Or one could even go for deriving them from the SAMD RTC XTAL.
Regards, Harald
- allow different output voltages for two of the four banks of the Silabs chip https://osmocom.org/issues/3905
I'd use the DAC for software voltage tuning. Use 0R to select which bank uses which (default rail or programmable one, with just default to have 1/2 bank being the programmable vio).
- should we keep the VCTCXO?
No. As you explained I think it's better to split functions and not overload this board.
- Use SAMD XOSC / PLL / GCLK to allow lower reference frequencies https://osmocom.org/issues/3857 Where we'd actually use one of the SAMD GCLK outputs as one of the intputs to the Si5351C, and expose a GCLK input of the SAMD on an external header. This way, much lower frequencies can be used to driver the Si5351C. Or one could even go for deriving them from the SAMD RTC XTAL.
Does that mean the SAMD core would be running from the reference clock ? (and so wouldn't run if there is no reference connected)
Cheers,
Sylvain
Hi Sylvain,
On Mon, May 20, 2019 at 05:13:42PM +0200, Sylvain Munaut wrote:
- allow different output voltages for two of the four banks of the Silabs chip https://osmocom.org/issues/3905
I'd use the DAC for software voltage tuning. Use 0R to select which bank uses which (default rail or programmable one, with just default to have 1/2 bank being the programmable vio).
Our solution so far was to have two banks fixed and two banks either fixed or variable by means of (mechanical, tht) jumpers. I'm not sure we can fit our of them, or if we can fit 0R SMD resistors at lest. @Martin?
- should we keep the VCTCXO?
No. As you explained I think it's better to split functions and not overload this board.
happy to see we're in agreement here.
- Use SAMD XOSC / PLL / GCLK to allow lower reference frequencies https://osmocom.org/issues/3857 Where we'd actually use one of the SAMD GCLK outputs as one of the intputs to the Si5351C, and expose a GCLK input of the SAMD on an external header. This way, much lower frequencies can be used to driver the Si5351C. Or one could even go for deriving them from the SAMD RTC XTAL.
Does that mean the SAMD core would be running from the reference clock ? (and so wouldn't run if there is no reference connected)
The SAMD can run from its internal oscillator, even while communicating over USB where it derives/recovers the USB clock from the SOF. So while one could run it from an external reference, it is not mandatory/required.
Hi Sylvain & Harald,
On Tue, 2019-05-21 at 11:37 +0200, Harald Welte wrote:
Hi Sylvain,
On Mon, May 20, 2019 at 05:13:42PM +0200, Sylvain Munaut wrote:
- allow different output voltages for two of the four banks of the Silabs chip https://osmocom.org/issues/3905
I'd use the DAC for software voltage tuning. Use 0R to select which bank uses which (default rail or programmable one, with just default to have 1/2 bank being the programmable vio).
Our solution so far was to have two banks fixed and two banks either fixed or variable by means of (mechanical, tht) jumpers. I'm not sure we can fit our of them, or if we can fit 0R SMD resistors at lest. @Martin?
Knowing that 2.54 mm jumpers can be huge – can't one just add a resistor in series with the DAC output and connect both that and the external Vref input to the tracking input of the regulator? (I didn't even know there was tracking regulators, that's awesome! I'd just have gone for an SC-70 opamp voltage follower; considering the 5.6 mA max bank I_DDOx current, that would suffice, I think?)
That way, with no external voltage fed in to these jumpers, the DAC is "alone" and assuming no significant current into the tracking input, the resistor doesn't skew the voltage. With an external source connected, one could just set the DAC output to be a high-Z input. The resistor then just fulfills the role of avoiding high currents going between DAC and external voltage source if one forgets to float the output first or the external voltage is significantly higher than the MCU's VCC. (the question would be "how does the MCU know there's an external voltage reference connected", but if the tracking input's impedance is high enough, one could use a very weak resistor, so that a "competing" DAC wouldn't even affect the external reference, and it wouldn't have to know.)
- should we keep the VCTCXO?
No. As you explained I think it's better to split functions and not overload this board.
happy to see we're in agreement here.
- Use SAMD XOSC / PLL / GCLK to allow lower reference frequencies https://osmocom.org/issues/3857 Where we'd actually use one of the SAMD GCLK outputs as one of the intputs to the Si5351C, and expose a GCLK input of the SAMD on an external header. This way, much lower frequencies can be used to driver the Si5351C. Or one could even go for deriving them from the SAMD RTC XTAL.
Does that mean the SAMD core would be running from the reference clock ? (and so wouldn't run if there is no reference connected)
The SAMD can run from its internal oscillator, even while communicating over USB where it derives/recovers the USB clock from the SOF. So while one could run it from an external reference, it is not mandatory/required.
I think the XOSC input pads of the SAM D11/21 can also function as normal GPIOs, so one could comfortably use these to detect the presence of a roughly suitable clock signal, and only then configure one of the internal clock buses (don't know – maybe even one used by nothing else) to source the clock from that, and enable the output of that internal clock to the respective GCLK to the GCLK_IO pin.
Regards, Marcus
Hi,
I'd use the DAC for software voltage tuning. Use 0R to select which bank uses which (default rail or programmable one, with just default to have 1/2 bank being the programmable vio).
Our solution so far was to have two banks fixed and two banks either fixed or variable by means of (mechanical, tht) jumpers. I'm not sure we can fit our of them, or if we can fit 0R SMD resistors at lest. @Martin?
Now it contains a 4x3 jumper block to switch the io supply of four banks (each forming two outputs) each between VDD fixed (3V3) and the adjustable supply.
considering the 5.6 mA max bank I_DDOx current, that would suffice, I think?)
5.6mA is max I_DDOx, - but _per output_. So any adjustable source must supply over 40mA to the PLL out drivers.
For the tracking LOD, I first selected the TLE4250. But lowest output voltage of this part is 2.5V, and as we want to have e.g. 1V8 as well, another part has to be found. I again took a buffer (voltage follower) formed of a generic R2R-IO, unity gain-stable CMOS opamp (MIC7300, TLV9001...). Those supply (or sink) 40 mA and more. But the max. output current depends on the output voltage, so, if we want to continue with that approach, I'd likely add a BJT current helper stage behind the opamp (BJT collector on 5V). We have almost no dynamic demands on that opamp, so disregarding any phase errors we introduce by driving large capacitive and resistive loads, it would work w/o a BJT, but let's see...
laforge just mentioned he wants to have added a very weak pull-down between VOUT (DAC) and op amp input, to ground spikes during power-on and fw started/GPIOs initialized. The PULLEN bits are 0 after reset, so no PU should be set...
external voltage reference and its input:
Knowing that 2.54 mm jumpers can be huge – can't one just add a resistor in series with the DAC output and connect both that and the external Vref input to the tracking input of the regulator? [...]
The DACVREFA (=ADCVREFA) pin has a limitation of AV_ref<= V_DDANA - 0.6V . As I'd want to have V_DDANA connected w/ a ferrite to V_DD (3V3), we can only use the internal reference 2, which is V_DDANA (SAMD21 ds: 37.11.5)
So I don't see an external ref voltage input on that PCB... maybe your use case would explain your needs here! ;)
VCTCXO:
- should we keep the VCTCXO?
No. As you explained I think it's better to split functions and not overload this board.
happy to see we're in agreement here.
;)
OK, thanks, part skipped and occupied area freed. I'll keep you updated about the ongoing progress.
Martin --
On Thu, 2019-05-23 at 19:27 +0200, Martin Schramm wrote:
For the tracking LOD, I first selected the TLE4250. But lowest output voltage of this part is 2.5V, and as we want to have e.g. 1V8 as well, another part has to be found.
yeah, that was my impression too once I searched ti.com for tracking LDOs: the ones available are either exceedingly large or don't go far enough down the voltage range. Hm, what about a buffered voltage follower (i.e. NPN BJT's base on the output of the opamp negative feedback and output on the emitter, VCC on the collector)? Should give plenty of current, with limited CE voltage drop but the ability to basically go to the negative rail with output voltage.
I again took a buffer (voltage follower) formed of a generic R2R-IO, unity gain-stable CMOS opamp (MIC7300, TLV9001...). Those supply (or sink) 40 mA and more. But the max. output current depends on the output voltage, so, if we want to continue with that approach, I'd likely add a BJT current helper stage behind the opamp (BJT collector on 5V). We have almost no dynamic demands on that opamp, so disregarding any phase errors we introduce by driving large capacitive and resistive loads, it would work w/o a BJT, but let's see...
ah nevermind, I think we're thinking of the same.
The DACVREFA (=ADCVREFA) pin has a limitation of AV_ref<= V_DDANA - 0.6V . As I'd want to have V_DDANA connected w/ a ferrite to V_DD (3V3), we can only use the internal reference 2, which is V_DDANA (SAMD21 ds: 37.11.5)
aaaah...
So I don't see an external ref voltage input on that PCB... maybe your use case would explain your needs here! ;)
Don't have a use case of my own here, sorry :) Maybe then using a GPIO pin PWM + FET + 2.54 mm jumper to VCC that doubles as external input would be easiest?
Best regards, Marcus
Hi
I again took a buffer (voltage follower) formed of a generic R2R-IO, unity gain-stable CMOS opamp (MIC7300, TLV9001...). Those supply (or sink) 40 mA and more. But the max. output current depends on the output voltage, so, if we want to continue with that approach, I'd likely add a BJT current helper stage behind the opamp (BJT collector on 5V). We have almost no dynamic demands on that opamp, so disregarding any phase errors we introduce by driving large capacitive and resistive loads, it would work w/o a BJT, but let's see...
Heh, I just prototyped something last weekend for another project with controlled VIO using a mcp6001 and a N-mos pass transistor. ( It sure doesn't have the lower drop-out configuration but I think it's more stable that way ).
So I don't see an external ref voltage input on that PCB... maybe your use case would explain your needs here! ;)
I don't see the need for a external vref input. VDDANA is fine.
Cheers,
Sylvain
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Harald Welte -
Martin Schramm -
Müller, Marcus (CEL) -
Sylvain Munaut