In RTL_SDR, option -b
What does:
"output_block_size (default 16*16384)" mean?
I have been searching and I just can't find that explained anywhere.
Thanks,
Pete
And another thing - the configuration demonstrated on the image you
provided is an actual Π (pi) type low pass filter composed by R-L-R
elements.
There, the individual resistor is 150 ohm, in DC they are parallel, in RF
they make a low pass filter along with the coil in btw.
Some implementations do not use any coil but a 0-ohm shunt resistor
instead. That means the resistors are parallel and they yield 75 ohms.
Cheers
On Sat, 25 May 2019 at 16:10, Ioannis Makris <makrisj(a)gmail.com> wrote:
> I mean that each RGB analog output of the FL2k on the PCB has permanent
> fixed terminations of 150 ohm. Still, I need to apologise for having to add
> a correction:
>
> Some of the dongles having only analog output are being terminated @ 75
> ohms at the factory.
>
> Ref.1: http://www.marsport.org.uk/smd/mainframe.htm
> Ref.2: See attached image
>
> This is normal. Those outputs are most probably open emitter outputs;
> hence they need a termination in order to actually produce any current.
> Leaving them floating in DC would most probably lead to unexpected and
> unaccounted for results.
> One could experiment by adding different values for termination or even a
> 330 ohms trimmer in rheostat configuration,while maintaining at least an 75
> ohms resistor in series so as to give a range of 75-405 ohms of
> termination.
> What is to be monitored is the actual spectral behavior of the DAC rather
> its maximum output, as there are unwanted spectral elements that could
> register as power output on the wanted frequency in conventional needle
> meters, when it actually that is far from truth.
> Affecting terminations yields intermodulation in amplifiers and unwanted
> spectral elements may occur due to several effects I can think of.
> Always monitor spectral output if you want to transmit with this thing.
> What I've seen is that if you just add 20dB of gain on its output without
> applying heavy filtering beforehand you could easily end up to jail for
> interfering aviation frequencies used at airports nearby.
>
Hi!
due to work overloead I've asked Martin to take over doing the various
design changes of osmo-clock-gen towards v2. As the work progresses, we
have some questions about your preference.
The major changes performed so far in the design:
1) switch from SAMD11 to SAMD21 processor (more flash/ram)
https://osmocom.org/issues/3856
We also used the opportunity of having more UARTs available to use a
different UART on the UEXT than on the 2.5mm console port.
There are no questions here.
2) allow different output voltages for two of the four banks of the Silabs chip
https://osmocom.org/issues/3905
* have jumpers in-line of two of the four output banks of the PLL chipc
* jumper closed: reference is drawn from one (shared) "other voltage" LDO onboard
* jumper open: reference voltage can be provided/injected by user from external reference
What's still open to discuss is whether or not the LDO will be fixed
(you have to change resistors to change the voltage) or adjustable. In
the latter case, we'd apply the DAC output of the SAMD21 as an input to
the tracking input of the LDO. However, this would mean that we'd no
longer have the DAC output for driving a VCTCXO.
Which brings us to
3) should we keep the VCTCXO?
I really only placed it in v1 as PCB space was available. Note that
while v1 can drive the VCTCXO Control voltrage from the microcontroller,
there is no circuitry on board to acually measure/compare/count the
output frequency and hence it's not possible to really have a control
*loop* as the feedback is missing. That makes it rather useless.
So for the v2, we can either
a) remove the VCTCXO altogether and use the DAC output for
software-modifiable output voltage levels of [some of] the clocks, or
b) try to come up with a way to actually count the clock cycles and
compare it against some reference. I'm not sure the SAMD21 could do
a very good job of that, as I'm assuming that all inputs are sampled
to some internal clock and hence experience jitter.
I personally would go for 'a', as to me this board/module was always only
about the PLL, and not about providing a stable reference itself. I'd
much rather have a separate board/module with a GPS-DO, which then
provides a 10MHz reference into any number of osmo-clk-gen boards to
derive any number of other clocks. Sort of like the good old unix
philosophy of doing only one thing in one program and chaining them
together.
Any thoughts?
There's also still to be done:
4) Use SAMD XOSC / PLL / GCLK to allow lower reference frequencies
https://osmocom.org/issues/3857
Where we'd actually use one of the SAMD GCLK outputs as one of the
intputs to the Si5351C, and expose a GCLK input of the SAMD on an
external header. This way, much lower frequencies can be used to
driver the Si5351C. Or one could even go for deriving them from the
SAMD RTC XTAL.
Regards,
Harald
--
- Harald Welte <laforge(a)gnumonks.org> http://laforge.gnumonks.org/
============================================================================
"Privacy in residential applications is a desirable marketing option."
(ETSI EN 300 175-7 Ch. A6)
While this is truly unexpected behaviour, please understand that the device
was designed for a termination load of 75+j0 ohms (that's what all
video/VGA analog signals require to be present at the load side) so any
other load impedance value is untested at factory.
I have independently tested that shorting the output to the ground causes
an instant halt to the output of the plain VGA dongle, so there might be
some protection circuit. Also, the VGA circuit has 150 ohms termination
loads.
Hello.
Managed to compile gr-osmosdr from git with gnuradio
3.8tech-preview-365-gd66bc948 (Python 3.7.3)
Having some issue converting osmosdr-source and sink block files from xml
verion to yml.
Anyone done such they'd be willing to share?
Thank you.
--
If something is requisite, how can it possibly be, prerequisite?
vanitas vanitatum omnia vanitas
later, steve
http://umn.edu/~barbo
Hi. When running the command line
fl2k_fm -c 5000 /dev/zero
to generate a continuous wave, the output voltage of the fl2k dongle
regularly switches between two different amplitude levels (peak to
peak voltage) every 2 or 3 seconds, by about %30 to %70 depending on
the load. There's no visible gradual transition, it just switches
instantly. The output peak-to-peak voltage is about 350 milivolts with
no load. I've calculated the output impedance to be about 750 ohm at
that frequency for the larger output level.
I'm using the HDMI version of the dongle with the wire soldered after
a capacitor (or resistor maybe) which was already there, to the red
VGA pixel output of the chip.
Could the issue be because some signal conditioning circuitry is
missing that is present in the actual VGA version of the dongle, or
that the pin is actually pulled to ground in this dongle as it is
unused, and the chip doesn't like it and for some reason it then
decides to regularly switch voltages? Any other ideas?
