May 2011 - baseband-devel - lists.osmocom.org

Engagetted !

by Sébastien Lorquet

http://www.engadget.com/2010/12/29/researchers-eavesdrop-on-encrypted-gsm-c… Congrats!

6 months, 1 week

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status report layer1 and layer23

by Andreas.Eversberg

hi, i just fixed some locking issues the last days. fix will follow. it took a bit longer, because there were some race conditions. it took up to about one hour until it crashed. my way to detect the area where the crash happened, was to turn on buzzer before that area, and turn it off after that area. after many hours of approximation, i finally found out that the major crash happend during _talloc_zero. (first it looks for a free memory chunk, then it allocates it.) since it can be called from all contexts (main, irq, fiq), it need to be locked against any interrupt, otherwise the memory chunk can be assigned multiple times. (the process of _talloc_free is "atomic" and requires no locking.) because it seems pretty stable, i think it is time to merge some branches into the master. (i made a 6 hours call yesterday. and no crash after bugfix ever since.) i will do that together with sylvain, if we find the time this weekend. currently i use the jolly/voice together with the sylvain/traffic branch. i am able to use an isdn phone togehter with linux-call-router and make/receive calls. audio is passed both ways. i think this is a stage where it actually become "usable". (if not moving arround.) one of my major work for the next weeks/months will be the neighbour cell measurement, cell re-selection, and handover. this is essential when moving with the phone. regards, andreas

11 years

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Receiving on TS=1 ?

by Sylvain Munaut

Hi, I've hacked something together to quickly test non-combined CCCH. However, I've hit a problem when trying to receive anything on another timeslot than 0. The TX side seems to work fine as the BTS can see my location update request and answers with a reject, but on the MS side, I never see the reject and wireshark only shows invalid incohrent data on the RX. The frames for SDCCH/8 show really nothing valid (looks like random bytes), things like 09 80 7f 47 49 06 1d 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 09 00 47 d5 2d 06 1e 00 00 69 7c a0 91 3d 22 ff ab fe 6c 4f 56 4f 36 ... while the frames for the associated SAACH show at least something gsm-like : 03 03 01 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b 2b but that's not quite a SI5/6 ... To RX/TX on TS=1, I just delayed the RX/TX window by 625 bits (4 * 156.25) when I'm in dedicated channel mode by chaning the 'start' in l1s_tx_win_ctrl / l1s_rx_win_ctrl Is there something else that should be done ? Cheers, Sylvain

11 years, 9 months

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burst_ind and TCH

by Mad

Hi Sylvain, hi list! I'm experimenting with burst_ind and TCHs right now and ran into some problem I couldn't solve yet. After receiving an Assignment Command for a hopping TCH/F I call l1ctl_tx_dm_est_req_h1() with all necessary parameters and tch_mode GSM48_CMODE_SPEECH_V1 or _EFR. After that I do get burst indications containing the received bits on up- and downlink for the active arfcn on each consecutive frame number. BUT the rx level measurements are most of the time very low and sporadic higher, surely not from that nearby bts and the very close cellphone. It looks like the layer1 doesn't "hit" the right timeslot on the right arfcn at the right time. There are some possible sources of error leading to that, like hopping parameters, channel number and MA list. But I checked these and I took all of them directly from the ASS CMD, the MA as word list in ascending order, like in layer23 IMM ASS handling. The specific AC doesn't have any specialties like Starting Time or "before time" parameters. So my question is if there is some obvious pitfall I'm missing and are there any suggestions how to debug that? Regards, Mad

11 years, 9 months

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bursts****.dat

by Victor P

Hi, I am trying to use burst_ind branch of osmocom. I have noticed that layer23 creates bursts****.dat files when it indicates uplink. What data are written to these files and what should I use to see its data? Thank you.

11 years, 10 months

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Use OsmocomBB as OpenBTS / airprobe clock generator

by Harald Welte

Hi! Recently we've had the idea of using OsmocomBB with a simple firmware that synchronizes to an existing GSM networks FCCH and use the resulting 13MHz clock to drive the USRP for airprobe or OpenBTS. Ideally, we would even use the Calypso-internal PLL (for ARM or DSP) to multiply it up to the required 52 MHz. However, neither the Openmoko nor the Compal/Motorola phones expose any of the 3 clock output pads :( So the only choice is to use something along the lines of the http://focus.ti.com/docs/prod/folders/print/cdcvf25084.html as a quad clock multiplier and attach it to the CLK13OUT signal of the phone. The chip is available for 9 USD in single quantities at digikey, and possibly cheaper at other sources. Combined with a sub-20EUR phone it might be a very cheap but still accurate frequency source for OpenBTS - at least as long as there are any commercial gsm networks available. Regards, Harald -- - Harald Welte <laforge(a)gnumonks.org> http://laforge.gnumonks.org/ ============================================================================ "Privacy in residential applications is a desirable marketing option." (ETSI EN 300 175-7 Ch. A6)

12 years, 1 month

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Linux + u-boot port to MT6235

by Marcin Mielczarczyk

Hi All! That's true, I managed to run U-Boot on MT6235, but linux kernel is not fully functional yet (it's fresh stuff as I managed to ran it on Tuesday and then I was off to conference). For MT6235 development I chose Sciphone G2, which is pretty cheap. After some time I managed to download code to SRAM (just 64KB) using MTK's FlashTool. MTK FlashTool communicates over UART directly with MT6235 bootloader and sends its own chunk of code (about 58KB) which is executed in SRAM and communicates with FlashTool. I found on pudn.com some pack to customize code loaded by FlashTool, thanks to which I could download my own code to SRAM (without JTAG). The problem was that it had to be linked with some security libraries which occupied about 56KB and not much memory left for my own code. Then I decided to try find JTAG pins to get all control on MT6235. That took me sometime, but finally I succeeded. The other bigger issue was initializing DRAM controller to be able to download bigger code (linux kernel + uboot) to external RAM. In sciphone there is problem that all interesting chips are under metal shield which is pretty havily soldered. In this case I couldn't read what kind of RAM memory is mounted without destroying the board (I don't have such soldering machine which could unsolder so big metal shield). Thanks to JTAG I could attach to target and then dump DRAM controller registers from processor running MTK's software, but setting these values after processor start and configuration of PLL didn't work. I decided to disassemble bootloader which could show me how DRAM controller is initialized and how code fron NAND is loaded (to be able to flash U-Boot and kernel to NAND so MT6235 will start my code automatically and I will not have to use JTAG). Currently I have knowledge how internal MT6235 bootloader is loading code from memory during startup and I also extracted procedure of DRAM controller initialization. Thanks to that I'm able to run U-Boot from the very begining of processor startup. The problem is that I have just one piece of Sciphone G2 and I don't want to flash it yet to not break existing code in it. Thanks to running device I'm able to attach with JTAG and check how peripherals are configured (i.e. LCD, MMC, etc.). I have backup of flash, but I'm not 100% sure if I will flash it back, phone will startup. That's why I bought second piece of Sciphone G2 and should receive it today or on Tuesday (this Monday is holiday in Poland). In this case I'll flash U-Boot to NAND and try to make it working. Then we could load the rest of code from U-Boot (to RAM or NAND over serial). You can see how my setup looks on attached picture. The good thing about it is that the same bootloader is used in MT622x, so it should be fairly easy to do the same on phones based on that SoCs (but unfortuantely it's just ARM7). If it comes to code, of course I can share it on "git.osmocom.org". Currently it's just basic port of U-Boot and not much for linux kernel, but I'm working on this now so I'll push it when it'll be ready. Currently I'm working on driver for NAND memory for U-Boot, so we could flash linux kernel. When that will be ready I'll push the code. Then I'll switch to linux kernel and when it'll be functional I also push the code. At this stage you will not need to have JTAG and you could load the code over serial in U-Boot. If it comes to GSM I didn't work with it before. I actualy worked 6 months in L2/3 team for LTE (on RRC) but it's different story. That could be really outstanding thing if we could run first phone ever with whole code open (from BB up to APP). BR, Marcin

12 years, 3 months

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calypso SIM driver on c139 (also: l1ctl SIM APDU)

by Gianni Tedesco

The SIM and the SIM reader in the phone and the mechanical contact between them are definitely working because the SIM can be accessed from the motorola firmware, from another phone and from a PC smartcard reader with no PIN or anything. However, under simtest firmware no data is received by the phone, even the ATR is zero bytes... Anybody had this problem? Also, is l1CTL SIM APDU command not implemented in the layer1 firmware? How are people making calls without a SIM? :P Gianni ----------------SIMTEST----8<----------------- Initializing driver: SIM: Registering interrupt handler for simcard-interface ====================== CALYPSO SIM REGISTER DUMP ===================== Reg_sim_cmd register (R/W) - FFFE:0000 |-REG_SIM_CMD = 0000 | |-REG_SIM_CMD_CMDCARDRST = 0 ==> SIM card reset sequence disabled. | |-REG_SIM_CMD_CMDIFRST = 0 | |-REG_SIM_CMD_CMDSTOP = 0 | |-REG_SIM_CMD_CMDSTART = 0 | |-REG_SIM_CMD_MODULE_CLK_EN = 0 ==> Clock of the module disabled. |-REG_SIM_STAT = 000b | |-REG_SIM_STAT_STATNOCARD = 1 ==> No card! | |-REG_SIM_STAT_STATTXPAR = 1 ==> Parity ok! | |-REG_SIM_STAT_STATFIFOFULL = 0 | |-REG_SIM_STAT_STATFIFOEMPTY = 1 ==> Fifo empty! |-REG_SIM_CONF1 = 000c | |-REG_SIM_CONF1_CONFCHKPAR = 0 ==> Parity check on reception disabled. | |-REG_SIM_CONF1_CONFCODCONV = 0 ==> Coding convention is direct (normal). | |-REG_SIM_CONF1_CONFTXRX = 1 ==> SIO line direction is in transmit mode. | |-REG_SIM_CONF1_CONFSCLKEN = 1 ==> SIM clock in normal mode. | |-REG_SIM_CONF1_reserved = 0 ==> ETU period is CONFETUPERIOD. | |-REG_SIM_CONF1_CONFSCLKDIV = 0 ==> SIM clock frequency is 13/4 Mhz. | |-REG_SIM_CONF1_CONFSCLKLEV = 0 ==> SIM clock idle level is low. | |-REG_SIM_CONF1_CONFETUPERIOD = 0 ==> ETU period is 372/8*1/Fsclk. | |-REG_SIM_CONF1_CONFBYPASS = 0 ==> Hardware timers and start and stop sequences are normal. | |-REG_SIM_CONF1_CONFSVCCLEV = 0 ==> SVCC Level is low (Only valid when CONFBYPASS = 1). | |-REG_SIM_CONF1_CONFSRSTLEV = 0 ==> SRST Level is low (Only valid when CONFBYPASS = 1). | |-REG_SIM_CONF1_CONFTRIG = 0x0 (FIFO trigger level) | |-REG_SIM_CONF1_CONFSIOLOW = 0 |-REG_SIM_CONF2 = 0940 | |-REG_SIM_CONF2_CONFTFSIM = 0x0 (time delay for filtering of SIM_CD) | |-REG_SIM_CONF2_CONFTDSIM = 0x4 (time delay for contact activation/deactivation) | |-REG_SIM_CONF2_CONFWAITI = 0x9 (CONFWAITI overflow wait time between two received chars) |-REG_SIM_IT = 0000 | |-REG_SIM_IT_SIM_NATR = 0 ==> On read access to REG_SIM_IT. | |-REG_SIM_IT_SIM_WT = 0 ==> On read access to REG_SIM_IT. | |-REG_SIM_IT_SIM_OV = 0 ==> On read access to REG_SIM_IT. | |-REG_SIM_IT_SIM_TX = 0 ==> On write access to REG_SIM_DTX or on switching | | from transmit to receive mode (CONFTXRX bit) | |-REG_SIM_IT_SIM_RX = 0 ==> On read access to REG_SIM_DRX. |-REG_SIM_DRX = 0100 | |-REG_SIM_DRX_SIM_DRX = 0x0 (next data byte in FIFO available for reading) | |-REG_SIM_DRX_STATRXPAR = 1 ==> Parity Ok. |-REG_SIM_DTX = 00 (next data byte to be transmitted) |-REG_SIM_MASKIT = 003f | |-REG_SIM_MASKIT_MASK_SIM_NATR = 1 ==> No-answer-to-reset interrupt is masked. | |-REG_SIM_MASKIT_MASK_SIM_WT = 1 ==> Character wait-time overflow interrupt is masked. | |-REG_SIM_MASKIT_MASK_SIM_OV = 1 ==> Receive overflow interrupt is masked. | |-REG_SIM_MASKIT_MASK_SIM_TX = 1 ==> Waiting characters to be transmit interrupt is masked. | |-REG_SIM_MASKIT_MASK_SIM_RX = 1 ==> Waiting characters to be read interrupt is masked. | |-REG_SIM_MASKIT_MASK_SIM_CD = 1 ==> SIM card insertion/extraction interrupt is masked. |-REG_SIM_IT_CD = fffe0010 |-REG_SIM_IT_CD_IT_CD = 0 ==> SIM card insertion/extraction interrupt is unmasked. Power up simcard: * Power enabled! * Clock enabled! * Reset released! SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Character underflow! (0 bytes) Reset simcard: * Reset pulled down! * Reset released! SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Character underflow! (0 bytes) SIM-T0: Transceiving APDU-Header: (a0 a4 00 00 02) SIM-ISR: Interrupt caught: Waiting for character to transmit... SIM-ISR: Interrupt caught: Waiting for character to transmit... SIM-ISR: Interrupt caught: Waiting for character to transmit... SIM-ISR: Interrupt caught: Waiting for character to transmit... SIM-ISR: Interrupt caught: Waiting for character to transmit... SIM-T0: Case 2: No input / Output of known length (See also GSM 11.11 Page 34) SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Character underflow! SIM-T0: T0 Protocol error: Missing ACK byte -- aborting! SIM-T0: Transceiving APDU-Header: (a0 c0 00 00 0f) SIM-ISR: Interrupt caught: Waiting for character to transmit... SIM-ISR: Interrupt caught: Waiting for character to transmit... SIM-ISR: Interrupt caught: Waiting for character to transmit... SIM-ISR: Interrupt caught: Waiting for character to transmit... SIM-ISR: Interrupt caught: Waiting for character to transmit... SIM-T0: Case 4: Input / No output (See also GSM 11.11 Page 34) SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Character underflow! SIM-T0: T0 Protocol error: Incorrect or missing answer -- aborting! e0 73 d7 b9 ae ea bf 7e f7 3b 7f 6f 32 fe 25 (15 bytes) Test Phase 1: Testing bare sim commands... * Testing SELECT: Selecting MF SIM-T0: Transceiving APDU-Header: (a0 a4 00 00 02) SIM-ISR: Interrupt caught: Waiting for character to transmit... SIM-ISR: Interrupt caught: Waiting for character to transmit... SIM-ISR: Interrupt caught: Waiting for character to transmit... SIM-ISR: Interrupt caught: Waiting for character to transmit... SIM-ISR: Interrupt caught: Waiting for character to transmit... SIM-T0: Case 2: No input / Output of known length (See also GSM 11.11 Page 34) SIM-ISR: Interrupt caught: Waiting characters to be read... SIM-ISR: Interrupt caught: Character underflow! SIM-T0: T0 Protocol error: Missing ACK byte -- aborting! ==> Status word: ffff * Testing SELECT: Selecting DF_GSM SIM-T0: Transceiving APDU-Header: (a0 a4 00 00 02) SIM-ISR: Interrupt caught: Waiting for character to transmit... SIM-ISR: Interrupt caught: Waiting for character to transmit... SIM-ISR: Interrupt caught: Waiting for character to transmit... At this point it hangs "forever" - well at least half hour.

12 years, 5 months

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Problems while building osmocomBB

by Begerad Stefan

Hi guys, I dunno if that is the right place for my concern about building the osmocomBB source. Here is what I already have done: - downloading the sources for osmocomBB and GNU toolchain for ARM, - setting the PATH for the arm-elf-* executables, - calling make in the src directory. Now, this appears as response of the make command in the terminal: cd shared/libosmocore/build-host && ../configure configure: error: cannot find install-sh, install.sh, or shtool in ".." "../.." "../../.." make: *** [shared/libosmocore/build-host/Makefile] Error 1. If you need details about my system, you can look at the following snippet from the config.log file: This file contains any messages produced by compilers while running configure, to aid debugging if configure makes a mistake. It was created by libosmocore configure UNKNOWN, which was generated by GNU Autoconf 2.65. Invocation command line was $ ../configure ## --------- ## ## Platform. ## ## --------- ## hostname = ubuntu-stefan uname -m = x86_64 uname -r = 2.6.32-24-generic uname -s = Linux uname -v = #41-Ubuntu SMP Thu Aug 19 01:38:40 UTC 2010 /usr/bin/uname -p = unknown /bin/uname -X = unknown /bin/arch = unknown /usr/bin/arch -k = unknown /usr/convex/getsysinfo = unknown /usr/bin/hostinfo = unknown /bin/machine = unknown /usr/bin/oslevel = unknown /bin/universe = unknown PATH: /usr/local/sbin PATH: /usr/local/bin PATH: /usr/sbin PATH: /usr/bin PATH: /sbin PATH: /bin PATH: /usr/games PATH: /home/stefan/osmocomBB/gnuarm-4.0.2/bin ## ----------- ## ## Core tests. ## ## ----------- ## configure:2032: error: cannot find install-sh, install.sh, or shtool in ".." "../.." "../../..". So, I would be very glad, if someone could give me a hint to solve the problem. Thank you in advance. Regards, begy

12 years, 5 months

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Motorola C116 experiment

by Henk

Hi, I could not resist buying a C116 for 15 euro, so I compiled osmocombb and connected a 3.3V serial cable. Of course the C116 was not in the supported list, but I was hoping it would work as it seems that it is very similar to the C115. Here is my load attempt: (used -m c123 ) but there's no loading of the image. I am not using TX mode, also I don't have a SIM installed. Anything I can try to get it working? ./osmocon -p /dev/ttyS0 -m c123xor ../../target/firmware/board/compal_e88/loader.compalram.bin got 1 bytes from modem, data looks like: 00 . got 2 bytes from modem, data looks like: 00 81 .. got 4 bytes from modem, data looks like: 1b f6 02 00 .... got 1 bytes from modem, data looks like: 41 A got 1 bytes from modem, data looks like: 01 . got 1 bytes from modem, data looks like: 40 @ Received PROMPT1 from phone, responding with CMD read_file(../../target/firmware/board/compal_e88/loader.compalram.bin): file_size=16788, hdr_len=4, dnload_le n=16795 got 1 bytes from modem, data looks like: 66 f got 1 bytes from modem, data looks like: 74 t got 1 bytes from modem, data looks like: 6d m got 1 bytes from modem, data looks like: 74 t got 1 bytes from modem, data looks like: 6f o got 1 bytes from modem, data looks like: 6f o got 1 bytes from modem, data looks like: 6c l Received FTMTOOL from phone, ramloader has aborted got 1 bytes from modem, data looks like: 65 e got 1 bytes from modem, data looks like: 72 r got 1 bytes from modem, data looks like: 72 r got 1 bytes from modem, data looks like: 6f o got 1 bytes from modem, data looks like: 72 r got 1 bytes from modem, data looks like: 00 . got 1 bytes from modem, data looks like: 1b . got 1 bytes from modem, data looks like: 66 f got 1 bytes from modem, data looks like: 6d m got 1 bytes from modem, data looks like: 74 t got 1 bytes from modem, data looks like: 6f o Regards, Henk

12 years, 9 months

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Help me I have a difficult problem

by adel

Hello I'm having a problem in the start mobile application ~/osmocom-bb$ cd src/host/layer23/src/mobile ~/osmocom-bb/src/host/layer23/src/mobile$ ./mobile Copyright (C) 2008-2010 ... Contributions by ... License GPLv2+: GNU GPL version 2 or later <http://gnu.org/licenses/gpl.html> This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. Failed to parse the config file: '/etc/osmocom/osmocom.cfg' Please check or create config file using: 'touch /etc/osmocom/osmocom.cfg' ~/osmocom-bb/src/host/layer23/src/mobile$ Please help me as soon as -- View this message in context: http://baseband-devel.722152.n3.nabble.com/Help-me-I-have-a-difficult-probl… Sent from the baseband-devel mailing list archive at Nabble.com.

12 years, 9 months

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replacing the RX filter with a balun on the c139

by Joshua Lackey

I've been going over Sylvain's report on removing the RX filters, http://www.246tnt.com/gsm/rx_filter.html, and I had some slight differences on the c139 that I'm hoping someone can help me with. Similar to Sylvain's experience, the schematic doesn't match reality. Just as Sylvain describes, the signal from the balanced output appears to be going through inductors rather than capacitors and there isn't a bridging inductor. However on my c139, the unbalanced input is missing the inductor to ground on the EGSM path and is missing the capacitor to ground on the DCS path. (Sylvain had a capacitor to ground on DCS where the schematic has an inductor to ground.) You can find a picture of what I'm looking at here: http://thre.at/c139/c139rxfilters.jpg . I've placed the c139 schematics in that directory as well, http://thre.at/c139 . My guess is that the filters in the schematics had a different unbalanced impedance than the ones they ended up placing on the c139. But I'm not an EE, and that is just a guess. I can't read the markings on the filters I have, so I can't check the unbalanced input from a data sheet. I also don't have a way to measure the components that are there now so I can't try and compute the value. My question is, does this matter? That is, should I use the same balun that Sylvain chose or should I find one with a different unbalanced impedance? Alternatively, should I use the same baluns and just install an inductor (or capacitor on DCS) to ground so that it matches Sylvain's c123? Any ideas? (As an aside, the baluns that Sylvain chose aren't perfect for the US frequency range, but they should work okay.)

12 years, 9 months

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Invitation

by weberbe＠ee.ethz.ch

Hi list First of all: Thanks to all of you who actively develop OsmocomBB. Second: In the past few months I worked on an interface between a GSM transceiver and ABB towards the mobile application from OsmocomBB. The findings will be presented Tuesday, May 31, 1.55 pm in ETZ J64 at ETH in Zurich (Gloriastrasse 35, 8092 Zürich). You are all invited. The goal of this project was to understand the GSM protocol flow better in order to be able to extend the hardware towards higher layers. To this end, the mobile application (L2 and L3) was used. Benjamin

12 years, 10 months

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Testing protocol stack with OsmocomBB (cheap way)

by Drasko DRASKOVIC

Hi all, going through the documentation, I am trying to figure out what would be the best way to have whole protocol stack communication with OsmocomBB. Now, I understand that osmocon can be used to load layer1 into phones RAM, so that this code turns on Calypso and communicate with DSP with AT commands. Then osmocon gets messages from layer1 via RS232 and can distribute them to the mobile application, which sends them to layer23 for further processing or via GSM tap to Wireshark or outputs them on stdout. What I am most interested in how do we insert pacgaes on the other side of the stack, i.e. via telephone air interface (packets that will traverse through Rita, Iota, Calypso down to stdout of host). From what I understand we need some kind of BTS, and I can see that GNU Radio is used for this purpose. But for this, as I understand USPRP (http://en.wikipedia.org/wiki/Universal_Software_Radio_Peripheral) FPGA motherboard with both RX and TX doughterboards is needed, which can go up to 1k eur (too expensive for a hobbist). I was wondering so, what is the best and the cheapest way to inject packets at the protocol stack on the phone and analyze some packet flow later with Wireshark - i.e. to get some usage of the OsmocomBB and to see how it works. At this point I can only run Hello World application, or "mobile" app without any usage (or I do not know how to use it). What would be the best way to start playing around without spending too much money. Speaking of this, what would be the price of the cheapest existing packet generator that can transmit them via Um (i.e. what is the price of the cheapest BTS)? Is there some open source FPGA that can be used for this purpose? Thanks for your explanations and best regards, Drasko

12 years, 10 months

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First OsmocomBB Connection Tests (Unsuccessful)

by Drasko DRASKOVIC

Hi all, I am trying to have some OsmocomBB communication and my procedure is following : 1) I start osmocon with layer1 sw : ./osmocon -p /dev/ttyUSB1 -m c123xor ../../target/firmware/board/compal_e88/layer1.compalram.bin It now waits for power on button from the phone 2) In the other terminal I start mobile application : ./mobile -i 127.0.0.1 Copyright (C) 2008-2010 ... Contributions by ... License GPLv2+: GNU GPL version 2 or later <http://gnu.org/licenses/gpl.html> This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. VTY available on port 4247. No Mobile Station defined, creating: MS '1' <000e> sim.c:1206 init SIM client <0005> gsm48_cc.c:61 init Call Control <0001> gsm48_rr.c:4944 init Radio Ressource process <0004> gsm48_mm.c:1220 init Mobility Management process <0004> gsm48_mm.c:971 Selecting PLMN SEARCH state, because no SIM. <0002> gsm322.c:3472 init PLMN process <0003> gsm322.c:3473 init Cell Selection process Mobile '1' initialized, please start phone now! 3) Now I press a "power-on" button on the phone and I have logs comming out on the both terminals. I guess that MS is doing various cell power measurements and trying to discass with near-by cells over controle channels. However, in ./osmocon terminal it finishes like this : $ ./osmocon -p /dev/ttyUSB1 -m c123xor ../../target/firmware/board/compal_e88/layer1.compalram.bin got 1 bytes from modem, data looks like: 00 . got 1 bytes from modem, data looks like: 00 . got 1 bytes from modem, data looks like: 81 . got 4 bytes from modem, data looks like: 1b f6 02 00 .... got 1 bytes from modem, data looks like: 41 A got 1 bytes from modem, data looks like: 01 . got 1 bytes from modem, data looks like: 40 @ Received PROMPT1 from phone, responding with CMD read_file(../../target/firmware/board/compal_e88/layer1.compalram.bin): file_size=47700, hdr_len=4, dnload_len=47707 got 1 bytes from modem, data looks like: 1b . got 1 bytes from modem, data looks like: f6 . got 1 bytes from modem, data looks like: 02 . got 1 bytes from modem, data looks like: 00 . got 1 bytes from modem, data looks like: 41 A got 1 bytes from modem, data looks like: 02 . got 1 bytes from modem, data looks like: 43 C Received PROMPT2 from phone, starting download handle_write(): 1023 bytes (1023/47707) handle_write(): 768 bytes (1791/47707) handle_write(): 768 bytes (2559/47707) handle_write(): 768 bytes (3327/47707) ... handle_write(): 768 bytes (44031/47707) handle_write(): 768 bytes (44799/47707) handle_write(): 768 bytes (45567/47707) handle_write(): 768 bytes (46335/47707) handle_write(): 768 bytes (47103/47707) handle_write(): 604 bytes (47707/47707) handle_write(): finished got 1 bytes from modem, data looks like: 1b . got 1 bytes from modem, data looks like: f6 . got 1 bytes from modem, data looks like: 02 . got 1 bytes from modem, data looks like: 00 . got 1 bytes from modem, data looks like: 41 A got 1 bytes from modem, data looks like: 03 . got 1 bytes from modem, data looks like: 42 B Received DOWNLOAD ACK from phone, your code is running now! OSMOCOM Layer 1 (revision osmocon_v0.0.0-884-gd76345a) ====================================================================== Device ID code: 0xb4fb Device Version code: 0x0000 ARM ID code: 0xfff3 cDSP ID code: 0x0128 Die ID code: 2c903414df039b3f ====================================================================== REG_DPLL=0x2413 CNTL_ARM_CLK=0xf0a1 CNTL_CLK=0xff91 CNTL_RST=0xfff3 CNTL_ARM_DIV=0xfff9 ====================================================================== THIS FIRMWARE WAS COMPILED WITHOUT TX SUPPORT!!! Assert DSP into Reset Releasing DSP from Reset Setting some dsp_api.ndb values Setting API NDB parameters DSP Download Status: 0x0001 DSP API Version: 0x0000 0x0000 Finishing download phase DSP Download Status: 0x0002 DSP API Version: 0x3606 0x0000 LOST 1201! L1CTL_RESET_REQ: FULL!L1CTL_PM_REQ start=0 end=124 PM MEAS: ARFCN=0, 32 dBm at baseband, -105 dBm at RF PM MEAS: ARFCN=0, 32 dBm at baseband, -105 dBm at RF ... PM MEAS: ARFCN=98, 36 dBm at baseband, -101 dBm at RF PM MEAS: ARFCN=99, 39 dBm at baseband, -98 dBm at RF PM MEAS: ARFCN=100, 31 dBm at baseband, -106 dBm at RF PM MEAS: ARFCN=101, 30 dBm at baseband, -107 dBm at RF PM MEAS: ARFCN=110, 36 dBm at baseband, -101 dBm at RF PM MEAS: ARFCN=111, 34 dBm at baseband, -103 dBm at RF PM MEAS: ARFCN=112, 31 dBm at baseband, -107 dBm at RF PM MEAS: ARFCN=113, 33 dBm at baseband, -104 dBm at RF ... L1CTL_PM_REQ start=955 end=1023 PM MEAS: ARFCN=955, 26 dBm at baseband, -111 dBm at RF PM MEAS: ARFCN=955, 26 dBm at baseband, -111 dBm at RF PM MEAS: ARFCN=956, 27 dBm at baseband, -110 dBm at RF PM MEAS: ARFCN=957, 26 dBm at baseband, -111 dBm at RF PM MEAS: ARFCN=958, 27 dBm at baseband, -110 dBm at RF PM MEAS: ARFCN=959, 25 dBm at baseband, -112 dBm at RF ... PM MEAS: ARFCN=1020, 37 dBm at baseband, -100 dBm at RF PM MEAS: ARFCN=1021, 41 dBm at baseband, -96 dBm at RF PM MEAS: ARFCN=1022, 31 dBm at baseband, -106 dBm at RF PM MEAS: ARFCN=1023, 42 dBm at baseband, -95 dBm at RF L1CTL_RESET_REQ: FULL!L1CTL_FBSB_REQ (arfcn=121, flags=0x7) Starting FCCH RecognitionFB0 (1735:8): TOA= 9600, Power= -52dBm, Angle= 1218Hz FB1 (1745:8): TOA= 9563, Power= -52dBm, Angle= 174Hz fn_offset=1744 (fn=1745 + attempt=8 + ntdma = 7)m delay=9 (fn_offset=1744 + 11 - fn=1745 - 1 scheduling next FB/SB detection task with delay 9 =>FB @ FNR 1744 fn_offset=1744 qbits=3068 Synchronize_TDMA LOST 3054! What would this LOST 3054! say ? It does not sound good anyway, but at this point I am not skilled enough to read OsmocomBB logs. On the other side, in the ./mobile terminal I have something like this : <0002> gsm322.c:3099 (ms 1) Event 'EVENT_SWITCH_ON' for automatic PLMN selection in state 'A0 null' <000d> gsm322.c:1056 SIM is removed <0002> gsm322.c:1057 SIM is removed <0002> gsm322.c:512 new state 'A0 null' -> 'A6 no SIM inserted' <0003> gsm322.c:3319 (ms 1) Event 'EVENT_SWITCH_ON' for Cell selection in state 'C0 null' <0003> gsm322.c:2992 Switch on without SIM. <0003> gsm322.c:541 new state 'C0 null' -> 'C6 any cell selection' <0003> gsm322.c:2405 Getting PM for frequency 0 twice. Overwriting the first! Please fix prim_pm.c <0003> gsm322.c:2416 Found signal (frequency 2 rxlev -105 (5)) <0003> gsm322.c:2416 Found signal (frequency 3 rxlev -106 (4)) <0003> gsm322.c:2416 Found signal (frequency 4 rxlev -86 (24)) <0003> gsm322.c:2416 Found signal (frequency 5 rxlev -68 (42)) <0003> gsm322.c:2416 Found signal (frequency 6 rxlev -86 (24)) ... <0003> gsm322.c:2405 Getting PM for frequency 512 twice. Overwriting the first! Please fix prim_pm.c <0003> gsm322.c:2416 Found signal (frequency 512 rxlev -93 (17)) <0003> gsm322.c:2416 Found signal (frequency 516 rxlev -90 (20)) ... <0003> gsm322.c:2416 Found signal (frequency 1023 rxlev -95 (15)) <0003> gsm322.c:2349 Found 201 frequencies. <0003> gsm322.c:258 Sync to ARFCN=121 rxlev=-54 (No sysinfo yet, ccch mode NONE) <0002> gsm322.c:3099 (ms 1) Event 'EVENT_USER_RESEL' for automatic PLMN selection in state 'A6 no SIM inserted' Can somebody explain me what the hell is happening here ? I am watching all these nice Harald's presentations, like one here : http://www.youtube.com/watch?v=H7rNKZdASBE, but I am not obtaining list of cells like presented to which I can synchronize to. Actually, show cell is giving me : OsmocomBB> show cell 1 arfcn |MCC |MNC |LAC |cell ID|forb.LA|prio |min-db |max-pwr|rx-lev -------+-------+-------+-------+-------+-------+-------+-------+-------+------- OsmocomBB> As you can see, I am pretty much lost here and I would highly appreciate helping hand. Thanks and best regards, Drasko

12 years, 10 months

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[PATCH 1/2] mtk: uart: remove forgotten calypso-include

by Wolfram Sang

Dunno how that survived... Signed-off-by: Wolfram Sang <wolfram(a)the-dreams.de> --- src/target/firmware/board/mediatek/uart.c | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/src/target/firmware/board/mediatek/uart.c b/src/target/firmware/board/mediatek/uart.c index ff82245..8e86b20 100644 --- a/src/target/firmware/board/mediatek/uart.c +++ b/src/target/firmware/board/mediatek/uart.c @@ -36,8 +36,6 @@ #include <comm/sercomm.h> -#include <calypso/irq.h> - /* MT622x */ #if 0 #define BASE_ADDR_UART1 0x80130000 -- 1.7.2.5

12 years, 10 months

2
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Re: target/firmware/board/compal_e88/loader.compalram.bin T191 cable out of order

by Uli Kleemann

Hi Konrad, sorry for that but anyway thanks for your advice with the software. Which software would you like to recommend to fix that? Regards, -- Uli Kleemann

12 years, 10 months

1
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mobile crashes

by weberbe＠ee.ethz.ch

Hi guys I just run into a problem and was wondering whether anybody has experienced the same: When I start mobile with GSMTAB support (./mobile -i localhost) it crashes immediately after the first GSMTAB packet was sent. Any ideas or remedies? I compiled the current master branch and am using Ubuntu 11.04 Ben

12 years, 10 months

4
6
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Nokia 3310 tracing

by Duncan Salerno

Hi, I've put together a small program that puts Nokia 3310 phones into debug mode (via serial/USB cable) and forwards all sent/received GSM messages and SIM APDUs via GSMTAP to be viewed realtime in Wireshark. This allows you to see the message flows for a real phone on a real network. Nokia 3310's are very cheap and easy to come by, so should appeal to a wide audience. Thought osmocom might be a good home for this utility - could it go into git, and a short page on bb.osmocom.org? Duncan

12 years, 11 months

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hmm, sorry, data cable question

by labad jala

Hello techies! I am new to the list and I acquired a c139. I'd like to buy a rs232/jack 2,5mm named t191 flash (and not unlock) cable. They look 100% the same (even stickers). Is this important? I understand that I have also to use a rs232/usb adapter. The one I have (U232P9 with link/tx/rx leds) gives +/-9,4 v. So my concern is to not fry the Moto..Any advise welcome. Cheers.

12 years, 11 months

8
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Infineon PMB 6277 Chip

by Axel Walsleben

hi list, does anybody knew a device that uses an Infineon PMB 6277 chip ? it is a quad band rf edge receiver chip. i got a full datasheet for it. ;) thanks axel

12 years, 11 months

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Re: osmocon compal_e88/loader.compalram.bin

by Uli Kleemann

I took out the battery and I got that: got 2 bytes from modem, data looks like: 3c 00 <. got 1 bytes from modem, data looks like: 00 . got 1 bytes from modem, data looks like: 00 . got 1 bytes from modem, data looks like: 00 . got 1 bytes from modem, data looks like: 00 . got 1 bytes from modem, data looks like: 00 . got 1 bytes from modem, data looks like: 00 . So I took out the SIM Card, too but nothing changed. 2011/5/25, eisencah eisenach <wbg_1000(a)yahoo.com>: > Try taking out the battery too. > > --- On Wed, 5/25/11, Uli Kleemann <uli.radiotux(a)googlemail.com> wrote: > > From: Uli Kleemann <uli.radiotux(a)googlemail.com> > Subject: Re: osmocon compal_e88/loader.compalram.bin > To: "Gianni Tedesco" <gianni(a)scaramanga.co.uk> > Cc: baseband-devel(a)lists.osmocom.org > Date: Wednesday, May 25, 2011, 7:48 PM > > Hi Gianni, > > Many thanks for your answer. Yes I did press the power button several > times, shortly. > > All I got all I still get is this: > > /install/osmocom-bb/src/host/osmocon$ ./osmocon -p /dev/ttyUSB0 -m > c123xor ../../target/firmware/board/compal_e88/loader.compalram.bin > got 2 bytes from modem, data looks like: fe 00 .. > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > got 1 bytes from modem, data looks like: 00 . > > Regards, > > Uli > > 2011/5/24, Gianni Tedesco <gianni(a)scaramanga.co.uk>: >> On Mon, 2011-05-23 at 13:43 +0200, Uli Kleemann wrote: >>> Hi fellows, >>> >>> I am new at osmocon and I would like to ask fpr some help about >>> flashing the firmware on my C118. >>> >>> I build the software as described on Ubuntu11.0.4 using gnuarm-3.4.3. >>> I use the Motorola T191 serial-cable on an Prolific Technology, Inc. >>> PL2303 Serial Port USB-Serial adapter. (module USB-serial is loaded) >>> >>> when I startosmocon like this: >>> ./osmocon -p /dev/ttyUSB0 -m c123xor >>> ../../target/firmware/board/compal_e88/loader.compalram.bin >>> >>> all I get is that: >>> >>> got 2 bytes from modem, data looks like: fe 00 .. >>> got 1 bytes from modem, data looks like: 00 . >>> got 1 bytes from modem, data looks like: 00 . >>> got 1 bytes from modem, data looks like: 00 . >>> got 1 bytes from modem, data looks like: 00 . >>> got 1 bytes from modem, data looks like: 00 . >>> got 1 bytes from modem, data looks like: 00 . >> >> Just looks like noise from plugging the cable in to the phone. >> >>> Can anybody give me an advice how to fix that? >> >> Did you press the power button on the phone? Just a quick tap is >> required, not a long press like you would normally do to turn it on. >> >> Gianni >> >> > > > -- > Uli Kleemann > > -- Uli Kleemann

12 years, 11 months

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1
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osmocon compal_e88/loader.compalram.bin

by Uli Kleemann

Hi fellows, I am new at osmocon and I would like to ask fpr some help about flashing the firmware on my C118. I build the software as described on Ubuntu11.0.4 using gnuarm-3.4.3. I use the Motorola T191 serial-cable on an Prolific Technology, Inc. PL2303 Serial Port USB-Serial adapter. (module USB-serial is loaded) when I startosmocon like this: ./osmocon -p /dev/ttyUSB0 -m c123xor ../../target/firmware/board/compal_e88/loader.compalram.bin all I get is that: got 2 bytes from modem, data looks like: fe 00 .. got 1 bytes from modem, data looks like: 00 . got 1 bytes from modem, data looks like: 00 . got 1 bytes from modem, data looks like: 00 . got 1 bytes from modem, data looks like: 00 . got 1 bytes from modem, data looks like: 00 . got 1 bytes from modem, data looks like: 00 . Can anybody give me an advice how to fix that? Thanks in advance Uli -- Uli Kleemann

12 years, 11 months

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Re: Nuttx for Calypso

by Gregory Nutt

Hi, Let me volunteer suggestions to at some of your questions. > Also (unrelated to the patch), somethings that I think should be > discussed/addressed soon are: > > - How we will handle the boards in nuttx (including variants like > US/EU version of the same phone) Nuttx is designed to support a hiearchical configuration: processor family, chips in the family, boards that host the chips, and board software configurations. NuttX is configured with .config file. In that file you specify the family (ARM), the chip (Calypso), and the board (also Calypso now?). The family corresponds to a directory under arch/ (arch/arm) and the chip corresponds to sub-directories under arch/arm/src and arch/arm/include (arch/arm/src/calypso and arch/arm/include/calypso). * arch/arm/include holds general ARM header files * arch/arm/include/calypso holds calypso specific header files * arch/arm/src/calypso holds calypso specific source files Boards are represented by directories under configs/. Right now, I think there is only a configs/compal_e99. * configs/compal_e99/include holds Compal E99 specific header files * configs/compal_e99/src holds Compal E99 specific header files Other directories under configs/compal_e99 can hold different software configurations for the same board. For example, configs/compal_e99/ostest holds the make logic for the OS test; configs/compal_e99/nsh would hold the NuttShell (NSH) make configuration files, etc. The .config file, for example, is on of the software configuration files in those directories (it is call defconfig before it is copied to the top-level directory as .config). You can see these settings in the .config/defconfig file: CONFIG_ARCH=arm >CONFIG_ARCH_ARM=y >CONFIG_ARCH_ARM7TDMI=y >CONFIG_ARCH_CHIP=calypso >CONFIG_ARCH_CHIP_CALYPSO=y >CONFIG_ARCH_BOARD=compal_e99 >CONFIG_ARCH_BOARD_COMPALE99=y When the OS is configured, the top-level Makefile uses these definitions to create symbolic links: * arch/arm/src/chip will refer to arch/arm/src/calypso * arch/arm/include/chip will refer to arch/arm/include/calypso * arch/arm/include/board will refer to configs/compal_e99/include * arch/arm/src/board will refer to configs/compal_e99/src. And * include/arch will refer to to arch/arm/include So you can include ARM general header, calypso-specific, and board-specific header files like: #include <arch/arch.h> // architecture (ARM) specific header files >#include <arch/chip/chip.h> // Chip (calypso) specific header files >#include <arch/board/board.h> // Board specific header files So, if you want to support the same processor (calypso) on a different board, say boardX, you could create a directory: configs/boardX And put boardX specific header files and source files in: configs/boardX/include >configs/boardX/src And put boardX software configurations under config/boardX/configY > - How we will handle our different ram config (boot from ram / flash), > can we use the loader to load part of the SDRAM if we don't fit in > SRAM completely ? I would think that these would correspond to different software build configuration directories under configs/BoardX. You also ask several memory related questions that I can't really answer. I think there may be some additional memory management requirements here: > - How we will handle the memory zones (SRAM / SDRAM / Flash / XIP from > flash (or just .rodata ?)) > - Memory allocator (handling zones ...). I think that'd be something > very useful. Currently we can only allocate msgb and that's a little > limiting. Right now, the memory allocator can handle multiple, discontinuous regions of memory. There is an interface called mm_addregion() that can always add a new block of memory to the memory pool. But there is mechanism now to select which region memory will be allocated from. malloc() is the only allocator for user programs. It will allocate memory only from the best fitting free memory chunk, but does not take into account any properties of the memory. Greg

12 years, 11 months

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[PATCH 4/4] Initial support for Nuttx on TI Calypso platform

by l--putt

12 years, 11 months

1
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[PATCH 3/4] Initial support for Nuttx on TI Calypso platform

by l--putt

12 years, 11 months

1
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[PATCH 2/4] Initial support for Nuttx on TI Calypso platform

by l--putt

12 years, 11 months

1
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[PATCH 1/4] Initial support for Nuttx on TI Calypso platform

by l--putt

12 years, 11 months

1
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re : hmmm, data cable question

by labad jala

Thanks again. I measured 4v using a USB/RS232 (U232-P9) adapatator attached to a laptop and also a desktop + "T191" that looks exactly like http://www.cellcorner.com/xshp/unlock-phone-codes/motorola-t190-t191-t193-u….<http://www.cellcorner.com/xshp/unlock-phone-codes/motorola-t190-t191-t193-u…>Please, did someone buy this one and had good voltage and results? Regards.

12 years, 11 months

2
1
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[PATCH 4/4] Initial support for Nuttx on TI Calypso platform: Memory initialization Switch lights in ostest example

by Stefan Richter

Now, nuttx.bin should build and run on your phone. No console output yet but turns on backlight of compal E99 and off when ostest has finished. --- apps/examples/ostest/main.c | 50 ++++++++++++++++++ nuttx/arch/arm/src/calypso/calypso_heap.c | 81 +++++++++++++++++++++++++++++ nuttx/arch/arm/src/common/up_internal.h | 3 +- 3 files changed, 133 insertions(+), 1 deletions(-) create mode 100644 nuttx/arch/arm/src/calypso/calypso_heap.c diff --git a/apps/examples/ostest/main.c b/apps/examples/ostest/main.c index 327ec60..641c3c9 100644 --- a/apps/examples/ostest/main.c +++ b/apps/examples/ostest/main.c @@ -33,6 +33,53 @@ * ****************************************************************************/ +/* + * Debug stuff for Compal E99 + * taken from Osmocom-BB init.c + * + * Turn on backlight on entry and off when done + */ + +#include <stdint.h> +#include <arch/calypso/memory.h> + +#define ARMIO_LATCH_OUT 0xfffe4802 +#define IO_CNTL_REG 0xfffe4804 +#define ASIC_CONF_REG 0xfffef008 + +static void lights_on(void) +{ + uint16_t reg; + + reg = readw(ASIC_CONF_REG); + /* LCD Set I/O(3) / SA0 to I/O(3) mode */ + reg &= ~( (1 << 12) | (1 << 10) | (1 << 7) | (1 << 1)) ; + /* don't set function pins to I2C Mode, C155 uses UWire */ + /* TWL3025: Set SPI+RIF RX clock to rising edge */ + reg |= (1 << 13) | (1 << 14); + writew(reg, ASIC_CONF_REG); + + /* LCD Set I/O(3) to output mode and enable C155 backlight (IO1) */ + /* FIXME: Put the display backlight control to backlight.c */ + reg = readw(IO_CNTL_REG); + reg &= ~( (1 << 3) | (1 << 1)); + writew(reg, IO_CNTL_REG); + + /* LCD Set I/O(3) output low */ + reg = readw(ARMIO_LATCH_OUT); + reg &= ~(1 << 3); + reg |= (1 << 1); + writew(reg, ARMIO_LATCH_OUT); +} + +static void lights_off(void) +{ + uint16_t reg; + reg = readw(ARMIO_LATCH_OUT); + reg &= ~(1 << 1); + writew(reg, ARMIO_LATCH_OUT); +} + /**************************************************************************** * Included Files ****************************************************************************/ @@ -421,6 +468,7 @@ static int user_main(int argc, char *argv[]) #endif } printf("user_main: Exitting\n"); + lights_off(); return 0; } @@ -457,6 +505,8 @@ int user_start(int argc, char *argv[]) { int result; + lights_on(); + /* Verify that stdio works first */ stdio_test(); diff --git a/nuttx/arch/arm/src/calypso/calypso_heap.c b/nuttx/arch/arm/src/calypso/calypso_heap.c new file mode 100644 index 0000000..d35a76f --- /dev/null +++ b/nuttx/arch/arm/src/calypso/calypso_heap.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * calypso_heap.c + * Initialize memory interfaces of Calypso MCU + * + * Copyright (C) 2011 Stefan Richter <ichgeh(a)l--putt.de> + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <sys/types.h> +#include <debug.h> + +#include <nuttx/arch.h> +#include <arch/board/board.h> + +#include <arch/calypso/clock.h> +#include <arch/calypso/timer.h> + +#include "up_arch.h" +#include "up_internal.h" + +/**************************************************************************** + * Name: up_addregion + * + * Description: + * This function is called right after basics are initialized and right + * before IRQ system setup. + * + ****************************************************************************/ + +void up_addregion(void) +{ + /* Disable watchdog in first non-common function */ + wdog_enable(0); + + // XXX: change to initialization of extern memory with save defaults + /* Configure memory interface */ + calypso_mem_cfg(CALYPSO_nCS0, 3, CALYPSO_MEM_16bit, 1); + calypso_mem_cfg(CALYPSO_nCS1, 3, CALYPSO_MEM_16bit, 1); + calypso_mem_cfg(CALYPSO_nCS2, 5, CALYPSO_MEM_16bit, 1); + calypso_mem_cfg(CALYPSO_nCS3, 5, CALYPSO_MEM_16bit, 1); + calypso_mem_cfg(CALYPSO_CS4, 0, CALYPSO_MEM_8bit, 1); + calypso_mem_cfg(CALYPSO_nCS6, 0, CALYPSO_MEM_32bit, 1); + calypso_mem_cfg(CALYPSO_nCS7, 0, CALYPSO_MEM_32bit, 0); + + /* Set VTCXO_DIV2 = 1, configure PLL for 104 MHz and give ARM half of that */ + calypso_clock_set(2, CALYPSO_PLL13_104_MHZ, ARM_MCLK_DIV_2); + + /* Configure the RHEA bridge with some sane default values */ + calypso_rhea_cfg(0, 0, 0xff, 0, 1, 0, 0); +} diff --git a/nuttx/arch/arm/src/common/up_internal.h b/nuttx/arch/arm/src/common/up_internal.h index 803a656..21c34e2 100644 --- a/nuttx/arch/arm/src/common/up_internal.h +++ b/nuttx/arch/arm/src/common/up_internal.h @@ -64,9 +64,10 @@ #if CONFIG_NFILE_DESCRIPTORS == 0 || defined(CONFIG_DEV_LOWCONSOLE) # undef CONFIG_USE_SERIALDRIVER # undef CONFIG_USE_EARLYSERIALINIT + #elif defined(CONFIG_DEV_CONSOLE) && CONFIG_NFILE_DESCRIPTORS > 0 # define CONFIG_USE_SERIALDRIVER 1 -# define CONFIG_USE_EARLYSERIALINIT 1 +# undef CONFIG_USE_EARLYSERIALINIT #endif /* Check if an interrupt stack size is configured */ -- 1.7.1

12 years, 11 months

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[PATCH 3/4] Initial support for Nuttx on TI Calypso platform: IRQ support for Calypso Main patches Osmocom code to match Nuttx API

by Stefan Richter

--- nuttx/arch/arm/include/calypso/irq.h | 67 +++++++ nuttx/arch/arm/src/calypso/calypso_irq.c | 300 ++++++++++++++++++++++++++++++ 2 files changed, 367 insertions(+), 0 deletions(-) create mode 100644 nuttx/arch/arm/include/calypso/irq.h create mode 100644 nuttx/arch/arm/src/calypso/calypso_irq.c diff --git a/nuttx/arch/arm/include/calypso/irq.h b/nuttx/arch/arm/include/calypso/irq.h new file mode 100644 index 0000000..1333a6e --- /dev/null +++ b/nuttx/arch/arm/include/calypso/irq.h @@ -0,0 +1,67 @@ +/**************************************************************************** + * arch/arm/include/calypso/irq.h + * Driver for Calypso IRQ controller + * + * (C) 2010 by Harald Welte <laforge(a)gnumonks.org> + * (C) 2011 by Stefan Richter <ichgeh(a)l--putt.de> + * + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_IRQ_H +#error "This file should never be included directly! Use <nuttx/irq.h>" +#endif + +#ifndef _CALYPSO_IRQ_H +#define _CALYPSO_IRQ_H + +#ifndef __ASSEMBLY__ + +enum irq_nr { + IRQ_WATCHDOG = 0, + IRQ_TIMER1 = 1, + IRQ_TIMER2 = 2, + IRQ_TSP_RX = 3, + IRQ_TPU_FRAME = 4, + IRQ_TPU_PAGE = 5, + IRQ_SIMCARD = 6, + IRQ_UART_MODEM = 7, + IRQ_KEYPAD_GPIO = 8, + IRQ_RTC_TIMER = 9, + IRQ_RTC_ALARM_I2C = 10, + IRQ_ULPD_GAUGING = 11, + IRQ_EXTERNAL = 12, + IRQ_SPI = 13, + IRQ_DMA = 14, + IRQ_API = 15, + IRQ_SIM_DETECT = 16, + IRQ_EXTERNAL_FIQ = 17, + IRQ_UART_IRDA = 18, + IRQ_ULPD_GSM_TIMER = 19, + IRQ_GEA = 20, + _NR_IRQS +}; + +#endif /* __ASSEMBLY__ */ + +/* Don't use _NR_IRQS!!! Won't work in preprocessor... */ +#define NR_IRQS 21 + +#define IRQ_SYSTIMER IRQ_TIMER2 + +#endif /* _CALYPSO_IRQ_H */ diff --git a/nuttx/arch/arm/src/calypso/calypso_irq.c b/nuttx/arch/arm/src/calypso/calypso_irq.c new file mode 100644 index 0000000..993e475 --- /dev/null +++ b/nuttx/arch/arm/src/calypso/calypso_irq.c @@ -0,0 +1,300 @@ +/**************************************************************************** + * arch/arm/src/calypso/calypso_irq.c + * Driver for Calypso IRQ controller + * + * (C) 2010 by Harald Welte <laforge(a)gnumonks.org> + * (C) 2011 by Stefan Richter <ichgeh(a)l--putt.de> + * + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include <nuttx/config.h> + +#include <stdio.h> +#include <stdint.h> +#include <nuttx/irq.h> +#include <nuttx/arch.h> +#include <arch/calypso/memory.h> + +#include "arm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define BASE_ADDR_IRQ 0xfffffa00 +#define BASE_ADDR_IBOOT_EXC 0x0080001C + +enum irq_reg { + IT_REG1 = 0x00, + IT_REG2 = 0x02, + MASK_IT_REG1 = 0x08, + MASK_IT_REG2 = 0x0a, + IRQ_NUM = 0x10, + FIQ_NUM = 0x12, + IRQ_CTRL = 0x14, +}; + +#define ILR_IRQ(x) (0x20 + (x*2)) +#define IRQ_REG(x) ((void *)BASE_ADDR_IRQ + (x)) + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uint32_t *current_regs; +extern uint32_t _exceptions; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint8_t default_irq_prio[] = { + [IRQ_WATCHDOG] = 0xff, + [IRQ_TIMER1] = 0xff, + [IRQ_TIMER2] = 0xff, + [IRQ_TSP_RX] = 0, + [IRQ_TPU_FRAME] = 3, + [IRQ_TPU_PAGE] = 0xff, + [IRQ_SIMCARD] = 0xff, + [IRQ_UART_MODEM] = 8, + [IRQ_KEYPAD_GPIO] = 4, + [IRQ_RTC_TIMER] = 9, + [IRQ_RTC_ALARM_I2C] = 10, + [IRQ_ULPD_GAUGING] = 2, + [IRQ_EXTERNAL] = 12, + [IRQ_SPI] = 0xff, + [IRQ_DMA] = 0xff, + [IRQ_API] = 0xff, + [IRQ_SIM_DETECT] = 0, + [IRQ_EXTERNAL_FIQ] = 7, + [IRQ_UART_IRDA] = 2, + [IRQ_ULPD_GSM_TIMER] = 1, + [IRQ_GEA] = 0xff, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void _irq_enable(enum irq_nr nr, int enable) +{ + uint16_t *reg = IRQ_REG(MASK_IT_REG1); + uint16_t val; + + if (nr > 15) { + reg = IRQ_REG(MASK_IT_REG2); + nr -= 16; + } + + val = readw(reg); + if (enable) + val &= ~(1 << nr); + else + val |= (1 << nr); + writew(val, reg); +} + +static void set_default_priorities(void) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(default_irq_prio); i++) { + uint16_t val; + uint8_t prio = default_irq_prio[i]; + if (prio > 31) + prio = 31; + + val = readw(IRQ_REG(ILR_IRQ(i))); + val &= ~(0x1f << 2); + val |= prio << 2; + writew(val, IRQ_REG(ILR_IRQ(i))); + } +} + +/* Install the exception handlers to where the ROM loader jumps */ +static void calypso_exceptions_install(void) +{ + uint32_t *exceptions_dst = (uint32_t *) BASE_ADDR_IBOOT_EXC; + uint32_t *exceptions_src = &_exceptions; + int i; + + for (i = 0; i < 7; i++) + *exceptions_dst++ = *exceptions_src++; + +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + * + * Description: + * Setup the IRQ and FIQ controllers + * + ****************************************************************************/ + +void up_irqinitialize(void) +{ + /* Prepare hardware */ + calypso_exceptions_install(); + current_regs = NULL; + + /* Switch to internal ROM */ + calypso_bootrom(1); + + /* set default priorities */ + set_default_priorities(); + + /* mask all interrupts off */ + writew(0xffff, IRQ_REG(MASK_IT_REG1)); + writew(0xffff, IRQ_REG(MASK_IT_REG2)); + + /* clear all pending interrupts */ + writew(0, IRQ_REG(IT_REG1)); + writew(0, IRQ_REG(IT_REG2)); + + /* enable interrupts globally to the ARM core */ +#ifndef CONFIG_SUPPRESS_INTERRUPTS + irqrestore(SVC_MODE | PSR_F_BIT); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + if((unsigned)irq < NR_IRQS) + _irq_enable(irq, 0); +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + if((unsigned)irq < NR_IRQS) + _irq_enable(irq, 1); +} + +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + ****************************************************************************/ + +#ifndef CONFIG_ARCH_IRQPRIO +int up_prioritize_irq(int nr, int prio) +{ + uint16_t val; + + if (prio == -1) + prio = default_irq_prio[nr]; + + if (prio > 31) + prio = 31; + + val = prio << 2; +/* + if (edge) + val |= 0x02; + if (fiq) + val |= 0x01; +*/ + writew(val, IRQ_REG(ILR_IRQ(nr))); + + return 0; // XXX: what's the return??? +} +#endif + +/**************************************************************************** + * Entry point for interrupts + ****************************************************************************/ + +void up_decodeirq(uint32_t *regs) +{ + uint8_t num, tmp; + uint32_t *saved_regs; + + /* XXX: What is this??? + * Passed to but ignored in IRQ handlers + * Only valid meaning is apparently non-NULL == IRQ context */ + saved_regs = (uint32_t *)current_regs; + current_regs = regs; + + /* Detect & deliver the IRQ */ + num = readb(IRQ_REG(IRQ_NUM)) & 0x1f; + irq_dispatch(num, regs); + + /* Start new IRQ agreement */ + tmp = readb(IRQ_REG(IRQ_CTRL)); + tmp |= 0x01; + writeb(tmp, IRQ_REG(IRQ_CTRL)); + + current_regs = saved_regs; +} + +/**************************************************************************** + * Entry point for FIQs + ****************************************************************************/ + +void calypso_fiq(void) +{ + uint8_t num, tmp; + uint32_t *regs; + + /* XXX: What is this??? + * Passed to but ignored in IRQ handlers + * Only valid meaning is apparently non-NULL == IRQ context */ + regs = (uint32_t *)current_regs; + current_regs = (uint32_t *)&num; + + /* Detect & deliver like an IRQ but we are in FIQ context */ + num = readb(IRQ_REG(FIQ_NUM)) & 0x1f; + irq_dispatch(num, regs); + + /* Start new FIQ agreement */ + tmp = readb(IRQ_REG(IRQ_CTRL)); + tmp |= 0x02; + writeb(tmp, IRQ_REG(IRQ_CTRL)); + + current_regs = regs; +} -- 1.7.1

12 years, 11 months

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[PATCH 2/4] Initial support for Nuttx on TI Calypso platform: Import clock and timer related files Osmocom Modify timer.c to Nuttx API

by Stefan Richter

--- nuttx/arch/arm/include/calypso/clock.h | 67 +++++++++ nuttx/arch/arm/include/calypso/timer.h | 25 ++++ nuttx/arch/arm/src/calypso/calypso_timer.c | 205 ++++++++++++++++++++++++++++ nuttx/arch/arm/src/calypso/clock.c | 202 +++++++++++++++++++++++++++ 4 files changed, 499 insertions(+), 0 deletions(-) create mode 100644 nuttx/arch/arm/include/calypso/clock.h create mode 100644 nuttx/arch/arm/include/calypso/timer.h create mode 100644 nuttx/arch/arm/src/calypso/calypso_timer.c create mode 100644 nuttx/arch/arm/src/calypso/clock.c diff --git a/nuttx/arch/arm/include/calypso/clock.h b/nuttx/arch/arm/include/calypso/clock.h new file mode 100644 index 0000000..abcfde1 --- /dev/null +++ b/nuttx/arch/arm/include/calypso/clock.h @@ -0,0 +1,67 @@ +#ifndef _CALYPSO_CLK_H +#define _CALYPSO_CLK_H + +#include <stdint.h> + +#define CALYPSO_PLL26_52_MHZ ((2 << 8) | 0) +#define CALYPSO_PLL26_86_7_MHZ ((10 << 8) | 2) +#define CALYPSO_PLL26_87_MHZ ((3 << 8) | 0) +#define CALYPSO_PLL13_104_MHZ ((8 << 8) | 0) + +enum mclk_div { + _ARM_MCLK_DIV_1 = 0, + ARM_MCLK_DIV_1 = 1, + ARM_MCLK_DIV_2 = 2, + ARM_MCLK_DIV_3 = 3, + ARM_MCLK_DIV_4 = 4, + ARM_MCLK_DIV_5 = 5, + ARM_MCLK_DIV_6 = 6, + ARM_MCLK_DIV_7 = 7, + ARM_MCLK_DIV_1_5 = 0x80 | 1, + ARM_MCLK_DIV_2_5 = 0x80 | 2, +}; + +void calypso_clock_set(uint8_t vtcxo_div2, uint16_t inp, enum mclk_div mclk_div); +void calypso_pll_set(uint16_t inp); +void calypso_clk_dump(void); + +/* CNTL_RST */ +enum calypso_rst { + RESET_DSP = (1 << 1), + RESET_EXT = (1 << 2), + RESET_WDOG = (1 << 3), +}; + +void calypso_reset_set(enum calypso_rst calypso_rst, int active); +int calypso_reset_get(enum calypso_rst); + +enum calypso_bank { + CALYPSO_nCS0 = 0, + CALYPSO_nCS1 = 2, + CALYPSO_nCS2 = 4, + CALYPSO_nCS3 = 6, + CALYPSO_nCS7 = 8, + CALYPSO_CS4 = 0xa, + CALYPSO_nCS6 = 0xc, +}; + +enum calypso_mem_width { + CALYPSO_MEM_8bit = 0, + CALYPSO_MEM_16bit = 1, + CALYPSO_MEM_32bit = 2, +}; + +void calypso_mem_cfg(enum calypso_bank bank, uint8_t ws, + enum calypso_mem_width width, int we); + +/* Enable or disable the internal bootrom mapped to 0x0000'0000 */ +void calypso_bootrom(int enable); + +/* Enable or disable the debug unit */ +void calypso_debugunit(int enable); + +/* configure the RHEA bus bridge[s] */ +void calypso_rhea_cfg(uint8_t fac0, uint8_t fac1, uint8_t timeout, + uint8_t ws_h, uint8_t ws_l, uint8_t w_en0, uint8_t w_en1); + +#endif /* _CALYPSO_CLK_H */ diff --git a/nuttx/arch/arm/include/calypso/timer.h b/nuttx/arch/arm/include/calypso/timer.h new file mode 100644 index 0000000..694e4eb --- /dev/null +++ b/nuttx/arch/arm/include/calypso/timer.h @@ -0,0 +1,25 @@ +#ifndef _CAL_TIMER_H +#define _CAL_TIMER_H + +/* Enable or Disable a timer */ +void hwtimer_enable(int num, int on); + +/* Configure pre-scaler and if timer is auto-reload */ +void hwtimer_config(int num, uint8_t pre_scale, int auto_reload); + +/* Load a timer with the given value */ +void hwtimer_load(int num, uint16_t val); + +/* Read the current timer value */ +uint16_t hwtimer_read(int num); + +/* Enable or disable the watchdog */ +void wdog_enable(int on); + +/* Reset cpu using watchdog */ +void wdog_reset(void); + +/* power up the timers */ +void hwtimer_init(void); + +#endif /* _CAL_TIMER_H */ diff --git a/nuttx/arch/arm/src/calypso/calypso_timer.c b/nuttx/arch/arm/src/calypso/calypso_timer.c new file mode 100644 index 0000000..0191c0c --- /dev/null +++ b/nuttx/arch/arm/src/calypso/calypso_timer.c @@ -0,0 +1,205 @@ +/**************************************************************************** + * arch/arm/src/calypso/calypso_timer.c + * Calypso DBB internal Timer Driver + * + * (C) 2010 by Harald Welte <laforge(a)gnumonks.org> + * (C) 2011 by Stefan Richter <ichgeh(a)l--putt.de> + * + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + ****************************************************************************/ + +#include <stdio.h> +#include <stdint.h> +#include <nuttx/arch.h> + +#include <arch/calypso/defines.h> +#include <arch/calypso/memory.h> +#include <arch/calypso/timer.h> + + +#define BASE_ADDR_TIMER 0xfffe3800 +#define TIMER2_OFFSET 0x3000 + +#define TIMER_REG(n, m) (((n)-1) ? (BASE_ADDR_TIMER + TIMER2_OFFSET + (m)) : (BASE_ADDR_TIMER + (m))) + +enum timer_reg { + CNTL_TIMER = 0x00, + LOAD_TIMER = 0x02, + READ_TIMER = 0x04, +}; + +enum timer_ctl { + CNTL_START = (1 << 0), + CNTL_AUTO_RELOAD = (1 << 1), + CNTL_CLOCK_ENABLE = (1 << 5), +}; + +/* Regular Timers (1 and 2) */ + +void hwtimer_enable(int num, int on) +{ + uint8_t ctl; + + if (num < 1 || num > 2) { + printf("Unknown timer %u\n", num); + return; + } + + ctl = readb(TIMER_REG(num, CNTL_TIMER)); + if (on) + ctl |= CNTL_START|CNTL_CLOCK_ENABLE; + else + ctl &= ~CNTL_START; + writeb(ctl, TIMER_REG(num, CNTL_TIMER)); +} + +void hwtimer_config(int num, uint8_t pre_scale, int auto_reload) +{ + uint8_t ctl; + + ctl = (pre_scale & 0x7) << 2; + if (auto_reload) + ctl |= CNTL_AUTO_RELOAD; + + writeb(ctl, TIMER_REG(num, CNTL_TIMER)); +} + +void hwtimer_load(int num, uint16_t val) +{ + writew(val, TIMER_REG(num, LOAD_TIMER)); +} + +uint16_t hwtimer_read(int num) +{ + uint8_t ctl = readb(TIMER_REG(num, CNTL_TIMER)); + + /* somehow a read results in an abort */ + if ((ctl & (CNTL_START|CNTL_CLOCK_ENABLE)) != (CNTL_START|CNTL_CLOCK_ENABLE)) + return 0xFFFF; + return readw(TIMER_REG(num, READ_TIMER)); +} + +/************************************************************ + * Watchdog Timer + ************************************************************/ + +#define BASE_ADDR_WDOG 0xfffff800 +#define WDOG_REG(m) (BASE_ADDR_WDOG + m) + +enum wdog_reg { + WD_CNTL_TIMER = CNTL_TIMER, + WD_LOAD_TIMER = LOAD_TIMER, + WD_READ_TIMER = 0x02, + WD_MODE = 0x04, +}; + +enum wdog_ctl { + WD_CTL_START = (1 << 7), + WD_CTL_AUTO_RELOAD = (1 << 8) +}; + +enum wdog_mode { + WD_MODE_DIS_ARM = 0xF5, + WD_MODE_DIS_CONFIRM = 0xA0, + WD_MODE_ENABLE = (1 << 15) +}; + +#define WD_CTL_PRESCALE(value) (((value)&0x07) << 9) + +static void wdog_irq(__unused enum irq_nr nr) +{ + puts("=> WATCHDOG\n"); +} + +void wdog_enable(int on) +{ + if (on) { +#if 0 + irq_config(IRQ_WATCHDOG, 0, 0, 0); + irq_register_handler(IRQ_WATCHDOG, &wdog_irq); + irq_enable(IRQ_WATCHDOG); + writew(WD_MODE_ENABLE, WDOG_REG(WD_MODE)); +#endif + } else { + writew(WD_MODE_DIS_ARM, WDOG_REG(WD_MODE)); + writew(WD_MODE_DIS_CONFIRM, WDOG_REG(WD_MODE)); + } +} + +void wdog_reset(void) +{ +#if 0 + // XXX: this is supposed to reset immediately but does not seem to + writew(0xF5, WDOG_REG(WD_MODE)); + writew(0xFF, WDOG_REG(WD_MODE)); +#else + // enable watchdog + writew(WD_MODE_ENABLE, WDOG_REG(WD_MODE)); + // force expiration + writew(0x0000, WDOG_REG(WD_LOAD_TIMER)); + writew(0x0000, WDOG_REG(WD_LOAD_TIMER)); +#endif +} + +/************************************************************ + * Global Functions + ************************************************************/ + +/************************************************************ + * Function: up_timerisr + * + * Description: + * The timer ISR will perform a variety of services for + * various portions of the systems. + * + ************************************************************/ + +int up_timerisr(int irq, uint32_t *regs) +{ + /* Process timer interrupt */ + + sched_process_timer(); + return 0; +} + +/************************************************************ + * Function: up_timerinit + * + * Description: + * Setup Calypso HW timer 2 to cause system ticks. + * + * This function is called during start-up to initialize + * the timer interrupt. + * + ************************************************************/ + +void up_timerinit(void) +{ + up_disable_irq(IRQ_SYSTIMER); + + /* The timer runs at 13MHz / 32, i.e. 406.25kHz */ + /* 4062 ticks until expiry yields 100Hz interrupt */ + hwtimer_load(2, 4062); + hwtimer_config(2, 0, 1); + hwtimer_enable(2, 1); + + /* Attach and enable the timer interrupt */ + irq_attach(IRQ_SYSTIMER, (xcpt_t)up_timerisr); + up_enable_irq(IRQ_SYSTIMER); +} + diff --git a/nuttx/arch/arm/src/calypso/clock.c b/nuttx/arch/arm/src/calypso/clock.c new file mode 100644 index 0000000..77b4ea5 --- /dev/null +++ b/nuttx/arch/arm/src/calypso/clock.c @@ -0,0 +1,202 @@ +/* Driver for Calypso clock management */ + +/* (C) 2010 by Harald Welte <laforge(a)gnumonks.org> + * + * All Rights Reserved + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + */ + +#include <nuttx/config.h> + +#include <stdint.h> +#include <stdio.h> + +//#define DEBUG +#include <arch/calypso/debug.h> + +#include <arch/calypso/memory.h> +#include <arch/calypso/clock.h> + +#define REG_DPLL 0xffff9800 +#define DPLL_LOCK (1 << 0) +#define DPLL_BREAKLN (1 << 1) +#define DPLL_BYPASS_DIV_SHIFT 2 /* 2 bits */ +#define DPLL_PLL_ENABLE (1 << 4) +#define DPLL_PLL_DIV_SHIFT 5 /* 2 bits */ +#define DPLL_PLL_MULT_SHIFT 7 /* 5 bits */ +#define DPLL_TEST (1 << 12) +#define DPLL_IOB (1 << 13) /* Initialize on break */ +#define DPLL_IAI (1 << 14) /* Initialize after Idle */ + +#define BASE_ADDR_CLKM 0xfffffd00 +#define CLKM_REG(m) (BASE_ADDR_CLKM+(m)) + +enum clkm_reg { + CNTL_ARM_CLK = 0, + CNTL_CLK = 2, + CNTL_RST = 4, + CNTL_ARM_DIV = 8, +}; + +/* CNTL_ARM_CLK */ +#define ARM_CLK_BIG_SLEEP (1 << 0) /* MCU Master Clock enabled? */ +#define ARM_CLK_CLKIN_SEL0 (1 << 1) /* MCU source clock (0 = DPLL output, 1 = VTCXO or CLKIN */ +#define ARM_CLK_CLKIN_SEL (1 << 2) /* 0 = VTCXO or 1 = CLKIN */ +#define ARM_CLK_MCLK_DIV5 (1 << 3) /* enable 1.5 or 2.5 division factor */ +#define ARM_CLK_MCLK_DIV_SHIFT 4 /* 3 bits */ +#define ARM_CLK_DEEP_POWER_SHIFT 8 +#define ARM_CLK_DEEP_SLEEP 12 + +/* CNTL_CLK */ +#define CLK_IRQ_CLK_DIS (1 << 0) /* IRQ clock control (0 always, 1 according ARM_MCLK_EN) */ +#define CLK_BRIDGE_CLK_DIS (1 << 1) +#define CLK_TIMER_CLK_DIS (1 << 2) +#define CLK_DPLL_DIS (1 << 3) /* 0: DPLL is not stopped during SLEEP */ +#define CLK_CLKOUT_EN (1 << 4) /* Enable CLKOUT output pins */ +#define CLK_EN_IDLE3_FLG (1 << 5) /* DSP idle flag control (1 = + * SAM/HOM register forced to HOM when DSP IDLE3) */ +#define CLK_VCLKOUT_DIV2 (1 << 6) /* 1: VCLKOUT-FR is divided by 2 */ +#define CLK_VTCXO_DIV2 (1 << 7) /* 1: VTCXO is dividied by 2 */ + +#define BASE_ADDR_MEMIF 0xfffffb00 +#define MEMIF_REG(x) (BASE_ADDR_MEMIF+(x)) + +enum memif_reg { + API_RHEA_CTL = 0x0e, + EXTRA_CONF = 0x10, +}; + +static void dump_reg16(uint32_t addr, char *name) +{ + printf("%s=0x%04x\n", name, readw(addr)); +} + +void calypso_clk_dump(void) +{ + dump_reg16(REG_DPLL, "REG_DPLL"); + dump_reg16(CLKM_REG(CNTL_ARM_CLK), "CNTL_ARM_CLK"); + dump_reg16(CLKM_REG(CNTL_CLK), "CNTL_CLK"); + dump_reg16(CLKM_REG(CNTL_RST), "CNTL_RST"); + dump_reg16(CLKM_REG(CNTL_ARM_DIV), "CNTL_ARM_DIV"); +} + +void calypso_pll_set(uint16_t inp) +{ + uint8_t mult = inp >> 8; + uint8_t div = inp & 0xff; + uint16_t reg = readw(REG_DPLL); + + reg &= ~0x0fe0; + reg |= (div & 0x3) << DPLL_PLL_DIV_SHIFT; + reg |= (mult & 0x1f) << DPLL_PLL_MULT_SHIFT; + reg |= DPLL_PLL_ENABLE; + + writew(reg, REG_DPLL); +} + +void calypso_reset_set(enum calypso_rst calypso_rst, int active) +{ + uint8_t reg = readb(CLKM_REG(CNTL_RST)); + + if (active) + reg |= calypso_rst; + else + reg &= ~calypso_rst; + + writeb(reg, CLKM_REG(CNTL_RST)); +} + +int calypso_reset_get(enum calypso_rst calypso_rst) +{ + uint8_t reg = readb(CLKM_REG(CNTL_RST)); + + if (reg & calypso_rst) + return 1; + else + return 0; +} + +void calypso_clock_set(uint8_t vtcxo_div2, uint16_t inp, enum mclk_div mclk_div) +{ + uint16_t cntl_clock = readw(CLKM_REG(CNTL_CLK)); + uint16_t cntl_arm_clk = readw(CLKM_REG(CNTL_ARM_CLK)); + + /* First set the vtcxo_div2 */ + cntl_clock &= ~CLK_VCLKOUT_DIV2; + if (vtcxo_div2) + cntl_clock |= CLK_VTCXO_DIV2; + else + cntl_clock &= ~CLK_VTCXO_DIV2; + writew(cntl_clock, CLKM_REG(CNTL_CLK)); + + /* Then configure the MCLK divider */ + cntl_arm_clk &= ~ARM_CLK_CLKIN_SEL0; + if (mclk_div & 0x80) { + mclk_div &= ~0x80; + cntl_arm_clk |= ARM_CLK_MCLK_DIV5; + } else + cntl_arm_clk &= ~ARM_CLK_MCLK_DIV5; + cntl_arm_clk &= ~(0x7 << ARM_CLK_MCLK_DIV_SHIFT); + cntl_arm_clk |= (mclk_div << ARM_CLK_MCLK_DIV_SHIFT); + writew(cntl_arm_clk, CLKM_REG(CNTL_ARM_CLK)); + + /* Then finally set the PLL */ + calypso_pll_set(inp); +} + +void calypso_mem_cfg(enum calypso_bank bank, uint8_t ws, + enum calypso_mem_width width, int we) +{ + writew((ws & 0x1f) | ((width & 3) << 5) | ((we & 1) << 7), + BASE_ADDR_MEMIF + bank); +} + +void calypso_bootrom(int enable) +{ + uint16_t conf = readw(MEMIF_REG(EXTRA_CONF)); + + conf |= (3 << 8); + + if (enable) + conf &= ~(1 << 9); + + writew(conf, MEMIF_REG(EXTRA_CONF)); +} + +void calypso_debugunit(int enable) +{ + uint16_t conf = readw(MEMIF_REG(EXTRA_CONF)); + + if (enable) + conf &= ~(1 << 11); + else + conf |= (1 << 11); + + writew(conf, MEMIF_REG(EXTRA_CONF)); +} + +#define REG_RHEA_CNTL 0xfffff900 +#define REG_API_CNTL 0xfffff902 +#define REG_ARM_RHEA 0xfffff904 + +void calypso_rhea_cfg(uint8_t fac0, uint8_t fac1, uint8_t timeout, + uint8_t ws_h, uint8_t ws_l, uint8_t w_en0, uint8_t w_en1) +{ + writew(fac0 | (fac1 << 4) | (timeout << 8), REG_RHEA_CNTL); + writew(ws_h | (ws_l << 5), REG_API_CNTL); + writew(w_en0 | (w_en1 << 1), REG_ARM_RHEA); +} -- 1.7.1

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[PATCH 1/4] Initial support for Nuttx on TI Calypso platform: Add calypso chip and compal E99 board to Nuttx targets linker script no-brainer / dummy files Osmocom's debug.h, defines.h, memory.h for compatibility

by Stefan Richter

--- nuttx/arch/arm/include/calypso/debug.h | 31 ++ nuttx/arch/arm/include/calypso/defines.h | 18 ++ nuttx/arch/arm/include/calypso/memory.h | 28 ++ nuttx/arch/arm/src/Makefile | 2 +- nuttx/arch/arm/src/calypso/Make.defs | 53 ++++ nuttx/arch/arm/src/calypso/calypso_head.S | 23 ++ nuttx/arch/arm/src/calypso/calypso_lowputc.S | 136 +++++++++ nuttx/arch/arm/src/calypso/chip.h | 204 +++++++++++++ nuttx/configs/compal_e99/include/board.h | 6 + nuttx/configs/compal_e99/ld.script | 126 ++++++++ nuttx/configs/compal_e99/ostest/Make.defs | 123 ++++++++ nuttx/configs/compal_e99/ostest/appconfig | 39 +++ nuttx/configs/compal_e99/ostest/defconfig | 414 ++++++++++++++++++++++++++ nuttx/configs/compal_e99/ostest/setenv.sh | 46 +++ nuttx/configs/compal_e99/src/Makefile | 80 +++++ nuttx/configs/compal_e99/src/dummy.c | 1 + 16 files changed, 1329 insertions(+), 1 deletions(-) create mode 100644 nuttx/arch/arm/include/calypso/debug.h create mode 100644 nuttx/arch/arm/include/calypso/defines.h create mode 100644 nuttx/arch/arm/include/calypso/memory.h create mode 100644 nuttx/arch/arm/src/calypso/Make.defs create mode 100644 nuttx/arch/arm/src/calypso/calypso_head.S create mode 100644 nuttx/arch/arm/src/calypso/calypso_lowputc.S create mode 100644 nuttx/arch/arm/src/calypso/chip.h create mode 100644 nuttx/configs/compal_e99/include/board.h create mode 100644 nuttx/configs/compal_e99/ld.script create mode 100644 nuttx/configs/compal_e99/ostest/Make.defs create mode 100644 nuttx/configs/compal_e99/ostest/appconfig create mode 100644 nuttx/configs/compal_e99/ostest/defconfig create mode 100755 nuttx/configs/compal_e99/ostest/setenv.sh create mode 100644 nuttx/configs/compal_e99/src/Makefile create mode 100644 nuttx/configs/compal_e99/src/dummy.c diff --git a/nuttx/arch/arm/include/calypso/debug.h b/nuttx/arch/arm/include/calypso/debug.h new file mode 100644 index 0000000..27c4185 --- /dev/null +++ b/nuttx/arch/arm/include/calypso/debug.h @@ -0,0 +1,31 @@ +#ifndef _DEBUG_H +#define _DEBUG_H + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#endif + +/* + * Check at compile time that something is of a particular type. + * Always evaluates to 1 so you may use it easily in comparisons. + */ +#define typecheck(type,x) \ +({ type __dummy; \ + typeof(x) __dummy2; \ + (void)(&__dummy == &__dummy2); \ + 1; \ +}) + +#ifdef DEBUG +#define dputchar(x) putchar(x) +#define dputs(x) puts(x) +#define dphex(x,y) phex(x,y) +#define printd(x, args ...) printf(x, ## args) +#else +#define dputchar(x) +#define dputs(x) +#define dphex(x,y) +#define printd(x, args ...) +#endif + +#endif /* _DEBUG_H */ diff --git a/nuttx/arch/arm/include/calypso/defines.h b/nuttx/arch/arm/include/calypso/defines.h new file mode 100644 index 0000000..3c8732f --- /dev/null +++ b/nuttx/arch/arm/include/calypso/defines.h @@ -0,0 +1,18 @@ + +#ifndef _DEFINES_H +#define _DEFINES_H + +#define __attribute_const__ __attribute__((__const__)) + +/* type properties */ +#define __packed __attribute__((packed)) +#define __aligned(alignment) __attribute__((aligned(alignment))) +#define __unused __attribute__((unused)) + +/* linkage */ +#define __section(name) __attribute__((section(name))) + +/* force placement in zero-waitstate memory */ +#define __ramtext __section(".ramtext") + +#endif /* !_DEFINES_H */ diff --git a/nuttx/arch/arm/include/calypso/memory.h b/nuttx/arch/arm/include/calypso/memory.h new file mode 100644 index 0000000..b0a0490 --- /dev/null +++ b/nuttx/arch/arm/include/calypso/memory.h @@ -0,0 +1,28 @@ +#ifndef _MEMORY_H +#define _MEMORY_H + +#define __arch_getb(a) (*(volatile unsigned char *)(a)) +#define __arch_getw(a) (*(volatile unsigned short *)(a)) +#define __arch_getl(a) (*(volatile unsigned int *)(a)) + +#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v)) +#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v)) +#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v)) + +#define __raw_writeb(v,a) __arch_putb(v,a) +#define __raw_writew(v,a) __arch_putw(v,a) +#define __raw_writel(v,a) __arch_putl(v,a) + +#define __raw_readb(a) __arch_getb(a) +#define __raw_readw(a) __arch_getw(a) +#define __raw_readl(a) __arch_getl(a) + +#define writeb(v,a) __arch_putb(v,a) +#define writew(v,a) __arch_putw(v,a) +#define writel(v,a) __arch_putl(v,a) + +#define readb(a) __arch_getb(a) +#define readw(a) __arch_getw(a) +#define readl(a) __arch_getl(a) + +#endif /* _MEMORY_H */ diff --git a/nuttx/arch/arm/src/Makefile b/nuttx/arch/arm/src/Makefile index 22327af..2530c05 100644 --- a/nuttx/arch/arm/src/Makefile +++ b/nuttx/arch/arm/src/Makefile @@ -67,7 +67,7 @@ SRCS = $(ASRCS) $(CSRCS) OBJS = $(AOBJS) $(COBJS) LDFLAGS = $(ARCHSCRIPT) -EXTRA_LIBS = +#EXTRA_LIBS = LINKLIBS = ifeq ($(WINTOOL),y) diff --git a/nuttx/arch/arm/src/calypso/Make.defs b/nuttx/arch/arm/src/calypso/Make.defs new file mode 100644 index 0000000..d1c14d4 --- /dev/null +++ b/nuttx/arch/arm/src/calypso/Make.defs @@ -0,0 +1,53 @@ +############################################################################ +# calypso/Make.defs +# +# Copyright (C) 2007 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <spudmonkey(a)racsa.co.cr> +# +# Copyright (C) 2011 Stefan Richter. All rights reserved. +# Author: Stefan Richter <ichgeh(a)l--putt.de> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name Gregory Nutt nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +HEAD_ASRC = calypso_head.S + +CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_vectors.S \ + up_nommuhead.S +CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ + up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c up_doirq.c \ + up_exit.c up_idle.c up_initialstate.c up_initialize.c \ + up_interruptcontext.c up_prefetchabort.c up_releasepending.c \ + up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \ + up_sigdeliver.c up_syscall.c up_unblocktask.c \ + up_undefinedinsn.c up_usestack.c + +CHIP_ASRCS = calypso_lowputc.S +CHIP_CSRCS = calypso_irq.c calypso_timer.c calypso_heap.c \ + clock.c diff --git a/nuttx/arch/arm/src/calypso/calypso_head.S b/nuttx/arch/arm/src/calypso/calypso_head.S new file mode 100644 index 0000000..eb83b68 --- /dev/null +++ b/nuttx/arch/arm/src/calypso/calypso_head.S @@ -0,0 +1,23 @@ +/* Place a branch to the real head at the entry point */ +.section .text.start + b __start + + +/* Exception Vectors like they are needed for the exception vector + indirection of the internal boot ROM. The following section must + be liked to appear at 0x80001c */ +.section .text.exceptions +_undef_instr: + b up_vectorundefinsn +_sw_interr: + b up_vectorswi +_prefetch_abort: + b up_vectorprefetch +_data_abort: + b up_vectordata +_reserved: + b _reserved +_irq: + b up_vectorirq +_fiq: + b up_vectorfiq diff --git a/nuttx/arch/arm/src/calypso/calypso_lowputc.S b/nuttx/arch/arm/src/calypso/calypso_lowputc.S new file mode 100644 index 0000000..bf30fe0 --- /dev/null +++ b/nuttx/arch/arm/src/calypso/calypso_lowputc.S @@ -0,0 +1,136 @@ +/************************************************************************** + * calypso/calypso_lowputc.S + * + * Copyright (C) 2011 Stefan Richter. All rights reserved. + * Author: Stefan Richter <ichgeh(a)l--putt.de> + * + * based on: c5471/c5471_lowputc.S + * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey(a)racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + **************************************************************************/ + +/************************************************************************** + * Included Files + **************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" + +/************************************************************************** + * Private Definitions + **************************************************************************/ + +/************************************************************************** + * Private Types + **************************************************************************/ + +/************************************************************************** + * Private Function Prototypes + **************************************************************************/ + +/************************************************************************** + * Global Variables + **************************************************************************/ + +/************************************************************************** + * Private Variables + **************************************************************************/ + +/************************************************************************** + * Private Functions + **************************************************************************/ + +/************************************************************************** + * Public Functions + **************************************************************************/ + +/************************************************************************** + * Name: up_lowputc + **************************************************************************/ + +/* This assembly language version has the advantage that it can does not + * require a C stack and uses only r0-r1. Hence it can be used during + * early boot phases. + */ + + .text + .global up_putc + .type up_putc, function +up_putc: + .global up_lowputc + .type up_lowputc, function +up_lowputc: + /* On entry, r0 holds the character to be printed */ + +#ifdef CONFIG_SERIAL_IRDA_CONSOLE + ldr r2, =UART_IRDA_BASE /* r2=IRDA UART base */ +#else + ldr r2, =UART_MODEM_BASE /* r2=Modem UART base */ +#endif + + /* Poll bit 0 of the UART_SSR register. When the bit + * is clear, the TX FIFO is no longer full + */ + +1: ldrb r1, [r2, #UART_SSR_OFFS] + tst r1, #UART_SSR_TXFULL + bne 1b + + /* Send the character by writing it into the UART_THR + * register. + */ + + strb r0, [r2, #UART_THR_OFFS] + + /* Wait for the tranmsit holding regiser (THR) to be + * emptied. This is detemined when bit 6 of the LSR + * is set. + */ + +2: ldrb r1, [r2, #UART_LSR_OFFS] + tst r1, #0x00000020 + beq 2b + + /* If the character that we just sent was a linefeed, + * then send a carriage return as well. + */ + + teq r0, #'\n' + moveq r0, #'\r' + beq 1b + + /* And return */ + + mov pc, lr + diff --git a/nuttx/arch/arm/src/calypso/chip.h b/nuttx/arch/arm/src/calypso/chip.h new file mode 100644 index 0000000..b837871 --- /dev/null +++ b/nuttx/arch/arm/src/calypso/chip.h @@ -0,0 +1,204 @@ +/**************************************************************************** + * calypso/chip.h + * + * Copyright (C) 2011 Stefan Richter. All rights reserved. + * Author: Stefan Richter <ichgeh(a)l--putt.de> + * + * based on: c5471/chip.h + * Copyright (C) 2007 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey(a)racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name Gregory Nutt nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CALYPSO_CHIP_H +#define __CALYPSO_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/* UARTs ********************************************************************/ + +#define UART_IRDA_BASE 0xffff5000 +#define UART_MODEM_BASE 0xffff5800 +#define UARTn_IO_RANGE 0x00000800 + +/* Common UART Registers. Expressed as offsets from the BASE address */ + +#define UART_RHR_OFFS 0x00000000 /* Rcv Holding Register */ +#define UART_THR_OFFS 0x00000000 /* Xmit Holding Register */ +#define UART_FCR_OFFS 0x00000008 /* FIFO Control Register */ +#define UART_RFCR_OFFS 0x00000008 /* Rcv FIFO Control Register */ +#define UART_TFCR_OFFS 0x00000008 /* Xmit FIFO Control Register */ +#define UART_SCR_OFFS 0x0000000c /* Status Control Register */ +#define UART_LCR_OFFS 0x00000010 /* Line Control Register */ +#define UART_LSR_OFFS 0x00000005 /* Line Status Register */ +#define UART_SSR_OFFS 0x00000011 /* Supplementary Status Register */ +#define UART_MCR_OFFS 0x0000001c /* Modem Control Register */ +#define UART_MSR_OFFS 0x00000020 /* Modem Status Register */ +#define UART_IER_OFFS 0x00000024 /* Interrupt Enable Register */ +#define UART_ISR_OFFS 0x00000028 /* Interrupt Status Register */ +#define UART_EFR_OFFS 0x0000002c /* Enhanced Feature Register */ +#define UART_XON1_OFFS 0x00000030 /* XON1 Character Register */ +#define UART_XON2_OFFS 0x00000034 /* XON2 Character Register */ +#define UART_XOFF1_OFFS 0x00000038 /* XOFF1 Character Register */ +#define UART_XOFF2_OFFS 0x0000003c /* XOFF2 Character Register */ +#define UART_SPR_OFFS 0x00000040 /* Scratch-pad Register */ +#define UART_DIV_115K_OFFS 0x00000044 /* Divisor for baud generation */ +#define UART_DIV_BIT_RATE_OFFS 0x00000048 /* For baud rate generation */ +#define UART_TCR_OFFS 0x0000004c /* Transmission Control Register */ +#define UART_TLR_OFFS 0x00000050 /* Trigger Level Register */ +#define UART_MDR_OFFS 0x00000054 /* Mode Definition Register */ + +/* UART Settings ************************************************************/ + +/* Miscellaneous UART settings. */ + +#define UART_RX_FIFO_NOEMPTY 0x00000001 +#define UART_SSR_TXFULL 0x00000001 +#define UART_LSR_TREF 0x00000020 + +#define UART_XMIT_FIFO_SIZE 64 +#define UART_IRDA_XMIT_FIFO_SIZE 64 + +/* UART_LCR Register */ + /* Bits 31-7: Reserved */ +#define UART_LCR_BOC 0x00000040 /* Bit 6: Break Control */ + /* Bit 5: Parity Type 2 */ +#define UART_LCR_PAREVEN 0x00000010 /* Bit 4: Parity Type 1 */ +#define UART_LCR_PARODD 0x00000000 +#define UART_LCR_PAREN 0x00000008 /* Bit 3: Paity Enable */ +#define UART_LCR_PARDIS 0x00000000 +#define UART_LCR_2STOP 0x00000004 /* Bit 2: Number of stop bits */ +#define UART_LCR_1STOP 0x00000000 +#define UART_LCR_5BITS 0x00000000 /* Bits 0-1: Word-length */ +#define UART_LCR_6BITS 0x00000001 +#define UART_LCR_7BITS 0x00000002 +#define UART_LCR_8BITS 0x00000003 + +#define UART_FCR_FTL 0x00000000 +#define UART_FCR_FIFO_EN 0x00000001 +#define UART_FCR_TX_CLR 0x00000002 +#define UART_FCR_RX_CLR 0x00000004 + +#define UART_IER_RECVINT 0x00000001 +#define UART_IER_XMITINT 0x00000002 +#define UART_IER_LINESTSINT 0x00000004 +#define UART_IER_MODEMSTSINT 0x00000008 /* IrDA UART only */ +#define UART_IER_XOFFINT 0x00000020 +#define UART_IER_RTSINT 0x00000040 /* IrDA UART only */ +#define UART_IER_CTSINT 0x00000080 /* IrDA UART only */ +#define UART_IER_INTMASK 0x000000ff + +#define BAUD_115200 0x00000001 +#define BAUD_57600 0x00000002 +#define BAUD_38400 0x00000003 +#define BAUD_19200 0x00000006 +#define BAUD_9600 0x0000000C +#define BAUD_4800 0x00000018 +#define BAUD_2400 0x00000030 +#define BAUD_1200 0x00000060 + +#define MDR_UART_MODE 0x00000000 /* Both IrDA and Modem UARTs */ +#define MDR_SIR_MODE 0x00000001 /* IrDA UART only */ +#define MDR_AUTOBAUDING_MODE 0x00000002 /* Modem UART only */ +#define MDR_RESET_MODE 0x00000007 /* Both IrDA and Modem UARTs */ + +/* SPI **********************************************************************/ + +#define MAX_SPI 3 + +#define SPI_REGISTER_BASE 0xffff2000 + +/* ARMIO ********************************************************************/ +/* Timers / Watchdog ********************************************************/ + +#define C5471_TIMER0_CTRL 0xffff2a00 +#define C5471_TIMER0_CNT 0xffff2a04 +#define C5471_TIMER1_CTRL 0xffff2b00 +#define C5471_TIMER1_CNT 0xffff2b04 +#define C5471_TIMER2_CTRL 0xffff2c00 +#define C5471_TIMER2_CNT 0xffff2c04 + +/* Interrupts ***************************************************************/ + +#define HAVE_SRC_IRQ_BIN_REG 0 + +#define INT_FIRST_IO 0xffff2d00 +#define INT_IO_RANGE 0x5C + +#define IT_REG 0xffff2d00 +#define MASK_IT_REG 0xffff2d04 +#define SRC_IRQ_REG 0xffff2d08 +#define SRC_FIQ_REG 0xffff2d0c +#define SRC_IRQ_BIN_REG 0xffff2d10 +#define INT_CTRL_REG 0xffff2d18 + +#define ILR_IRQ0_REG 0xffff2d1C /* 0-Timer 0 */ +#define ILR_IRQ1_REG 0xffff2d20 /* 1-Timer 1 */ +#define ILR_IRQ2_REG 0xffff2d24 /* 2-Timer 2 */ +#define ILR_IRQ3_REG 0xffff2d28 /* 3-GPIO0 */ +#define ILR_IRQ4_REG 0xffff2d2c /* 4-Ethernet */ +#define ILR_IRQ5_REG 0xffff2d30 /* 5-KBGPIO[7:0] */ +#define ILR_IRQ6_REG 0xffff2d34 /* 6-Uart serial */ +#define ILR_IRQ7_REG 0xffff2d38 /* 7-Uart IRDA */ +#define ILR_IRQ8_REG 0xffff2d3c /* 8-KBGPIO[15:8] */ +#define ILR_IRQ9_REG 0xffff2d40 /* 9-GPIO3 */ +#define ILR_IRQ10_REG 0xffff2d44 /* 10-GPIO2 */ +#define ILR_IRQ11_REG 0xffff2d48 /* 11-I2C */ +#define ILR_IRQ12_REG 0xffff2d4c /* 12-GPIO1 */ +#define ILR_IRQ13_REG 0xffff2d50 /* 13-SPI */ +#define ILR_IRQ14_REG 0xffff2d54 /* 14-GPIO[19:4] */ +#define ILR_IRQ15_REG 0xffff2d58 /* 15-API */ + +/* CLKM *********************************************************************/ + +#define CLKM 0xffff2f00 +#define CLKM_CTL_RST 0xffff2f10 +#define CLKM_RESET 0xffff2f18 + +#define CLKM_RESET_EIM 0x00000008 +#define CLKM_EIM_CLK_STOP 0x00000010 +#define CLKM_CTL_RST_LEAD_RESET 0x00000000 +#define CLKM_CTL_RST_EXT_RESET 0x00000002 + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __CALYPSO_CHIP_H */ diff --git a/nuttx/configs/compal_e99/include/board.h b/nuttx/configs/compal_e99/include/board.h new file mode 100644 index 0000000..1a1a743 --- /dev/null +++ b/nuttx/configs/compal_e99/include/board.h @@ -0,0 +1,6 @@ +/************************************************************************ + * arch/board.h + * + * Supposed to be empty + * + ************************************************************************/ diff --git a/nuttx/configs/compal_e99/ld.script b/nuttx/configs/compal_e99/ld.script new file mode 100644 index 0000000..07f1ab0 --- /dev/null +++ b/nuttx/configs/compal_e99/ld.script @@ -0,0 +1,126 @@ +/* + * Linker script for running from internal SRAM on Compal phones + * + * This script is tailored specifically to the requirements imposed + * on us by the Compal bootloader. + * + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(__start) +MEMORY +{ + /* compal-loaded binary: our text, initialized data */ + LRAM (rw) : ORIGIN = 0x00800000, LENGTH = 0x00010000 + /* compal-loaded binary: our unitialized data, stacks, heap */ + IRAM (rw) : ORIGIN = 0x00810000, LENGTH = 0x00010000 +} +SECTIONS +{ + . = 0x800000; + + /* romloader data section, contains passthru interrupt vectors */ + .compal.loader (NOLOAD) : { . = 0x100; } > LRAM + + /* image signature (prepended by osmocon according to phone type) */ + .compal.header (NOLOAD) : { . = 4; } > LRAM + + /* initialization code */ + . = ALIGN(4); + .text.start : { + PROVIDE(__start = .); + KEEP(*(.text.start)) + *(.text.start) + } > LRAM + + /* exception vectors from 0x80001c to 0x800034 */ + .text.exceptions 0x80001c : AT (LOADADDR(.text.start) + SIZEOF(.text.start)) { + KEEP(*(.text.exceptions)) + * (.text.exceptions) + . = ALIGN(4); + } > LRAM + PROVIDE(_exceptions = LOADADDR(.text.exceptions)); + + /* code */ + . = ALIGN(4); + .text (LOADADDR(.text.exceptions) + SIZEOF(.text.exceptions)) : + AT (LOADADDR(.text.exceptions) + SIZEOF(.text.exceptions)) { + /* regular code */ + *(.text*) + /* always-in-ram code */ + *(.ramtext*) + /* gcc voodoo */ + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) *(.v4_bx) + . = ALIGN(4); + } > LRAM + PROVIDE(_text_start = LOADADDR(.text)); + PROVIDE(_text_end = LOADADDR(.text) + SIZEOF(.text)); + + /* constructor pointers */ + .ctors : { + /* ctor count */ + LONG(SIZEOF(.ctors) / 4 - 2) + /* ctor pointers */ + KEEP(*(SORT(.ctors))) + /* end of list */ + LONG(0) + } > LRAM + PROVIDE(_ctor_start = LOADADDR(.ctors)); + PROVIDE(_ctor_end = LOADADDR(.ctors) + SIZEOF(.ctors)); + + /* destructor pointers */ + .dtors : { + /* dtor count */ + LONG(SIZEOF(.dtors) / 4 - 2) + /* dtor pointers */ + KEEP(*(SORT(.dtors))) + /* end of list */ + LONG(0) + } > LRAM + PROVIDE(_dtor_start = LOADADDR(.dtors)); + PROVIDE(_dtor_end = LOADADDR(.dtors) + SIZEOF(.dtors)); + + /* read-only data */ + . = ALIGN(4); + .rodata : { + *(.rodata*) + } > LRAM + PROVIDE(_rodata_start = LOADADDR(.rodata)); + PROVIDE(_rodata_end = LOADADDR(.rodata) + SIZEOF(.rodata)); + + /* initialized data */ + . = ALIGN(4); + .data : { + *(.data) + } > LRAM + PROVIDE(_data_start = LOADADDR(.data)); + PROVIDE(_data_end = LOADADDR(.data) + SIZEOF(.data)); + + /* pic offset tables */ + . = ALIGN(4); + .got : { + *(.got) + *(.got.plt) *(.igot.plt) *(.got) *(.igot) + } > LRAM + PROVIDE(_got_start = LOADADDR(.got)); + PROVIDE(_got_end = LOADADDR(.got) + SIZEOF(.got)); + + /* uninitialized data */ + .bss (NOLOAD) : { + . = ALIGN(4); + __bss_start = .; + _sbss = ABSOLUTE(.); + *(.bss) + _ebss = ABSOLUTE(.); + } > IRAM + . = ALIGN(4); + __bss_end = .; + PROVIDE(_bss_start = __bss_start); + PROVIDE(_bss_end = __bss_end); + + /* end of image */ + . = ALIGN(4); + _end = .; + PROVIDE(end = .); +} diff --git a/nuttx/configs/compal_e99/ostest/Make.defs b/nuttx/configs/compal_e99/ostest/Make.defs new file mode 100644 index 0000000..06ef3d4 --- /dev/null +++ b/nuttx/configs/compal_e99/ostest/Make.defs @@ -0,0 +1,123 @@ +############################################################################ +# configs/compal_e99/ostest/Make.defs +# +# Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <spudmonkey(a)racsa.co.cr> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config + +OSMODIR = $(TOPDIR)/../../osmocom-bb +EXTRA_LIBS = $(OSMODIR)/src/target/firmware/comm/libcomm.a $(OSMODIR)/src/shared/libosmocore/build-target/src/.libs/libosmocore.a $(OSMODIR)/src/target/firmware/comm/libcomm.a + # ^^^ Stupid hack! Why do I have to put it twice??? + +CROSSDEV = arm-elf- +CC = $(CROSSDEV)gcc +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version $[0-9\.]$/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ("${CONFIG_DEBUG_SYMBOLS}","y") + ARCHOPTIMIZATION = -g +else + ARCHOPTIMIZATION = -Os -fno-strict-aliasing -fno-strength-reduce \ + -fomit-frame-pointer +endif + +ifeq ($(ARCHCCMAJOR),4) + ARCHCPUFLAGS = -mcpu=arm7tdmi -mfloat-abi=soft -fno-builtin +else + ARCHCPUFLAGS = -mapcs-32 -mcpu=arm7tdmi -msoft-float -fno-builtin +endif +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow +ARCHDEFINES = +ARCHINCLUDES = -I. -I$(OSMODIR)/src/shared/libosmocore/include -isystem $(TOPDIR)/include +ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/ld.script + +CFLAGS = $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ + $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) \ + -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat.ld \ + -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifeq ("${CONFIG_DEBUG_SYMBOLS}","y") + LDFLAGS += -g +endif + +define PREPROCESS + @echo "CPP: $1->$2" + @$(CPP) $(CPPFLAGS) $1 -o $2 +endef + +define COMPILE + @echo "CC: $1" + @$(CC) -c $(CFLAGS) $1 -o $2 +endef + +define ASSEMBLE + @echo "AS: $1" + @$(CC) -c $(AFLAGS) $1 -o $2 +endef + +define ARCHIVE + echo "AR: $2"; \ + $(AR) $1 $2 || { echo "$(AR) $1 $2 FAILED!" ; exit 1 ; } +endef + +define CLEAN + @rm -f *.o *.a +endef + +MKDEP = $(TOPDIR)/tools/mkdeps.sh + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -wstrict-prototypes -Wshadow -g -pipe +HOSTLDFLAGS = + + diff --git a/nuttx/configs/compal_e99/ostest/appconfig b/nuttx/configs/compal_e99/ostest/appconfig new file mode 100644 index 0000000..97e30c0 --- /dev/null +++ b/nuttx/configs/compal_e99/ostest/appconfig @@ -0,0 +1,39 @@ +############################################################################ +# configs/c5471evm/ostest/appconfig +# +# Copyright (C) 2011 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <spudmonkey(a)racsa.co.cr> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +# Path to example in apps/examples containing the user_start entry point + +CONFIGURED_APPS += examples/ostest + diff --git a/nuttx/configs/compal_e99/ostest/defconfig b/nuttx/configs/compal_e99/ostest/defconfig new file mode 100644 index 0000000..7cb55e2 --- /dev/null +++ b/nuttx/configs/compal_e99/ostest/defconfig @@ -0,0 +1,414 @@ +############################################################################ +# configs/compal_e99/ostest/defconfig +# +# Copyright (C) 2007-2011 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <spudmonkey(a)racsa.co.cr> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ +# +# architecture selection +# +# CONFIG_ARCH - identifies the arch subdirectory and, hence, the +# processor architecture. +# CONFIG_ARCH_family - for use in C code. This identifies the +# particular chip family that the architecture is implemented +# in. +# CONFIG_ARCH_architecture - for use in C code. This identifies the +# specific architecture within the chip familyl. +# CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory +# CONFIG_ARCH_CHIP_name - For use in C code +# CONFIG_ARCH_BOARD - identifies the configs subdirectory and, hence, +# the board that supports the particular chip or SoC. +# CONFIG_ARCH_BOARD_name - for use in C code +# CONFIG_BOARD_LOOPSPERMSEC - for delay loops +# CONFIG_ENDIAN_BIG - define if big endian (default is little endian) +# CONFIG_ROM_VECTORS - unique to c5471 +# CONFIG_DRAM_END - the size of installed DRAM. +# Unique to c5471 +# CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to c5471. +# CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt +# stack. If defined, this symbol is the size of the interrupt +# stack in bytes. If not defined, the user task stacks will be +# used during interrupt handling. +# CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions +# +CONFIG_ARCH=arm +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM7TDMI=y +CONFIG_ARCH_CHIP=calypso +CONFIG_ARCH_CHIP_CALYPSO=y +CONFIG_ARCH_BOARD=compal_e99 +CONFIG_ARCH_BOARD_COMPALE99=y +CONFIG_BOARD_LOOPSPERMSEC=1250 +CONFIG_ROM_VECTORS=n +CONFIG_DRAM_END=0x00840000 +CONFIG_ARCH_LEDS=n +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_ARCH_STACKDUMP=y + +# +# General build options +# +# CONFIG_RRLOAD_BINARY - make the rrload binary format used with +# BSPs from www.ridgerun.com using the tools/mkimage.sh script +# CONFIG_INTELHEX_BINARY - make the Intel HEX binary format +# used with many different loaders using the GNU objcopy program +# Should not be selected if you are not using the GNU toolchain. +# CONFIG_RAW_BINARY - make a raw binary format file used with many +# different loaders using the GNU objcopy program. This option +# should not be selected if you are not using the GNU toolchain. +# CONFIG_HAVE_LIBM - toolchain supports libm.a +# +CONFIG_RRLOAD_BINARY=n +CONFIG_INTELHEX_BINARY=n +CONFIG_RAW_BINARY=y +CONFIG_HAVE_LIBM=n + +# +# General OS setup +# +# CONFIG_APPS_DIR - Identifies the relative path to the directory +# that builds the application to link with NuttX. Default: ../apps +# CONFIG_DEBUG - enables built-in debug options +# CONFIG_DEBUG_VERBOSE - enables verbose debug output +# CONFIG_DEBUG_SYMBOLS - build without optimization and with +# debug symbols (needed for use with a debugger). +# CONFIG_MM_REGIONS - If the architecture includes multiple +# regions of memory to allocate from, this specifies the +# number of memory regions that the memory manager must +# handle and enables the API mm_addregion(start, end); +# CONFIG_ARCH_LOWPUTC - architecture supports low-level, boot +# time console output +# CONFIG_TICKS_PER_MSEC - The default system timer is 100Hz +# or TICKS_PER_MSEC=10. This setting may be defined to +# inform NuttX that the processor hardware is providing +# system timer interrupts at some interrupt interval other +# than 10 msec. +# CONFIG_RR_INTERVAL - The round robin timeslice will be set +# this number of milliseconds; Round robin scheduling can +# be disabled by setting this value to zero. +# CONFIG_SCHED_INSTRUMENTATION - enables instrumentation in +# scheduler to monitor system performance +# CONFIG_TASK_NAME_SIZE - Spcifies that maximum size of a +# task name to save in the TCB. Useful if scheduler +# instrumentation is selected. Set to zero to disable. +# CONFIG_START_YEAR, CONFIG_START_MONTH, CONFIG_START_DAY - +# Used to initialize the internal time logic. +# CONFIG_JULIAN_TIME - Enables Julian time conversions +# CONFIG_DEV_CONSOLE - Set if architecture-specific logic +# provides /dev/console. Enables stdout, stderr, stdin. +# CONFIG_DEV_LOWCONSOLE - Use the simple, low-level serial console +# driver (minimul support) +# CONFIG_MUTEX_TYPES: Set to enable support for recursive and +# errorcheck mutexes. Enables pthread_mutexattr_settype(). +# CONFIG_PRIORITY_INHERITANCE : Set to enable support for priority +# inheritance on mutexes and semaphores. +# CONFIG_SEM_PREALLOCHOLDERS: This setting is only used if priority +# inheritance is enabled. It defines the maximum number of +# different threads (minus one) that can take counts on a +# semaphore with priority inheritance support. This may be +# set to zero if priority inheritance is disabled OR if you +# are only using semaphores as mutexes (only one holder) OR +# if no more than two threads participate using a counting +# semaphore. +# CONFIG_SEM_NNESTPRIO. If priority inheritance is enabled, +# then this setting is the maximum number of higher priority +# threads (minus 1) than can be waiting for another thread +# to release a count on a semaphore. This value may be set +# to zero if no more than one thread is expected to wait for +# a semaphore. +# CONFIG_FDCLONE_DISABLE. Disable cloning of all file descriptors +# by task_create() when a new task is started. If set, all +# files/drivers will appear to be closed in the new task. +# CONFIG_FDCLONE_STDIO. Disable cloning of all but the first +# three file descriptors (stdin, stdout, stderr) by task_create() +# when a new task is started. If set, all files/drivers will +# appear to be closed in the new task except for stdin, stdout, +# and stderr. +# CONFIG_SDCLONE_DISABLE. Disable cloning of all socket +# desciptors by task_create() when a new task is started. If +# set, all sockets will appear to be closed in the new task. +# CONFIG_NXFLAT. Enable support for the NXFLAT binary format. +# This format will support execution of NuttX binaries located +# in a ROMFS filesystem (see examples/nxflat). +# +#CONFIG_APPS_DIR= +CONFIG_DEBUG=n +CONFIG_DEBUG_VERBOSE=n +CONFIG_DEBUG_SYMBOLS=n +CONFIG_MM_REGIONS=2 +CONFIG_ARCH_LOWPUTC=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_INSTRUMENTATION=n +CONFIG_TASK_NAME_SIZE=0 +CONFIG_START_YEAR=2007 +CONFIG_START_MONTH=2 +CONFIG_START_DAY=13 +CONFIG_JULIAN_TIME=n +CONFIG_DEV_CONSOLE=n +CONFIG_DEV_LOWCONSOLE=n +CONFIG_MUTEX_TYPES=n +CONFIG_PRIORITY_INHERITANCE=n +CONFIG_SEM_PREALLOCHOLDERS=0 +CONFIG_SEM_NNESTPRIO=0 +CONFIG_FDCLONE_DISABLE=n +CONFIG_FDCLONE_STDIO=n +CONFIG_SDCLONE_DISABLE=y +CONFIG_NXFLAT=n + +# +# The following can be used to disable categories of +# APIs supported by the OS. If the compiler supports +# weak functions, then it should not be necessary to +# disable functions unless you want to restrict usage +# of those APIs. +# +# There are certain dependency relationships in these +# features. +# +# o mq_notify logic depends on signals to awaken tasks +# waiting for queues to become full or empty. +# o pthread_condtimedwait() depends on signals to wake +# up waiting tasks. +# +CONFIG_DISABLE_CLOCK=n +CONFIG_DISABLE_POSIX_TIMERS=n +CONFIG_DISABLE_PTHREAD=n +CONFIG_DISABLE_SIGNALS=n +CONFIG_DISABLE_MQUEUE=y +CONFIG_DISABLE_MOUNTPOINT=y +CONFIG_DISABLE_ENVIRON=n +CONFIG_DISABLE_POLL=y + +# +# Misc libc settings +# +# CONFIG_NOPRINTF_FIELDWIDTH - sprintf-related logic is a +# little smaller if we do not support fieldwidthes +# +CONFIG_NOPRINTF_FIELDWIDTH=n + +# +# Allow for architecture optimized implementations +# +# The architecture can provide optimized versions of the +# following to improve sysem performance +# +CONFIG_ARCH_MEMCPY=n +CONFIG_ARCH_MEMCMP=n +CONFIG_ARCH_MEMMOVE=n +CONFIG_ARCH_MEMSET=n +CONFIG_ARCH_STRCMP=n +CONFIG_ARCH_STRCPY=n +CONFIG_ARCH_STRNCPY=n +CONFIG_ARCH_STRLEN=n +CONFIG_ARCH_STRNLEN=n +CONFIG_ARCH_BZERO=n + +# +# Sizes of configurable things (0 disables) +# +# CONFIG_MAX_TASKS - The maximum number of simultaneously +# active tasks. This value must be a power of two. +# CONFIG_MAX_TASK_ARGS - This controls the maximum number of +# of parameters that a task may receive (i.e., maxmum value +# of 'argc') +# CONFIG_NPTHREAD_KEYS - The number of items of thread- +# specific data that can be retained +# CONFIG_NFILE_DESCRIPTORS - The maximum number of file +# descriptors (one for each open) +# CONFIG_NFILE_STREAMS - The maximum number of streams that +# can be fopen'ed +# CONFIG_NAME_MAX - The maximum size of a file name. +# CONFIG_STDIO_BUFFER_SIZE - Size of the buffer to allocate +# on fopen. (Only if CONFIG_NFILE_STREAMS > 0) +# CONFIG_NUNGET_CHARS - Number of characters that can be +# buffered by ungetc() (Only if CONFIG_NFILE_STREAMS > 0) +# CONFIG_PREALLOC_MQ_MSGS - The number of pre-allocated message +# structures. The system manages a pool of preallocated +# message structures to minimize dynamic allocations +# CONFIG_MQ_MAXMSGSIZE - Message structures are allocated with +# a fixed payload size given by this settin (does not include +# other message structure overhead. +# CONFIG_MAX_WDOGPARMS - Maximum number of parameters that +# can be passed to a watchdog handler +# CONFIG_PREALLOC_WDOGS - The number of pre-allocated watchdog +# structures. The system manages a pool of preallocated +# watchdog structures to minimize dynamic allocations +# CONFIG_PREALLOC_TIMERS - The number of pre-allocated POSIX +# timer structures. The system manages a pool of preallocated +# timer structures to minimize dynamic allocations. Set to +# zero for all dynamic allocations. +# +CONFIG_MAX_TASKS=64 +CONFIG_MAX_TASK_ARGS=4 +CONFIG_NPTHREAD_KEYS=4 +CONFIG_NFILE_DESCRIPTORS=32 +CONFIG_NFILE_STREAMS=16 +CONFIG_NAME_MAX=32 +CONFIG_STDIO_BUFFER_SIZE=256 +CONFIG_NUNGET_CHARS=2 +CONFIG_PREALLOC_MQ_MSGS=32 +CONFIG_MQ_MAXMSGSIZE=32 +CONFIG_MAX_WDOGPARMS=4 +CONFIG_PREALLOC_WDOGS=32 +CONFIG_PREALLOC_TIMERS=8 + +# +# TCP/IP and UDP support via uIP +# CONFIG_NET - Enable or disable all network features +# CONFIG_NET_IPv6 - Build in support for IPv6 +# CONFIG_NSOCKET_DESCRIPTORS - Maximum number of socket descriptors per task/thread. +# CONFIG_NET_SOCKOPTS - Enable or disable support for socket options +# CONFIG_NET_BUFSIZE - uIP buffer size +# CONFIG_NET_TCP - TCP support on or off +# CONFIG_NET_TCP_CONNS - Maximum number of TCP connections (all tasks) +# CONFIG_NET_TCP_READAHEAD_BUFSIZE - Size of TCP read-ahead buffers +# CONFIG_NET_NTCP_READAHEAD_BUFFERS - Number of TCP read-ahead buffers (may be zero) +# CONFIG_NET_TCPBACKLOG - Incoming connections pend in a backlog until +# accept() is called. The size of the backlog is selected when listen() is called. +# CONFIG_NET_MAX_LISTENPORTS - Maximum number of listening TCP ports (all tasks) +# CONFIG_NET_UDP - UDP support on or off +# CONFIG_NET_UDP_CHECKSUMS - UDP checksums on or off +# CONFIG_NET_UDP_CONNS - The maximum amount of concurrent UDP connections +# CONFIG_NET_ICMP - ICMP ping response support on or off +# CONFIG_NET_ICMP_PING - ICMP ping request support on or off +# CONFIG_NET_PINGADDRCONF - Use "ping" packet for setting IP address +# CONFIG_NET_STATISTICS - uIP statistics on or off +# CONFIG_NET_RECEIVE_WINDOW - The size of the advertised receiver's window +# CONFIG_NET_ARPTAB_SIZE - The size of the ARP table +# CONFIG_NET_BROADCAST - Broadcast support +# CONFIG_NET_FWCACHE_SIZE - number of packets to remember when looking for duplicates +# +CONFIG_NET=n +CONFIG_NET_IPv6=n +CONFIG_NSOCKET_DESCRIPTORS=0 +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_BUFSIZE=420 +CONFIG_NET_TCP=n +CONFIG_NET_TCP_CONNS=40 +CONFIG_NET_NTCP_READAHEAD_BUFFERS=8 +CONFIG_NET_TCPBACKLOG=n +CONFIG_NET_MAX_LISTENPORTS=40 +CONFIG_NET_UDP=n +CONFIG_NET_UDP_CHECKSUMS=y +#CONFIG_NET_UDP_CONNS=10 +CONFIG_NET_ICMP=n +CONFIG_NET_ICMP_PING=n +#CONFIG_NET_PINGADDRCONF=0 +CONFIG_NET_STATISTICS=y +#CONFIG_NET_RECEIVE_WINDOW= +#CONFIG_NET_ARPTAB_SIZE=8 +CONFIG_NET_BROADCAST=n +#CONFIG_NET_FWCACHE_SIZE=2 + +# +# UIP Network Utilities +# CONFIG_NET_DHCP_LIGHT - Reduces size of DHCP +# CONFIG_NET_RESOLV_ENTRIES - Number of resolver entries +CONFIG_NET_DHCP_LIGHT=n +CONFIG_NET_RESOLV_ENTRIES=4 + +# +# Settings for examples/uip +CONFIG_EXAMPLE_UIP_NOMAC=y +CONFIG_EXAMPLE_UIP_IPADDR=(10<<24|0<<16|0<<8|2) +CONFIG_EXAMPLE_UIP_DRIPADDR=(10<<24|0<<16|0<<8|1) +CONFIG_EXAMPLE_UIP_NETMASK=(255<<24|255<<16|255<<8|0) +CONFIG_EXAMPLE_UIP_DHCPC=n + +# +# Settings for examples/nettest +CONFIG_EXAMPLE_NETTEST_SERVER=n +CONFIG_EXAMPLE_NETTEST_PERFORMANCE=n +CONFIG_EXAMPLE_NETTEST_NOMAC=y +CONFIG_EXAMPLE_NETTEST_IPADDR=(10<<24|0<<16|0<<8|2) +CONFIG_EXAMPLE_NETTEST_DRIPADDR=(10<<24|0<<16|0<<8|1) +CONFIG_EXAMPLE_NETTEST_NETMASK=(255<<24|255<<16|255<<8|0) +CONFIG_EXAMPLE_NETTEST_CLIENTIP=(10<<24|0<<16|0<<8|1) + +# +# Settings for examples/nsh +CONFIG_NSH_CONSOLE=y +CONFIG_NSH_TELNET=n +CONFIG_NSH_IOBUFFER_SIZE=512 +CONFIG_NSH_CMD_SIZE=40 +CONFIG_NSH_STACKSIZE=4096 +CONFIG_NSH_DHCPC=n +CONFIG_NSH_NOMAC=y +CONFIG_NSH_IPADDR=(10<<24|0<<16|0<<8|2) +CONFIG_NSH_DRIPADDR=(10<<24|0<<16|0<<8|1) +CONFIG_NSH_NETMASK=(255<<24|255<<16|255<<8|0) + +# +# Settings for examples/wget +# CONFIG_EXAMPLE_WGET_URL - The URL of the file to get +# CONFIG_EXAMPLE_WGET_NOMAC - (May be defined to use software assigned MAC) +# CONFIG_EXAMPLE_WGET_IPADDR - Target IP address +# CONFIG_EXAMPLE_WGET_DRIPADDR - Default router IP addess +# CONFIG_EXAMPLE_WGET_NETMASK - Network mask +CONFIG_EXAMPLE_WGET_URL="http://www.nuttx.org/index.html" +CONFIG_EXAMPLE_WGET_NOMAC=y +CONFIG_EXAMPLE_WGET_IPADDR=(10L<<24|0L<<16|0L<<8|2L) +CONFIG_EXAMPLE_WGET_DRIPADDR=(10L<<24|0L<<16|0L<<8|1L) +CONFIG_EXAMPLE_WGET_NETMASK=(255L<<24|255L<<16|255L<<8|0L) + +# +# Stack and heap information +# +# CONFIG_BOOT_RUNFROMFLASH - Some configurations support XIP +# operation from FLASH but must copy initialized .data sections to RAM. +# CONFIG_BOOT_COPYTORAM - Some configurations boot in FLASH +# but copy themselves entirely into RAM for better performance. +# CONFIG_CUSTOM_STACK - The up_ implementation will handle +# all stack operations outside of the nuttx model. +# CONFIG_STACK_POINTER - The initial stack pointer (arm7tdmi only) +# CONFIG_IDLETHREAD_STACKSIZE - The size of the initial stack. +# This is the thread that (1) performs the inital boot of the system up +# to the point where user_start() is spawned, and (2) there after is the +# IDLE thread that executes only when there is no other thread ready to +# run. +# CONFIG_USERMAIN_STACKSIZE - The size of the stack to allocate +# for the main user thread that begins at the user_start() entry point. +# CONFIG_PTHREAD_STACK_MIN - Minimum pthread stack size +# CONFIG_PTHREAD_STACK_DEFAULT - Default pthread stack size +# CONFIG_HEAP_BASE - The beginning of the heap +# CONFIG_HEAP_SIZE - The size of the heap +# +CONFIG_BOOT_RUNFROMFLASH=n +CONFIG_BOOT_COPYTORAM=n +CONFIG_CUSTOM_STACK=n +CONFIG_STACK_POINTER= +CONFIG_IDLETHREAD_STACKSIZE=4096 +CONFIG_USERMAIN_STACKSIZE=4096 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=4096 +CONFIG_HEAP_BASE= +CONFIG_HEAP_SIZE= diff --git a/nuttx/configs/compal_e99/ostest/setenv.sh b/nuttx/configs/compal_e99/ostest/setenv.sh new file mode 100755 index 0000000..dc2c643 --- /dev/null +++ b/nuttx/configs/compal_e99/ostest/setenv.sh @@ -0,0 +1,46 @@ +#!/bin/bash +# c5471evm/ostest/setenv.sh +# +# Copyright (C) 2007, 2008, 2011 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <spudmonkey(a)racsa.co.cr> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$(basename $0)" = "setenv.sh" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +if [ -z ${PATH_ORIG} ]; then export PATH_ORIG=${PATH}; fi + +WD=`pwd` +export BUILDROOT_BIN=${WD}/../buildroot/build_arm_nofpu/staging_dir/bin +export PATH=${BUILDROOT_BIN}:/sbin:/usr/sbin:${PATH_ORIG} + +echo "PATH : ${PATH}" diff --git a/nuttx/configs/compal_e99/src/Makefile b/nuttx/configs/compal_e99/src/Makefile new file mode 100644 index 0000000..2160ea3 --- /dev/null +++ b/nuttx/configs/compal_e99/src/Makefile @@ -0,0 +1,80 @@ +############################################################################ +# configs/compal_e99/src/Makefile +# +# Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt <spudmonkey(a)racsa.co.cr> +# +# Copyright (C) 2011 Stefan Richter. All rights reserved. +# Author: Stefan Richter <ichgeh(a)l--putt.de> +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +CFLAGS += -I$(TOPDIR)/sched + +ASRCS = +AOBJS = $(ASRCS:.S=$(OBJEXT)) +CSRCS = dummy.c +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src +CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/arm + +all: libboard$(LIBEXT) + +$(AOBJS): %$(OBJEXT): %.S + $(call ASSEMBLE, $<, $@) + +$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +libboard$(LIBEXT): $(OBJS) + @( for obj in $(OBJS) ; do \ + $(call ARCHIVE, $@, $${obj}); \ + done ; ) + +.depend: Makefile $(SRCS) + @$(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep + @touch $@ + +depend: .depend + +clean: + @rm -f libboard$(LIBEXT) *~ .*.swp + $(call CLEAN) + +distclean: clean + @rm -f Make.dep .depend + +-include Make.dep diff --git a/nuttx/configs/compal_e99/src/dummy.c b/nuttx/configs/compal_e99/src/dummy.c new file mode 100644 index 0000000..69853a1 --- /dev/null +++ b/nuttx/configs/compal_e99/src/dummy.c @@ -0,0 +1 @@ +/* no libboard.a otherwise */ -- 1.7.1

12 years, 11 months

1
0
0 0

T191 unlock cable

by R M

Hi This is my first mail to this list. I have downloaded the code and compiled it. My development environment is Eclipse using cygwin as I am a Windows user. I have succeeded in procuring Motorola C115 phone and also T191 unlock cable but the cable has a serial port on one end and 2.5 mm audio jack at the other. My laptop doesn't have a serial port. It only has USB ports. What sort of USB to serial converter should I use? I have not enquired the cost of FDTI cables in India. But they seem to cost a fortune online. Please do suggest one that is cheap say within 200 rupees. I am also having difficulty downloading Iota and Rita data sheets as the links provided in the wiki lead to chinese sites and I don't understand chinese. Can some one who has already downloaded them please tell me the process like which buttons I need to click etc. Regards, RM

12 years, 11 months

2
3
0 0

GSMTAP now creates a locally bound receive socket

by Harald Welte

Hi! libosmocore >= 0.3.1 and the current osmocom-bb code will now generate not only the sending GSMTAP UDP socket, but also a locally-bound receive socket. This avoids the manual start of "nc -l -u -p 4729 >/dev/null" or iptables rules to drop the UDP packets. The local receive socket is only created if the GSMTAP IP address is a locally configured address on any of your network interfaces. So sending it to 127.0.0.1 should work well. Don't be surprised if you happen to see GSMTAP over IPv6, I'm now using getaddrinfo() and related functions, i.e. "loopback" may now resolve to ::1 instead of 127.0.0.1 Regards, Harald -- - Harald Welte <laforge(a)gnumonks.org> http://laforge.gnumonks.org/ ============================================================================ "Privacy in residential applications is a desirable marketing option." (ETSI EN 300 175-7 Ch. A6)

12 years, 11 months

2
2
0 0

Re: Anybody using a BTS for debugging?

by Mohammad Hosein

most of the test systems are not built to be used for on-air operations . the ones that offer such features must be used in Shield rooms where no signal gets in or out . these rooms are expensive but usually tech universities have some rental hours for their shield and antenna rooms . its expensive as well , otherwise you are probably going to have some conflict with local regulatory sooner or later regards On Thu, May 19, 2011 at 9:04 PM, Gianni Tedesco <gianni(a)scaramanga.co.uk>wrote: > On Fri, 2011-05-13 at 15:00 +0430, Mohammad Hosein wrote: > > you could use most GSM test systems for such purpose . on ebay you > > might find very cheap ones > > regards > > I managed to track down a Racal 6103. It should arrive in next couple of > days. > > As a followup question then, I guess that these are intended for wired > rf connection or at least they transmit at very low power, and tell the > phone to do the same. > > However, one would feel a lot better using a channel unused by other > cells in my location. I've been using cell_log to put together a list of > active ARFCN's that my handset receives broadcasts from. Script for > parsing cell_log logs is attached. > > Am I to conclude that if cell_log hasn't dumped: > > [sysinfo] > arfcn 99 > > for example, after running for a reasonably long period of time (say > 24hrs) that operating test equipment on channel 99 should be safe? > > Gianni > > -- > > #!/usr/bin/python > > def getline(f): > while True: > l = f.readline() > if not l: > raise StopIteration > l = l.rstrip('\r\n') > if not l: > continue > yield l > def bsic(v): > (a,b) = v.split(',') > return (int(a),int(b)) > > def hexdump(v): > ret = bytearray() > for x in v.split(): > ret.append(int(x, 16)) > return ret > > class Parser: > pass > > class Power(Parser): > def line(self, s): > return > > class mcc: > tbl = {0x234: 'UK and Northern Ireland'} > def __init__(self, num): > x = ((num & 0xf00) >> 8, > (num & 0xf000) >> 12, > (num & 0xf)) > self.val = (x[0] << 8) | x[1] << 4 | x[2] > def __int__(self): > return self.val > def __str__(self): > return self.tbl.get(self.val, '%.3x'%self.val) > > class mnc: > tbl = {0x15: 'Vodafone', > 0x30: 'T-Mobile', > 0x10: 'O2', > 0x33: 'Orange', > } > def __init__(self, num): > x = ((num & 0xf0) >> 4, > (num & 0xf)) > self.val = (x[1] << 4) | x[0] > def __int__(self): > return self.val > def __str__(self): > return self.tbl.get(self.val, '%.2x'%self.val) > > class SystemInfo: > pass > > class SystemInfo3(SystemInfo): > def __init__(self, b): > if isinstance(b, str): > b = hexdump(b) > assert(b[0] > 9) # len > assert(b[1] == 0x06) # discr > assert(b[2] == 0x1b) # sysinfo3 > self.cell = (b[3] << 8) | b[4] > self.mcc = mcc((b[5] << 8) | b[6]) > self.mnc = mnc(b[7]) > self.lac = (b[8] << 8) | b[9] > def __str__(self): > return 'Cell(%s, %s)'%(self.mcc,self.mnc) > > class SystemInfo4(SystemInfo): > def __init__(self, b): > if isinstance(b, str): > b = hexdump(b) > assert(b[0] > 7) # len > assert(b[1] == 0x06) # discr > assert(b[2] == 0x1c) # sysinfo4 > self.cell = None > self.mcc = mcc((b[3] << 8) | b[4]) > self.mnc = mnc(b[5]) > self.lac = (b[6] << 8) | b[7] > def __str__(self): > return 'Cell(%s, %s)'%(self.mcc,self.mnc) > > class Sysinfo(Parser): > _keys = {'arfcn':int, > 'time':int, > 'rxlev':int, > 'bsic':bsic, > 'si1':hexdump, > 'si2':hexdump, > 'si2bis':hexdump, > 'si2ter':hexdump, > 'si3':SystemInfo3, > 'si4':SystemInfo4, > 'ta':int} > def line(self, s): > (k,v) = s.split(None, 1) > if self._keys.has_key(k): > setattr(self, k, self._keys[k](v)) > else: > print k, v > return > > class RFMap: > arfcns = {} > cells = {} > def commit(self, obj): > if isinstance(obj, Sysinfo): > self.arfcns.setdefault(obj.arfcn, {}) > self.arfcns[obj.arfcn][str(obj.si3.mnc)] = None > self.arfcns[obj.arfcn][str(obj.si4.mnc)] = None > > self.cells.setdefault(obj.si3.cell, {}) > self.cells[obj.si3.cell][str(obj.si3.mnc)] = None > elif isinstance(obj, Power): > return > assert(isinstance(obj, Parser)) > > def rf_map(f): > smap = {'[power]':Power, '[sysinfo]':Sysinfo} > obj = None > m = RFMap() > > for x in getline(f): > if x[0] == '[': > if obj is not None: > m.commit(obj) > obj = smap[x]() > continue > if obj is None: > raise ValueError, 'Bad state' > obj.line(x) > > if obj is not None: > m.commit(obj) > > print 'Active ARFCNs:' > x = m.arfcns.keys() > x.sort() > for i in x: > print ' %4d:'%i, ','.join(m.arfcns[i]) > print > > print 'Active Cells:' > x = m.cells.keys() > x.sort() > for i in x: > print ' 0x%.4x'%i, ','.join(m.cells[i]) > print > > def main(argv): > if len(argv) > 1: > infile = open(argv[1]) > else: > from sys import stdin > infile = stdin > > rf_map(infile) > return 0 > > if __name__ == '__main__': > from sys import argv > raise SystemExit, main(argv) > > >

12 years, 11 months

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Nuttx for Calypso

by l--putt

Hi list! As you can see from the patch, I made some progress with a port of Nuttx to the Calypso platform. The UART doesn't work yet. The few possible tests with just the backlight suggest that the IRQ is working. More work required but I'd like to avoid doing the work twice. Stefan

12 years, 11 months

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about voice

by shrek wu

hi all, About voice，I have one question. In the latest git code, when I use bb to call other phone, it will product a file voice.raw. How I can play the voice.raw? which kind of format? 16bit or 8 bit pcm?16khz and 8khz?LSE or MSE? In fact i used the cooledit to play it, both 16khz and 8khz, it has only noise. Other question, I want to input voice from pc that run BB, then the voice can be sent by C123. But I found the voice that be sent by C123 is C123 input voice. Can we realize the idea? Best Regards Shrek W

12 years, 11 months

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Strange error

by Sun Ich

Hi When I try to load any program from firmware/board/compal_e88/ to my C118 phone, I receive error below: ioctl(TIOCGSERIAL): Invalid argument I upload program successfully and I receive DOWNLOAD ACK from phone properly, but then I receive this strange ioctl error. I'm running Ubuntu 9 and I tried to load compal_dsp_dump.compalram.bin layer1.compalram.bin loader.compalram.bin Result is same for all of the above. Please advice. Thanks

12 years, 11 months

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[PATCH 0/6] osmocom-bb: get in sync with libosmocore namespace changes

by pablo＠gnumonks.org

From: Pablo Neira Ayuso <pablo(a)gnumonks.org> This patchset gets osmocom-bb in sync with the namespace fixes for libosmocore. You can find them in pablo/namespace branch. Please, merge it. BTW: I had to temporarily disable mtk62xx compilation since I hit a linking error. This problem occurs in the current git tree. I already contacted Wolfram to let him know. diff --git a/src/Makefile b/src/Makefile index d6f556f..6ff4dc4 100644 --- a/src/Makefile +++ b/src/Makefile @@ -17,7 +17,7 @@ OSMOCORE_CONFIGURE_ENV= LIBOSMOCORE_LIBS=$(TOPDIR)/shared/libosmocore/build-host LIBOSMOVTY_CFLAGS=-I$(TOPDIR)/shared/libosmocore/include \ LIBOSMOGSM_CFLAGS=-I$(TOPDIR)/shared/libosmocore/include -all: libosmocore-target nofirmware firmware mtk-firmware +all: libosmocore-target nofirmware firmware nofirmware: libosmocore-host layer23 osmocon gsmmap libosmocore-host: shared/libosmocore/build-host/src/.libs/libosmocore.la Pablo Neira Ayuso (6): src: use namespace prefix osmo_timer* src: use namespace prefix osmo_fd* and osmo_select* src: use namespace prefix osmo_signal* src: use namespace prefix osmo_wqueue* src: use namespace prefix osmo_* for utils src: use namespace prefix osmo_* for crc16 functions

12 years, 11 months

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Re: hmm, sorry, data cable question

by labad jala

Hi again techies. Thanks for your advises and schemas. I already bought what was announced and illustrated as a mot t191 cable at a french company but it turned to be a "flash cable" with possibly wrong pinout and voltage. If you look at http://www.cellcorner.com/xshp/unlock-phone-codes/motorola-t190-t191-t193-u…, it's looks exactly the same one as I have. Did someone buy this one and used it successfully? I measured 4 volts when putting positive pin of my voltmeter to rx and negative pin on ground of the 2.5mm jack.. As said before, don't want to fry my moto. No cable, no project:( Sorry for my noobie question on this high level mailing list...

12 years, 11 months

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http git for nuttx-bb

by Sébastien Lorquet

Hello, I installed a git mirror with http access at http://repo.or.cz/r/nuttx-bb.git Regards Sebastien

12 years, 11 months

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Re: RFC: RTOS for Calypso

by Gregory Nutt

Hi, List, I heard through the grape vine that you are considering using NuttX. I don't want to influence your decision, but if the decision is final, I would like to offer any support to the project that I can give. > Indeed. The TI C5471 DSP/ARM chip seems to be virtually a predecessor of the Calypso. I have quite a bit of experience working with these TI dual core chips and would be happy to help out as much as possible. With the ARM7/c5 family, I have developed OS support (uClinux) for the C5471, DSC21, DSC24, and DM270. Also the DM320 (ARM9/c5, Linux). I founded this business in Costa Rica (http://www.ridgerun.com, also once called Cadenux). But have not been involved with the more recent ARM11/Cortex A8/c6 chips. > I'm already working on the IRQ subsystem and took a look at the UART. > But there are open questions, see above... There is a porting guide here may be helpful to you: http://nuttx.sourceforge.net/NuttxPortingGuide.html. But it does a some "To be provided" sections -- particulary in the IRQ section. > I have a c5 DSP bridge driver somewhere around on my backup disks as > well. I never released it into NuttX because there was never any > need. Perhaps that could be useful now. These DSP bridge drivers present interfaces to load programs into the DSP and to support an integrated, seamless messaging system between the ARM7 and the DSP. The DSP interfaces differ from chip to chip and the drivers that I was referring were targeted for uClinux. However, if that is something you are interested in, I would be happy to do the port a driver and integrate DSP messaging with the NuttX messaging. Greg

12 years, 11 months

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[PATCH] uart: make *_UART_NR platform independent

by Wolfram Sang

* convert *_UART_NR to enum uart_type in uart.h * make uart-functions use uart_type consistently (was uint8_t and int) * map uart_type to correct uart for mtk * (remove forgotten calypso-include for mtk while we are here) Binaries have been successfully tested with a Sciphone G2 and a Motorola C155. Signed-off-by: Wolfram Sang <wolfram(a)the-dreams.de> --- And I just wanted to get rid of some build warnings ;) src/target/firmware/board/mediatek/uart.c | 31 ++++++++++++--------------- src/target/firmware/calypso/uart.c | 26 +++++++++++----------- src/target/firmware/include/comm/sercomm.h | 4 --- src/target/firmware/include/console.h | 3 -- src/target/firmware/include/uart.h | 21 +++++++++++------- 5 files changed, 40 insertions(+), 45 deletions(-) diff --git a/src/target/firmware/board/mediatek/uart.c b/src/target/firmware/board/mediatek/uart.c index ff82245..6a87473 100644 --- a/src/target/firmware/board/mediatek/uart.c +++ b/src/target/firmware/board/mediatek/uart.c @@ -36,8 +36,6 @@ #include <comm/sercomm.h> -#include <calypso/irq.h> - /* MT622x */ #if 0 #define BASE_ADDR_UART1 0x80130000 @@ -48,8 +46,7 @@ /* MT 6235 */ #define BASE_ADDR_UART1 0x81030000 -//TODO make UART2 and 3 work -#define UART_REG(n,m) (BASE_ADDR_UART1 + (m)) +#define UART_REG(n,m) (BASE_ADDR_UART1 + (!n) * 0x10000 + (m)) #define LCR7BIT 0x80 #define LCRBFBIT 0x40 @@ -112,7 +109,7 @@ enum iir_bits { /* enable or disable the divisor latch for access to DLL, DLH */ -static void uart_set_lcr7bit(int uart, int on) +static void uart_set_lcr7bit(enum uart_type uart, int on) { uint8_t reg; @@ -125,7 +122,7 @@ static void uart_set_lcr7bit(int uart, int on) } static uint8_t old_lcr; -static void uart_set_lcr_bf(int uart, int on) +static void uart_set_lcr_bf(enum uart_type uart, int on) { if (on) { old_lcr = readb(UART_REG(uart, LCR)); @@ -136,7 +133,7 @@ static void uart_set_lcr_bf(int uart, int on) } /* Enable or disable the TCR_TLR latch bit in MCR[6] */ -static void uart_set_mcr6bit(int uart, int on) +static void uart_set_mcr6bit(enum uart_type uart, int on) { uint8_t mcr; /* we assume EFR[4] is always set to 1 */ @@ -148,7 +145,7 @@ static void uart_set_mcr6bit(int uart, int on) writeb(mcr, UART_REG(uart, MCR)); } -static void uart_reg_write(int uart, enum uart_reg reg, uint8_t val) +static void uart_reg_write(enum uart_type uart, enum uart_reg reg, uint8_t val) { if (reg & LCRBFBIT) uart_set_lcr_bf(uart, 1); @@ -168,7 +165,7 @@ static void uart_reg_write(int uart, enum uart_reg reg, uint8_t val) } /* read from a UART register, applying any required latch bits */ -static uint8_t uart_reg_read(int uart, enum uart_reg reg) +static uint8_t uart_reg_read(enum uart_type uart, enum uart_reg reg) { uint8_t ret; @@ -271,7 +268,7 @@ static void uart_irq_handler_sercomm(__unused int irqnr) } } -void uart_init(uint8_t uart, __unused uint8_t interrupts) +void uart_init(enum uart_type uart, __unused uint8_t interrupts) { /* no interrupts, only polling so far */ @@ -302,7 +299,7 @@ void uart_init(uint8_t uart, __unused uint8_t interrupts) uart_set_lcr7bit(uart, 0); } -void uart_poll(uint8_t uart) { +void uart_poll(enum uart_type uart) { if(uart == CONS_UART_NR) { uart_irq_handler_cons(0); } else { @@ -310,7 +307,7 @@ void uart_poll(uint8_t uart) { } } -void uart_irq_enable(uint8_t uart, enum uart_irq irq, int on) +void uart_irq_enable(enum uart_type uart, enum uart_irq irq, int on) { uint8_t ier = uart_reg_read(uart, IER); uint8_t mask = 0; @@ -333,7 +330,7 @@ void uart_irq_enable(uint8_t uart, enum uart_irq irq, int on) } -void uart_putchar_wait(uint8_t uart, int c) +void uart_putchar_wait(enum uart_type uart, int c) { /* wait while TX FIFO indicates full */ while (~readb(UART_REG(uart, LSR)) & 0x20) { } @@ -342,7 +339,7 @@ void uart_putchar_wait(uint8_t uart, int c) writeb(c, UART_REG(uart, RBR)); } -int uart_putchar_nb(uint8_t uart, int c) +int uart_putchar_nb(enum uart_type uart, int c) { /* if TX FIFO indicates full, abort */ if (~readb(UART_REG(uart, LSR)) & 0x20) @@ -352,7 +349,7 @@ int uart_putchar_nb(uint8_t uart, int c) return 1; } -int uart_getchar_nb(uint8_t uart, uint8_t *ch) +int uart_getchar_nb(enum uart_type uart, uint8_t *ch) { uint8_t lsr; @@ -379,7 +376,7 @@ int uart_getchar_nb(uint8_t uart, uint8_t *ch) return 1; } -int uart_tx_busy(uint8_t uart) +int uart_tx_busy(enum uart_type uart) { /* Check THRE bit (LSR[5]) to see if FIFO is full */ if (~readb(UART_REG(uart, LSR)) & 0x20) @@ -409,7 +406,7 @@ static const uint16_t divider[] = { [UART_921600] = 7, /* would need UART_REG(HIGHSPEED) = 1 */ }; -int uart_baudrate(uint8_t uart, enum uart_baudrate bdrt) +int uart_baudrate(enum uart_type uart, enum uart_baudrate bdrt) { uint16_t div; diff --git a/src/target/firmware/calypso/uart.c b/src/target/firmware/calypso/uart.c index d3ede4d..0355ee2 100644 --- a/src/target/firmware/calypso/uart.c +++ b/src/target/firmware/calypso/uart.c @@ -112,7 +112,7 @@ enum iir_bits { #define UART_REG_UIR 0xffff6000 /* enable or disable the divisor latch for access to DLL, DLH */ -static void uart_set_lcr7bit(int uart, int on) +static void uart_set_lcr7bit(enum uart_type uart, int on) { uint8_t reg; @@ -125,7 +125,7 @@ static void uart_set_lcr7bit(int uart, int on) } static uint8_t old_lcr; -static void uart_set_lcr_bf(int uart, int on) +static void uart_set_lcr_bf(enum uart_type uart, int on) { if (on) { old_lcr = readb(UART_REG(uart, LCR)); @@ -136,7 +136,7 @@ static void uart_set_lcr_bf(int uart, int on) } /* Enable or disable the TCR_TLR latch bit in MCR[6] */ -static void uart_set_mcr6bit(int uart, int on) +static void uart_set_mcr6bit(enum uart_type uart, int on) { uint8_t mcr; /* we assume EFR[4] is always set to 1 */ @@ -148,7 +148,7 @@ static void uart_set_mcr6bit(int uart, int on) writeb(mcr, UART_REG(uart, MCR)); } -static void uart_reg_write(int uart, enum uart_reg reg, uint8_t val) +static void uart_reg_write(enum uart_type uart, enum uart_reg reg, uint8_t val) { if (reg & LCRBFBIT) uart_set_lcr_bf(uart, 1); @@ -168,7 +168,7 @@ static void uart_reg_write(int uart, enum uart_reg reg, uint8_t val) } /* read from a UART register, applying any required latch bits */ -static uint8_t uart_reg_read(int uart, enum uart_reg reg) +static uint8_t uart_reg_read(enum uart_type uart, enum uart_reg reg) { uint8_t ret; @@ -276,7 +276,7 @@ static const uint8_t uart2irq[] = { [1] = IRQ_UART_MODEM, }; -void uart_init(uint8_t uart, uint8_t interrupts) +void uart_init(enum uart_type uart, uint8_t interrupts) { uint8_t irq = uart2irq[uart]; @@ -330,7 +330,7 @@ void uart_init(uint8_t uart, uint8_t interrupts) uart_set_lcr7bit(uart, 0); } -void uart_poll(uint8_t uart) { +void uart_poll(enum uart_type uart) { if(uart == CONS_UART_NR) { uart_irq_handler_cons(0); } else { @@ -338,7 +338,7 @@ void uart_poll(uint8_t uart) { } } -void uart_irq_enable(uint8_t uart, enum uart_irq irq, int on) +void uart_irq_enable(enum uart_type uart, enum uart_irq irq, int on) { uint8_t ier = uart_reg_read(uart, IER); uint8_t mask = 0; @@ -361,7 +361,7 @@ void uart_irq_enable(uint8_t uart, enum uart_irq irq, int on) } -void uart_putchar_wait(uint8_t uart, int c) +void uart_putchar_wait(enum uart_type uart, int c) { /* wait while TX FIFO indicates full */ while (readb(UART_REG(uart, SSR)) & 0x01) { } @@ -370,7 +370,7 @@ void uart_putchar_wait(uint8_t uart, int c) writeb(c, UART_REG(uart, THR)); } -int uart_putchar_nb(uint8_t uart, int c) +int uart_putchar_nb(enum uart_type uart, int c) { /* if TX FIFO indicates full, abort */ if (readb(UART_REG(uart, SSR)) & 0x01) @@ -380,7 +380,7 @@ int uart_putchar_nb(uint8_t uart, int c) return 1; } -int uart_getchar_nb(uint8_t uart, uint8_t *ch) +int uart_getchar_nb(enum uart_type uart, uint8_t *ch) { uint8_t lsr; @@ -407,7 +407,7 @@ int uart_getchar_nb(uint8_t uart, uint8_t *ch) return 1; } -int uart_tx_busy(uint8_t uart) +int uart_tx_busy(enum uart_type uart) { if (readb(UART_REG(uart, SSR)) & 0x01) return 1; @@ -423,7 +423,7 @@ static const uint16_t divider[] = { [UART_921600] = 1, /* 812,500! (-3% would be 893,952) */ }; -int uart_baudrate(uint8_t uart, enum uart_baudrate bdrt) +int uart_baudrate(enum uart_type uart, enum uart_baudrate bdrt) { uint16_t div; diff --git a/src/target/firmware/include/comm/sercomm.h b/src/target/firmware/include/comm/sercomm.h index 54256b5..4c23b31 100644 --- a/src/target/firmware/include/comm/sercomm.h +++ b/src/target/firmware/include/comm/sercomm.h @@ -1,12 +1,8 @@ #ifndef _SERCOMM_H #define _SERCOMM_H -/* SERCOMM layer on UART1 (modem UART) */ - #include <osmocom/core/msgb.h> -#define SERCOMM_UART_NR 1 - #define HDLC_FLAG 0x7E #define HDLC_ESCAPE 0x7D diff --git a/src/target/firmware/include/console.h b/src/target/firmware/include/console.h index 7146e99..b5a83f5 100644 --- a/src/target/firmware/include/console.h +++ b/src/target/firmware/include/console.h @@ -11,9 +11,6 @@ int cons_putchar(char c); int cons_rb_flush(void); void cons_init(void); -/* We want the console on UART 0 (IRDA UART) */ -#define CONS_UART_NR 0 - /* Size of the static ring-buffer that we keep for console print messages */ #define CONS_RB_SIZE 4096 diff --git a/src/target/firmware/include/uart.h b/src/target/firmware/include/uart.h index 81d7a15..eedb006 100644 --- a/src/target/firmware/include/uart.h +++ b/src/target/firmware/include/uart.h @@ -3,6 +3,11 @@ #include <stdint.h> +enum uart_type { + CONS_UART_NR, + SERCOMM_UART_NR, +}; + enum uart_baudrate { UART_38400, UART_57600, @@ -13,20 +18,20 @@ enum uart_baudrate { UART_921600, }; -void uart_init(uint8_t uart, uint8_t interrupts); -void uart_putchar_wait(uint8_t uart, int c); -int uart_putchar_nb(uint8_t uart, int c); -int uart_getchar_nb(uint8_t uart, uint8_t *ch); -int uart_tx_busy(uint8_t uart); -int uart_baudrate(uint8_t uart, enum uart_baudrate bdrt); +void uart_init(enum uart_type uart, uint8_t interrupts); +void uart_putchar_wait(enum uart_type uart, int c); +int uart_putchar_nb(enum uart_type uart, int c); +int uart_getchar_nb(enum uart_type uart, uint8_t *ch); +int uart_tx_busy(enum uart_type uart); +int uart_baudrate(enum uart_type uart, enum uart_baudrate bdrt); enum uart_irq { UART_IRQ_TX_EMPTY, UART_IRQ_RX_CHAR, }; -void uart_irq_enable(uint8_t uart, enum uart_irq irq, int on); +void uart_irq_enable(enum uart_type uart, enum uart_irq irq, int on); -void uart_poll(uint8_t uart); +void uart_poll(enum uart_type uart); #endif /* _UART_H */ -- 1.7.2.5

12 years, 11 months

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hi all

by 麦田守望

do you know the mtk chip MT6217 it is usb interface chip we can use to make a GSM network the mt6217 with pc

12 years, 11 months

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Re: Power management

by Dieter Spaar

Hello Stefan, On Tue, 17 May 2011 00:09:13 +0200, "l--putt" <ichgeh(a)l--putt.de> wrote: > > Saving power > Having everything on and at maximum clock drains the battery _fast_! > With the ULPD, we actually have the appropriate solution build into the > Calypso. I guess other chipsets have something similar. > It is neat to get the timing and power sequence right. But since the > TDMA timing is affected, Layer 1 must be aware of those clock/power > changes or at least tolerate to be turned on and off. Does anybody right > away have ideas how to approach this? A few notes, I don't remember the details: The basic idea is to only receive in idle mode when its necessary. This means listening only for the paging group of the IMSI and doing the neighbour cell measurements. During the other time the processor can be stopped. There are different levels to which extend the clock is stopped, for saving the most power only the 32 kHz crystal remains active. However this requires some calibration, otherwise the TDMA frames could be missed after sleeping. Most of this calibration can be done with the help of the hardware, its always done before switching to 32 kHz. Best regards, Dieter -- Dieter Spaar, Germany spaar(a)mirider.augusta.de

12 years, 11 months

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Power management

by l--putt

Hi list! Some time ago Harald suggested to create a complete phone, at least with minimal features. Since this hasn't been covered yet and we will have to rewrite some parts during RTOS porting anyway, I think we should consider some kind of power management: Saving power Having everything on and at maximum clock drains the battery _fast_! With the ULPD, we actually have the appropriate solution build into the Calypso. I guess other chipsets have something similar. It is neat to get the timing and power sequence right. But since the TDMA timing is affected, Layer 1 must be aware of those clock/power changes or at least tolerate to be turned on and off. Does anybody right away have ideas how to approach this? Charger The C155 has a dedicated chip which you probably just have to turn on. On the C123, it's a bit more complex but the algorithms don't seem to be too complex. Has anybody tried this already? State-of-Charge For the usual concepts on batteryuniversity.com, a random book from the university lib, and some papers, we would need some means to measure the discharge current. No Compal phone provides this since the voltage regulators are connected directly to the battery. The gta02 avoids this with a dedicated Coulomb-counting chip. The gta01 doesn't care!? Maybe the battery voltage and temperature is sufficient for reasonably correct estimates. If not, we could try to model the current. However, this requires some kind of central power management that knows activated devices, their clocks, etc. I would volunteer for the latter and C155-charging. However, I lack a C123 for tests and don't want to be responsible for exploding phones ;) Integration of the ULPD is a bit more GSM-related. Might turn out to be interesting... Cheers, Stefan

12 years, 11 months

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linking error on board mt62xx (current git tree)

by Pablo Neira Ayuso

Hi Wolfram, I hit the following linking error in the current LD board/mt62xx/loader_mtk.mtkram.elf arm-elf-ld: address 0x400050ec of board/mt62xx/loader_mtk.mtkram.elf section .text is not within region LRAM make[1]: *** [board/mt62xx/loader_mtk.mtkram.elf] Error 1 I'm not familiar with those bits, any clue on what's wrong? Thanks.

12 years, 11 months

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MacOSX build

by Klaus Rechert

Hi, some quick notes on the MacOSX build. Current git builds fine using the perbuilt GNUARM MacOS toolchain except that GCC 3.3 does not support the option -Wextra. There are also some issues building mtk firmware but this seems to be a more general issue. Cheers Klaus diff --git a/src/target/firmware/Makefile.inc b/src/target/firmware/Makefile.inc index 1f54031..c8f4323 100644 --- a/src/target/firmware/Makefile.inc +++ b/src/target/firmware/Makefile.inc @@ -12,7 +12,7 @@ OBJCOPY=objcopy DEBUGF=dwarf-2 CFLAGS=-mcpu=arm7tdmi $(INCLUDES) -CFLAGS += -Wall -Wextra -Wcast-align -Wimplicit -Wunused +CFLAGS += -Wall -Wcast-align -Wimplicit -Wunused CFLAGS += -Wswitch -Wredundant-decls -Wreturn-type -Wshadow -Wnested-externs CFLAGS += -Wbad-function-cast -Wsign-compare -Waggregate-return CFLAGS += -Os -ffunction-sections

12 years, 11 months

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Osmocom building in Ubuntu Error

by Sun Ich

Hi I try to compile osmocom in Ubuntu, I have gcc 4.4.3 and I installed binutils 2.20 for ARM successfully and I have arm-elf-* binaries in PATH directory when I run make in src folder of osmocom, I get error: unknown instruction "ror xor" something something.... What's problem, do I missing something? Thanks

12 years, 11 months

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baseband-devel May 2011