Use OsmocomBB as OpenBTS / airprobe clock generator
Hi! Recently we've had the idea of using OsmocomBB with a simple firmware that synchronizes to an existing GSM networks FCCH and use the resulting 13MHz clock to drive the USRP for airprobe or OpenBTS. Ideally, we would even use the Calypso-internal PLL (for ARM or DSP) to multiply it up to the required 52 MHz. However, neither the Openmoko nor the Compal/Motorola phones expose any of the 3 clock output pads :( So the only choice is to use something along the lines of the http://focus.ti.com/docs/prod/folders/print/cdcvf25084.html as a quad clock multiplier and attach it to the CLK13OUT signal of the phone. The chip is available for 9 USD in single quantities at digikey, and possibly cheaper at other sources. Combined with a sub-20EUR phone it might be a very cheap but still accurate frequency source for OpenBTS - at least as long as there are any commercial gsm networks available. Regards, Harald -- - Harald Welte <laforge@gnumonks.org> http://laforge.gnumonks.org/ ============================================================================ "Privacy in residential applications is a desirable marketing option." (ETSI EN 300 175-7 Ch. A6)
Hi, The Altera Cyclone on the USRP1 has two internal PLL. Has anybody tried to use those to get a internal 52 MHz clock from an external 13 MHz input ? I've been wondering about that for a while now ... Sylvain
Hi! On Sat, Apr 10, 2010 at 11:57:12PM +0200, Sylvain Munaut wrote:
The Altera Cyclone on the USRP1 has two internal PLL.
oh, great, even better. We were speculating about that for some time and then thought it might be easier to generate the signal externally than to set up the proprietary toolchain fro building a modified version of the FPGA bitstream.
Has anybody tried to use those to get a internal 52 MHz clock from an external 13 MHz input ?
Maybe a good idea to ask that at gnuradio-discuss and the openbts mailing lists. Regards, Harald -- - Harald Welte <laforge@gnumonks.org> http://laforge.gnumonks.org/ ============================================================================ "Privacy in residential applications is a desirable marketing option." (ETSI EN 300 175-7 Ch. A6)
Hi, interesting idea... Harald Welte wrote:
Ideally, we would even use the Calypso-internal PLL (for ARM or DSP) to multiply it up to the required 52 MHz. However, neither the Openmoko nor the Compal/Motorola phones expose any of the 3 clock output pads :(
Hmm, 3 output pads? I only see DPLLCLK and CLKOUT_DSP, the third one would be CLKX_SPI, but can that one be used for this purpose? I looked at the Motorola W220, which uses the DPLLCLK-pin as TSPACT5 wired through a buffer to GSM900_TX of the antenna switch. see: http://www.steve-m.de/projects/osmocom/w220_dpllclk.jpg The pin on the buffer is quite well accessible, so we could tie it to low (and disable TX with that, but we don't need that anyway, right?) and use VC1B as clock output. Our code already runs on the W220, but we would need a driver for the Si4210 GSM transceiver. Regards, Steve
Hi once again, Steve Markgraf wrote:
I looked at the Motorola W220, which uses the DPLLCLK-pin as TSPACT5 wired through a buffer to GSM900_TX of the antenna switch.
Exactly the same design on the Motorola C168 by the way, which was manufactured by Chi-Mei, too. Both use the Calypso romloader and have the UART_MODEM wired to the headphone plug, like the Compal phones. But the C168 wasn't sold in Europe as it seems. Regards, Steve
Hi Steve, On Sun, Apr 11, 2010 at 01:28:27AM +0200, Steve Markgraf wrote:
Ideally, we would even use the Calypso-internal PLL (for ARM or DSP) to multiply it up to the required 52 MHz. However, neither the Openmoko nor the Compal/Motorola phones expose any of the 3 clock output pads :(
Hmm, 3 output pads? I only see DPLLCLK and CLKOUT_DSP, the third one would be CLKX_SPI, but can that one be used for this purpose?
The third one is MCLK, i.e. the clock that the Calypos PLL feeds into the ARM core.
I looked at the Motorola W220, which uses the DPLLCLK-pin as TSPACT5 wired through a buffer to GSM900_TX of the antenna switch.
see: http://www.steve-m.de/projects/osmocom/w220_dpllclk.jpg
The pin on the buffer is quite well accessible, so we could tie it to low (and disable TX with that, but we don't need that anyway, right?) and use VC1B as clock output.
Yes, I agree, this should work just fine. However, using the Altera internal PLL to multiply from 13 to 52 sounds even better!
Our code already runs on the W220, but we would need a driver for the Si4210 GSM transceiver.
That doesn't sound hard. Didn't you say that you have documentation? -- - Harald Welte <laforge@gnumonks.org> http://laforge.gnumonks.org/ ============================================================================ "Privacy in residential applications is a desirable marketing option." (ETSI EN 300 175-7 Ch. A6)
Hi, On 11.04.2010 17:54, Steve Markgraf wrote:
The third one is MCLK, i.e. the clock that the Calypos PLL feeds into the ARM core.
Ah, okay. But this one isn't accessible on all currently known phones anyway.
Just as an update on this idea: The Pirelli DP-L10 I have been playing around with recently exposes the MCLK pin. I've added a summary in the wiki: http://bb.osmocom.org/trac/wiki/PirelliDPL10#Phoneasclockgenerator Regards, Steve
Hi guys, I'd like to build a test scenario for my thesis based on a Motorola C123 and a PLL such as this http://search.digikey.com/us/en/products/ICS501MLFT/800-1036-1-ND/1916104 Like this, I'd feed the multiplied clock to a USRP1 to run OpenBTS reliably. Would you help me choose the correct PLL if you understand the topic? I have little experience with circuit design. Regards, Martin Janovský Dne 21.1.2011 17:47, Steve Markgraf napsal(a):
Hi,
On 11.04.2010 17:54, Steve Markgraf wrote:
The third one is MCLK, i.e. the clock that the Calypos PLL feeds into the ARM core. Ah, okay. But this one isn't accessible on all currently known phones anyway. Just as an update on this idea: The Pirelli DP-L10 I have been playing around with recently exposes the MCLK pin.
I've added a summary in the wiki:
http://bb.osmocom.org/trac/wiki/PirelliDPL10#Phoneasclockgenerator
Regards, Steve
Hi,
I'd like to build a test scenario for my thesis based on a Motorola C123 and a PLL such as this http://search.digikey.com/us/en/products/ICS501MLFT/800-1036-1-ND/1916104
Like this, I'd feed the multiplied clock to a USRP1 to run OpenBTS reliably. Would you help me choose the correct PLL if you understand the topic? I have little experience with circuit design.
That PLL looks fine, should work AFAICT. Maybe just check the clock levels at the C123 output. If it's 2.5v logic you may need to manually bias the PLL clock input and AC feed the clock. Cheers, Sylvain
Hi Martin, I'd like to suggest you to consider clock-tamer or new design as external clock for USRP - http://code.google.com/p/clock-tamer/ . It is open source software and hardware project and it is was specifically designed to be used with USRP. It is possible to use phone as external clock for openBTS, but except proof of concept, that solution does not have practical value. Regards Fadil On Wed, Mar 14, 2012 at 10:54 AM, Martin Janovský <martian@seznam.cz> wrote:
Hi guys,
I'd like to build a test scenario for my thesis based on a Motorola C123 and a PLL such as this http://search.digikey.com/us/en/products/ICS501MLFT/800-1036-1-ND/1916104
Like this, I'd feed the multiplied clock to a USRP1 to run OpenBTS reliably. Would you help me choose the correct PLL if you understand the topic? I have little experience with circuit design.
Regards,
Martin Janovský
Dne 21.1.2011 17:47, Steve Markgraf napsal(a):
Hi,
On 11.04.2010 17:54, Steve Markgraf wrote:
The third one is MCLK, i.e. the clock that the Calypos PLL feeds into the ARM core.
Ah, okay. But this one isn't accessible on all currently known phones anyway.
Just as an update on this idea: The Pirelli DP-L10 I have been playing around with recently exposes the MCLK pin.
I've added a summary in the wiki:
http://bb.osmocom.org/trac/wiki/PirelliDPL10#Phoneasclockgenerator
Regards, Steve
I think the osmocomBB signal generator would be a great idea; clock-tamers are significantly more expensive than calypso phones. 2012/3/14 Fadil Berisha <f.koliqi@gmail.com>:
Hi Martin,
I'd like to suggest you to consider clock-tamer or new design as external clock for USRP - http://code.google.com/p/clock-tamer/ . It is open source software and hardware project and it is was specifically designed to be used with USRP. It is possible to use phone as external clock for openBTS, but except proof of concept, that solution does not have practical value.
Regards
Fadil
On Wed, Mar 14, 2012 at 10:54 AM, Martin Janovský <martian@seznam.cz> wrote:
Hi guys,
I'd like to build a test scenario for my thesis based on a Motorola C123 and a PLL such as this http://search.digikey.com/us/en/products/ICS501MLFT/800-1036-1-ND/1916104
Like this, I'd feed the multiplied clock to a USRP1 to run OpenBTS reliably. Would you help me choose the correct PLL if you understand the topic? I have little experience with circuit design.
Regards,
Martin Janovský
Dne 21.1.2011 17:47, Steve Markgraf napsal(a):
Hi,
On 11.04.2010 17:54, Steve Markgraf wrote:
The third one is MCLK, i.e. the clock that the Calypos PLL feeds into the ARM core.
Ah, okay. But this one isn't accessible on all currently known phones anyway.
Just as an update on this idea: The Pirelli DP-L10 I have been playing around with recently exposes the MCLK pin.
I've added a summary in the wiki:
http://bb.osmocom.org/trac/wiki/PirelliDPL10#Phoneasclockgenerator
Regards, Steve
On Wed, Mar 14, 2012 at 03:03:48PM -0700, Kurtis Heimerl wrote:
I think the osmocomBB signal generator would be a great idea; clock-tamers are significantly more expensive than calypso phones.
I agree with Kurtis. In fact, I already tried to make such a circuit using a Ti CDCVF25084 some time ago, but it wasn't as straight-forwardd as I hoped and it was never completed :( -- - Harald Welte <laforge@gnumonks.org> http://laforge.gnumonks.org/ ============================================================================ "Privacy in residential applications is a desirable marketing option." (ETSI EN 300 175-7 Ch. A6)
Hi Harald, On Thu, Mar 15, 2012 at 12:45:35AM +0100, Harald Welte wrote:
In fact, I already tried to make such a circuit using a Ti CDCVF25084 some time ago, but it wasn't as straight-forwardd as I hoped and it was never completed :(
A while back there was a posting[1] on the OpenBTS ML that mentioned positive results using this exact PLL as clock input for a USRP. The posting itself does not contain the part#, but I remember to have read it in a follow up post or so. This setup did not use a phone as input to the PLL, but nevertheless used such a PLL to feed the USRP. Could you please elaborate on which problems you were facing? Kind regards, -Alexander Huemer [1] http://sourceforge.net/mailarchive/message.php?msg_id=24642256 [?] http://lists.osmocom.org/pipermail/baseband-devel/2010-April/000322.html
On Thu, Mar 15, 2012 at 10:04:37AM +0100, Alexander Huemer wrote:
Could you please elaborate on which problems you were facing?
I think it was mostly related to the levels and coupling, possibly combined with the 13 MHz signal being a sine wave and not square whihc I believe the TI PLL expects. It's probably 1.5 or 2 years since I tried that, I honestly don't remember the details. -- - Harald Welte <laforge@gnumonks.org> http://laforge.gnumonks.org/ ============================================================================ "Privacy in residential applications is a desirable marketing option." (ETSI EN 300 175-7 Ch. A6)
On Thu, Mar 15, 2012 at 10:56:57AM +0100, Harald Welte wrote:
I think it was mostly related to the levels and coupling, possibly combined with the 13 MHz signal being a sine wave and not square whihc I believe the TI PLL expects. As I understand the datasheet of the CDCVF25084 it can very well be the case that a sine wave input makes trouble. Assuming this is the case, could something like a Schmitt trigger between the sine wave source and the PLL improve the situation? Or would that add jitter or some other negative effects to the signal?
Kind regards, -Alexander Huemer
Hi Alexander, On Thu, 15 Mar 2012 11:51:06 +0100, Alexander Huemer <alexander.huemer@xx.vu> wrote:
Assuming this is the case, could something like a Schmitt trigger between the sine wave source and the PLL improve the situation? Or would that add jitter or some other negative effects to the signal?
74AC(T)04 are considered quite excellent input stages (or amplifiers for fanout) for timing signals. See, for example, this posting on the "time-nuts" mailinglist (which is dedicated to precision frequency measurement/timekeeping): http://www.mail-archive.com/time-nuts@febo.com/msg26830.html With a feedback resistors (say, a few 10kOhm) and a series input capacitor (a few nF) the bias-DC of the input will automatically adjust to 1/2 duty cycle. Using anything more fancy, for example high-bandwidth comparators, is frowned upon. Chris
Thanks everyone for opinion. I'm going to pursue the idea as far as I can, welcoming your advice in the future. Price is my concern as well. The ClockTamer might be excellent but it's way over the top for me at the moment. There are 7E9 people in the world for a reason. Some of us can work on different problems than others. :) Dne 15.3.2012 00:45, Harald Welte napsal(a):
On Wed, Mar 14, 2012 at 03:03:48PM -0700, Kurtis Heimerl wrote:
I think the osmocomBB signal generator would be a great idea; clock-tamers are significantly more expensive than calypso phones. I agree with Kurtis.
In fact, I already tried to make such a circuit using a Ti CDCVF25084 some time ago, but it wasn't as straight-forwardd as I hoped and it was never completed :(
participants (8)
-
Alexander Huemer -
Christian Vogel -
Fadil Berisha -
Harald Welte -
Kurtis Heimerl -
Martin Janovský -
Steve Markgraf -
Sylvain Munaut