- baseband-devel - lists.osmocom.org

http git for nuttx-bb
by Sébastien Lorquet 19 May '11

19 May '11

Hello, I installed a git mirror with http access at http://repo.or.cz/r/nuttx-bb.git Regards Sebastien

1 0

Re: RFC: RTOS for Calypso
by Gregory Nutt 19 May '11

19 May '11

Hi, List, I heard through the grape vine that you are considering using NuttX. I don't want to influence your decision, but if the decision is final, I would like to offer any support to the project that I can give. > Indeed. The TI C5471 DSP/ARM chip seems to be virtually a predecessor of the Calypso. I have quite a bit of experience working with these TI dual core chips and would be happy to help out as much as possible. With the ARM7/c5 family, I have developed OS support (uClinux) for the C5471, DSC21, DSC24, and DM270. Also the DM320 (ARM9/c5, Linux). I founded this business in Costa Rica (http://www.ridgerun.com, also once called Cadenux). But have not been involved with the more recent ARM11/Cortex A8/c6 chips. > I'm already working on the IRQ subsystem and took a look at the UART. > But there are open questions, see above... There is a porting guide here may be helpful to you: http://nuttx.sourceforge.net/NuttxPortingGuide.html. But it does a some "To be provided" sections -- particulary in the IRQ section. > I have a c5 DSP bridge driver somewhere around on my backup disks as > well. I never released it into NuttX because there was never any > need. Perhaps that could be useful now. These DSP bridge drivers present interfaces to load programs into the DSP and to support an integrated, seamless messaging system between the ARM7 and the DSP. The DSP interfaces differ from chip to chip and the drivers that I was referring were targeted for uClinux. However, if that is something you are interested in, I would be happy to do the port a driver and integrate DSP messaging with the NuttX messaging. Greg

2 1

[PATCH] uart: make *_UART_NR platform independent
by Wolfram Sang 18 May '11

18 May '11

* convert *_UART_NR to enum uart_type in uart.h * make uart-functions use uart_type consistently (was uint8_t and int) * map uart_type to correct uart for mtk * (remove forgotten calypso-include for mtk while we are here) Binaries have been successfully tested with a Sciphone G2 and a Motorola C155. Signed-off-by: Wolfram Sang <wolfram(a)the-dreams.de> --- And I just wanted to get rid of some build warnings ;) src/target/firmware/board/mediatek/uart.c | 31 ++++++++++++--------------- src/target/firmware/calypso/uart.c | 26 +++++++++++----------- src/target/firmware/include/comm/sercomm.h | 4 --- src/target/firmware/include/console.h | 3 -- src/target/firmware/include/uart.h | 21 +++++++++++------- 5 files changed, 40 insertions(+), 45 deletions(-) diff --git a/src/target/firmware/board/mediatek/uart.c b/src/target/firmware/board/mediatek/uart.c index ff82245..6a87473 100644 --- a/src/target/firmware/board/mediatek/uart.c +++ b/src/target/firmware/board/mediatek/uart.c @@ -36,8 +36,6 @@ #include <comm/sercomm.h> -#include <calypso/irq.h> - /* MT622x */ #if 0 #define BASE_ADDR_UART1 0x80130000 @@ -48,8 +46,7 @@ /* MT 6235 */ #define BASE_ADDR_UART1 0x81030000 -//TODO make UART2 and 3 work -#define UART_REG(n,m) (BASE_ADDR_UART1 + (m)) +#define UART_REG(n,m) (BASE_ADDR_UART1 + (!n) * 0x10000 + (m)) #define LCR7BIT 0x80 #define LCRBFBIT 0x40 @@ -112,7 +109,7 @@ enum iir_bits { /* enable or disable the divisor latch for access to DLL, DLH */ -static void uart_set_lcr7bit(int uart, int on) +static void uart_set_lcr7bit(enum uart_type uart, int on) { uint8_t reg; @@ -125,7 +122,7 @@ static void uart_set_lcr7bit(int uart, int on) } static uint8_t old_lcr; -static void uart_set_lcr_bf(int uart, int on) +static void uart_set_lcr_bf(enum uart_type uart, int on) { if (on) { old_lcr = readb(UART_REG(uart, LCR)); @@ -136,7 +133,7 @@ static void uart_set_lcr_bf(int uart, int on) } /* Enable or disable the TCR_TLR latch bit in MCR[6] */ -static void uart_set_mcr6bit(int uart, int on) +static void uart_set_mcr6bit(enum uart_type uart, int on) { uint8_t mcr; /* we assume EFR[4] is always set to 1 */ @@ -148,7 +145,7 @@ static void uart_set_mcr6bit(int uart, int on) writeb(mcr, UART_REG(uart, MCR)); } -static void uart_reg_write(int uart, enum uart_reg reg, uint8_t val) +static void uart_reg_write(enum uart_type uart, enum uart_reg reg, uint8_t val) { if (reg & LCRBFBIT) uart_set_lcr_bf(uart, 1); @@ -168,7 +165,7 @@ static void uart_reg_write(int uart, enum uart_reg reg, uint8_t val) } /* read from a UART register, applying any required latch bits */ -static uint8_t uart_reg_read(int uart, enum uart_reg reg) +static uint8_t uart_reg_read(enum uart_type uart, enum uart_reg reg) { uint8_t ret; @@ -271,7 +268,7 @@ static void uart_irq_handler_sercomm(__unused int irqnr) } } -void uart_init(uint8_t uart, __unused uint8_t interrupts) +void uart_init(enum uart_type uart, __unused uint8_t interrupts) { /* no interrupts, only polling so far */ @@ -302,7 +299,7 @@ void uart_init(uint8_t uart, __unused uint8_t interrupts) uart_set_lcr7bit(uart, 0); } -void uart_poll(uint8_t uart) { +void uart_poll(enum uart_type uart) { if(uart == CONS_UART_NR) { uart_irq_handler_cons(0); } else { @@ -310,7 +307,7 @@ void uart_poll(uint8_t uart) { } } -void uart_irq_enable(uint8_t uart, enum uart_irq irq, int on) +void uart_irq_enable(enum uart_type uart, enum uart_irq irq, int on) { uint8_t ier = uart_reg_read(uart, IER); uint8_t mask = 0; @@ -333,7 +330,7 @@ void uart_irq_enable(uint8_t uart, enum uart_irq irq, int on) } -void uart_putchar_wait(uint8_t uart, int c) +void uart_putchar_wait(enum uart_type uart, int c) { /* wait while TX FIFO indicates full */ while (~readb(UART_REG(uart, LSR)) & 0x20) { } @@ -342,7 +339,7 @@ void uart_putchar_wait(uint8_t uart, int c) writeb(c, UART_REG(uart, RBR)); } -int uart_putchar_nb(uint8_t uart, int c) +int uart_putchar_nb(enum uart_type uart, int c) { /* if TX FIFO indicates full, abort */ if (~readb(UART_REG(uart, LSR)) & 0x20) @@ -352,7 +349,7 @@ int uart_putchar_nb(uint8_t uart, int c) return 1; } -int uart_getchar_nb(uint8_t uart, uint8_t *ch) +int uart_getchar_nb(enum uart_type uart, uint8_t *ch) { uint8_t lsr; @@ -379,7 +376,7 @@ int uart_getchar_nb(uint8_t uart, uint8_t *ch) return 1; } -int uart_tx_busy(uint8_t uart) +int uart_tx_busy(enum uart_type uart) { /* Check THRE bit (LSR[5]) to see if FIFO is full */ if (~readb(UART_REG(uart, LSR)) & 0x20) @@ -409,7 +406,7 @@ static const uint16_t divider[] = { [UART_921600] = 7, /* would need UART_REG(HIGHSPEED) = 1 */ }; -int uart_baudrate(uint8_t uart, enum uart_baudrate bdrt) +int uart_baudrate(enum uart_type uart, enum uart_baudrate bdrt) { uint16_t div; diff --git a/src/target/firmware/calypso/uart.c b/src/target/firmware/calypso/uart.c index d3ede4d..0355ee2 100644 --- a/src/target/firmware/calypso/uart.c +++ b/src/target/firmware/calypso/uart.c @@ -112,7 +112,7 @@ enum iir_bits { #define UART_REG_UIR 0xffff6000 /* enable or disable the divisor latch for access to DLL, DLH */ -static void uart_set_lcr7bit(int uart, int on) +static void uart_set_lcr7bit(enum uart_type uart, int on) { uint8_t reg; @@ -125,7 +125,7 @@ static void uart_set_lcr7bit(int uart, int on) } static uint8_t old_lcr; -static void uart_set_lcr_bf(int uart, int on) +static void uart_set_lcr_bf(enum uart_type uart, int on) { if (on) { old_lcr = readb(UART_REG(uart, LCR)); @@ -136,7 +136,7 @@ static void uart_set_lcr_bf(int uart, int on) } /* Enable or disable the TCR_TLR latch bit in MCR[6] */ -static void uart_set_mcr6bit(int uart, int on) +static void uart_set_mcr6bit(enum uart_type uart, int on) { uint8_t mcr; /* we assume EFR[4] is always set to 1 */ @@ -148,7 +148,7 @@ static void uart_set_mcr6bit(int uart, int on) writeb(mcr, UART_REG(uart, MCR)); } -static void uart_reg_write(int uart, enum uart_reg reg, uint8_t val) +static void uart_reg_write(enum uart_type uart, enum uart_reg reg, uint8_t val) { if (reg & LCRBFBIT) uart_set_lcr_bf(uart, 1); @@ -168,7 +168,7 @@ static void uart_reg_write(int uart, enum uart_reg reg, uint8_t val) } /* read from a UART register, applying any required latch bits */ -static uint8_t uart_reg_read(int uart, enum uart_reg reg) +static uint8_t uart_reg_read(enum uart_type uart, enum uart_reg reg) { uint8_t ret; @@ -276,7 +276,7 @@ static const uint8_t uart2irq[] = { [1] = IRQ_UART_MODEM, }; -void uart_init(uint8_t uart, uint8_t interrupts) +void uart_init(enum uart_type uart, uint8_t interrupts) { uint8_t irq = uart2irq[uart]; @@ -330,7 +330,7 @@ void uart_init(uint8_t uart, uint8_t interrupts) uart_set_lcr7bit(uart, 0); } -void uart_poll(uint8_t uart) { +void uart_poll(enum uart_type uart) { if(uart == CONS_UART_NR) { uart_irq_handler_cons(0); } else { @@ -338,7 +338,7 @@ void uart_poll(uint8_t uart) { } } -void uart_irq_enable(uint8_t uart, enum uart_irq irq, int on) +void uart_irq_enable(enum uart_type uart, enum uart_irq irq, int on) { uint8_t ier = uart_reg_read(uart, IER); uint8_t mask = 0; @@ -361,7 +361,7 @@ void uart_irq_enable(uint8_t uart, enum uart_irq irq, int on) } -void uart_putchar_wait(uint8_t uart, int c) +void uart_putchar_wait(enum uart_type uart, int c) { /* wait while TX FIFO indicates full */ while (readb(UART_REG(uart, SSR)) & 0x01) { } @@ -370,7 +370,7 @@ void uart_putchar_wait(uint8_t uart, int c) writeb(c, UART_REG(uart, THR)); } -int uart_putchar_nb(uint8_t uart, int c) +int uart_putchar_nb(enum uart_type uart, int c) { /* if TX FIFO indicates full, abort */ if (readb(UART_REG(uart, SSR)) & 0x01) @@ -380,7 +380,7 @@ int uart_putchar_nb(uint8_t uart, int c) return 1; } -int uart_getchar_nb(uint8_t uart, uint8_t *ch) +int uart_getchar_nb(enum uart_type uart, uint8_t *ch) { uint8_t lsr; @@ -407,7 +407,7 @@ int uart_getchar_nb(uint8_t uart, uint8_t *ch) return 1; } -int uart_tx_busy(uint8_t uart) +int uart_tx_busy(enum uart_type uart) { if (readb(UART_REG(uart, SSR)) & 0x01) return 1; @@ -423,7 +423,7 @@ static const uint16_t divider[] = { [UART_921600] = 1, /* 812,500! (-3% would be 893,952) */ }; -int uart_baudrate(uint8_t uart, enum uart_baudrate bdrt) +int uart_baudrate(enum uart_type uart, enum uart_baudrate bdrt) { uint16_t div; diff --git a/src/target/firmware/include/comm/sercomm.h b/src/target/firmware/include/comm/sercomm.h index 54256b5..4c23b31 100644 --- a/src/target/firmware/include/comm/sercomm.h +++ b/src/target/firmware/include/comm/sercomm.h @@ -1,12 +1,8 @@ #ifndef _SERCOMM_H #define _SERCOMM_H -/* SERCOMM layer on UART1 (modem UART) */ - #include <osmocom/core/msgb.h> -#define SERCOMM_UART_NR 1 - #define HDLC_FLAG 0x7E #define HDLC_ESCAPE 0x7D diff --git a/src/target/firmware/include/console.h b/src/target/firmware/include/console.h index 7146e99..b5a83f5 100644 --- a/src/target/firmware/include/console.h +++ b/src/target/firmware/include/console.h @@ -11,9 +11,6 @@ int cons_putchar(char c); int cons_rb_flush(void); void cons_init(void); -/* We want the console on UART 0 (IRDA UART) */ -#define CONS_UART_NR 0 - /* Size of the static ring-buffer that we keep for console print messages */ #define CONS_RB_SIZE 4096 diff --git a/src/target/firmware/include/uart.h b/src/target/firmware/include/uart.h index 81d7a15..eedb006 100644 --- a/src/target/firmware/include/uart.h +++ b/src/target/firmware/include/uart.h @@ -3,6 +3,11 @@ #include <stdint.h> +enum uart_type { + CONS_UART_NR, + SERCOMM_UART_NR, +}; + enum uart_baudrate { UART_38400, UART_57600, @@ -13,20 +18,20 @@ enum uart_baudrate { UART_921600, }; -void uart_init(uint8_t uart, uint8_t interrupts); -void uart_putchar_wait(uint8_t uart, int c); -int uart_putchar_nb(uint8_t uart, int c); -int uart_getchar_nb(uint8_t uart, uint8_t *ch); -int uart_tx_busy(uint8_t uart); -int uart_baudrate(uint8_t uart, enum uart_baudrate bdrt); +void uart_init(enum uart_type uart, uint8_t interrupts); +void uart_putchar_wait(enum uart_type uart, int c); +int uart_putchar_nb(enum uart_type uart, int c); +int uart_getchar_nb(enum uart_type uart, uint8_t *ch); +int uart_tx_busy(enum uart_type uart); +int uart_baudrate(enum uart_type uart, enum uart_baudrate bdrt); enum uart_irq { UART_IRQ_TX_EMPTY, UART_IRQ_RX_CHAR, }; -void uart_irq_enable(uint8_t uart, enum uart_irq irq, int on); +void uart_irq_enable(enum uart_type uart, enum uart_irq irq, int on); -void uart_poll(uint8_t uart); +void uart_poll(enum uart_type uart); #endif /* _UART_H */ -- 1.7.2.5

5 9

hi all
by 麦田守望 17 May '11

17 May '11

do you know the mtk chip MT6217 it is usb interface chip we can use to make a GSM network the mt6217 with pc

1 0

Re: Power management
by Dieter Spaar 17 May '11

17 May '11

Hello Stefan, On Tue, 17 May 2011 00:09:13 +0200, "l--putt" <ichgeh(a)l--putt.de> wrote: > > Saving power > Having everything on and at maximum clock drains the battery _fast_! > With the ULPD, we actually have the appropriate solution build into the > Calypso. I guess other chipsets have something similar. > It is neat to get the timing and power sequence right. But since the > TDMA timing is affected, Layer 1 must be aware of those clock/power > changes or at least tolerate to be turned on and off. Does anybody right > away have ideas how to approach this? A few notes, I don't remember the details: The basic idea is to only receive in idle mode when its necessary. This means listening only for the paging group of the IMSI and doing the neighbour cell measurements. During the other time the processor can be stopped. There are different levels to which extend the clock is stopped, for saving the most power only the 32 kHz crystal remains active. However this requires some calibration, otherwise the TDMA frames could be missed after sleeping. Most of this calibration can be done with the help of the hardware, its always done before switching to 32 kHz. Best regards, Dieter -- Dieter Spaar, Germany spaar(a)mirider.augusta.de

1 0

Power management
by l--putt 16 May '11

16 May '11

Hi list! Some time ago Harald suggested to create a complete phone, at least with minimal features. Since this hasn't been covered yet and we will have to rewrite some parts during RTOS porting anyway, I think we should consider some kind of power management: Saving power Having everything on and at maximum clock drains the battery _fast_! With the ULPD, we actually have the appropriate solution build into the Calypso. I guess other chipsets have something similar. It is neat to get the timing and power sequence right. But since the TDMA timing is affected, Layer 1 must be aware of those clock/power changes or at least tolerate to be turned on and off. Does anybody right away have ideas how to approach this? Charger The C155 has a dedicated chip which you probably just have to turn on. On the C123, it's a bit more complex but the algorithms don't seem to be too complex. Has anybody tried this already? State-of-Charge For the usual concepts on batteryuniversity.com, a random book from the university lib, and some papers, we would need some means to measure the discharge current. No Compal phone provides this since the voltage regulators are connected directly to the battery. The gta02 avoids this with a dedicated Coulomb-counting chip. The gta01 doesn't care!? Maybe the battery voltage and temperature is sufficient for reasonably correct estimates. If not, we could try to model the current. However, this requires some kind of central power management that knows activated devices, their clocks, etc. I would volunteer for the latter and C155-charging. However, I lack a C123 for tests and don't want to be responsible for exploding phones ;) Integration of the ULPD is a bit more GSM-related. Might turn out to be interesting... Cheers, Stefan

1 0

linking error on board mt62xx (current git tree)
by Pablo Neira Ayuso 16 May '11

16 May '11

Hi Wolfram, I hit the following linking error in the current LD board/mt62xx/loader_mtk.mtkram.elf arm-elf-ld: address 0x400050ec of board/mt62xx/loader_mtk.mtkram.elf section .text is not within region LRAM make[1]: *** [board/mt62xx/loader_mtk.mtkram.elf] Error 1 I'm not familiar with those bits, any clue on what's wrong? Thanks.

6 7

MacOSX build
by Klaus Rechert 16 May '11

16 May '11

Hi, some quick notes on the MacOSX build. Current git builds fine using the perbuilt GNUARM MacOS toolchain except that GCC 3.3 does not support the option -Wextra. There are also some issues building mtk firmware but this seems to be a more general issue. Cheers Klaus diff --git a/src/target/firmware/Makefile.inc b/src/target/firmware/Makefile.inc index 1f54031..c8f4323 100644 --- a/src/target/firmware/Makefile.inc +++ b/src/target/firmware/Makefile.inc @@ -12,7 +12,7 @@ OBJCOPY=objcopy DEBUGF=dwarf-2 CFLAGS=-mcpu=arm7tdmi $(INCLUDES) -CFLAGS += -Wall -Wextra -Wcast-align -Wimplicit -Wunused +CFLAGS += -Wall -Wcast-align -Wimplicit -Wunused CFLAGS += -Wswitch -Wredundant-decls -Wreturn-type -Wshadow -Wnested-externs CFLAGS += -Wbad-function-cast -Wsign-compare -Waggregate-return CFLAGS += -Os -ffunction-sections

1 1

Osmocom building in Ubuntu Error
by Sun Ich 16 May '11

16 May '11

Hi I try to compile osmocom in Ubuntu, I have gcc 4.4.3 and I installed binutils 2.20 for ARM successfully and I have arm-elf-* binaries in PATH directory when I run make in src folder of osmocom, I get error: unknown instruction "ror xor" something something.... What's problem, do I missing something? Thanks

1 0

Fwd: Fwd: RFC: RTOS for Calypso
by Alan Carvalho de Assis 16 May '11

16 May '11

FYI ---------- Forwarded message ---------- From: Gregory Nutt <spudarnia(a)yahoo.com> Date: Sun, 15 May 2011 07:52:18 -0700 (PDT) Subject: Re: Fwd: RFC: RTOS for Calypso To: Alan Carvalho de Assis <acassis(a)gmail.com> Hi Alan, I also notice that they are using a TI dual core, ARM7TDMI and C5 DSP. I already have support for a TI chip like that (the C5471) and also for an ARM9 with C5 DSP (DM320). See http://focus.ti.com.cn/cn/lit/ml/sprt239/sprt239.pdf I have a c5 DSP bridge driver somewhere around on my backup disks as well. I never released it into NuttX because there was never any need. Perhaps that could be useful now. Somewhere I also have tools that will convert the TI proprietary object files and logic to manage loading different programs into the DSP. The bridge also supports communication channels to communicate with the DSP. Greg

1 0