Hi All,
I ported UmTRX project to the new UmTRX v2 board. Now you can compile FPGA project for UmTRX v2 board with "make UmTRXv2" command from fairwaves/umtrx branch. Now, my next goal is to get a working second transmission channel in fpga project.
Regards, Andrew Karpenkov
Hi Andrew,
How is the dual-channel work going?
On Thu, Oct 4, 2012 at 11:46 AM, Andrew Karpenkov plddesigner@gmail.com wrote:
Hi All,
I ported UmTRX project to the new UmTRX v2 board. Now you can compile FPGA project for UmTRX v2 board with "make UmTRXv2" command from fairwaves/umtrx branch. Now, my next goal is to get a working second transmission channel in fpga project.
Regards, Andrew Karpenkov
Utilities from UHD are working properly. However, the OpenBTS crashes at startup. Now step by step I connect each block and try to find what causes instability.
Regards, Andrew Karpenkov
2012/10/14 Alexander Chemeris alexander.chemeris@gmail.com
How is the dual-channel work going?
What do you mean by connecting blocks? I thought it's the problem with registers of the DSP block in FPGA.
On Sun, Oct 14, 2012 at 11:13 PM, Andrew Karpenkov plddesigner@gmail.com wrote:
Utilities from UHD are working properly. However, the OpenBTS crashes at startup. Now step by step I connect each block and try to find what causes instability.
Regards, Andrew Karpenkov
2012/10/14 Alexander Chemeris alexander.chemeris@gmail.com
How is the dual-channel work going?
The problem is not in the registers, but the fact that the second unit does not give the first unit to work, or vice versa. Somewhere I made a mistake. I think so ..
Regards, Andrew Karpenkov
2012/10/14 Alexander Chemeris alexander.chemeris@gmail.com
I thought it's the problem with registers of the DSP block in FPGA.
What is your expectation - how much time do you need to debug this?
On Sun, Oct 14, 2012 at 11:22 PM, Andrew Karpenkov plddesigner@gmail.com wrote:
The problem is not in the registers, but the fact that the second unit does not give the first unit to work, or vice versa. Somewhere I made a mistake. I think so ..
Regards, Andrew Karpenkov
2012/10/14 Alexander Chemeris alexander.chemeris@gmail.com
I thought it's the problem with registers of the DSP block in FPGA.
I suppose that I need one week for this job (from 17.10-24.10).
Sent from my Android device.
Regards, Andrew Karpenkov 14.10.2012 23:42 пользователь "Alexander Chemeris" < alexander.chemeris@gmail.com> написал:
What is your expectation - how much time do you need to debug this?
On Sun, Oct 14, 2012 at 11:22 PM, Andrew Karpenkov plddesigner@gmail.com wrote:
The problem is not in the registers, but the fact that the second unit
does
not give the first unit to work, or vice versa. Somewhere I made a mistake. I think so ..
Regards, Andrew Karpenkov
2012/10/14 Alexander Chemeris alexander.chemeris@gmail.com
I thought it's the problem with registers of the DSP block in FPGA.
-- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ООО УмРадио http://fairwaves.ru
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Alexander Chemeris -
Andrew Karpenkov