14 Oct
2012
14 Oct
'12
3:41 p.m.
What is your expectation - how much time do you need to debug this?
On Sun, Oct 14, 2012 at 11:22 PM, Andrew Karpenkov
<plddesigner(a)gmail.com> wrote:
The problem is not in the registers, but the fact that
the second unit does
not give the first unit to work, or vice versa.
Somewhere I made a mistake. I think so ..
Regards,
Andrew Karpenkov
2012/10/14 Alexander Chemeris <alexander.chemeris(a)gmail.com>
--
Regards,
Alexander Chemeris.
CEO, Fairwaves LLC / ООО УмРадио
http://fairwaves.ru
I thought it's the problem with
registers of the DSP block in FPGA.