UmTRX

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189 discussions

DC Offset vs temperature
by Alexander Chemeris 29 Jul '12

29 Jul '12

Hi all, Thomas has discovered that DC offset calibration for LMS is drifting a lot with temperature changes and this has detrimental effect on the modulation accuracy: http://code.google.com/p/umtrx/issues/detail?id=31 One solution proposed by Sylvain is to tune modulation a bit higher using digital modulation, which should be straightforward with UHD which has digital mixer in FPGA. But I wonder what is a recommended solution for this temperature compensation for LMS in general. Srdjan, could you comment on this? -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ООО УмРадио http://fairwaves.ru

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Plan for 10/100 Ethernet support for umTRX
by Robin Coxe 28 Jul '12

28 Jul '12

The Ettus UHD framework adopted for the umTRX only supports GigE (simple_gemac). A reworked, Wishbone-compliant 10/100 Ethernet MAC is included in the OpenRISC SoC project on Opencores. It has been ported to the Digilent Atlys board, which has a Spartan-6 FPGA. http://www.chokladfabriken.org/projects/orpsoc-atlys I'll begin the port of this Ethernet MAC (a cleaned-up version of the 10/100 core on OpenCores) to the UmTRX and test it on Close-Haul's SP-605 Spartan-6 eval. board. I'm not quite sure how long this task will take, but this feature falls into the "nice-to-have-but-not-urgent" category. -Robin -- Robin Coxe | Close-Haul Communications, Inc. | Boston, MA +1-617-470-8825

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Improving LMS6002 phase noise
by Srdjan Milenkovic 24 Jul '12

24 Jul '12

Hi all, As far as I am aware, you are currently discussing how to improve LMS6002 PLL phase noise. Below are some inputs from my side which may help. Apart from playing with PLL registers we have two additional options. 1. Use clean TCXCO which provides 4 times higher reference followed by divide by 4 to generate PLL reference clock. Recently, we experimented with 30.72*4 MHz TCXCO. Dividing its output by 4 before going into LMS chip we have got improvement of 6dB in phase noise plateau region. 2. Current PLL loop filter has been designed to cover the whole LMS frequency range hence using kind of mid value for Kvco. We can customize the loop filter for a particular band. To do that we need to know frequency range China Mobile is looking for and reference clock you want to use (26MHz, 26*4/4MHz, ...). Please note that PLL reference clock does not need to be the same as system clock i.e. we can also use 30.72MHz, 30.72*4/4MHz etc. Best regards, Srdjan

5 12

OpenBTS with UmTRX
by Thomas Tsou 24 Jul '12

24 Jul '12

Google project hosting is currently read only for network maintenance. Here are general OpenBTS / UmTRX setup instructions. I'll post them when write access is restored. Download ======= UHD git://github.com/chemeris/UHD-Fairwaves.git fairwaves/umtrx-dboard OpenBTS git://github.com/ttsou/openbts-p2.8 umtrx Follow standard build instructions. http://files.ettus.com/uhd_docs/manual/html/build.html http://wush.net/trac/rangepublic/wiki/BuildInstallRun UmTRX Setup =========== Configuration of the LMS6003D is through the control script 'umtrx_lms.py', which is installed in '/usr/local/share/uhd/utils'. Calibration prior to operation is strongly recommended. Example setup for ARFCN 925: Initialization and auto-calibration: ./umtrx_lms.py --lms 1 --lms-init ./umtrx_lms.py --lms 1 --lms-tx-enable 1 ./umtrx_lms.py --lms 1 --lms-rx-enable 1 ./umtrx_lms.py --lms 1 --pll-ref-clock 26e6 --lpf-bandwidth-code 0x0f --lms-auto-calibration RX LNA and RXVGA2 selection and gain control ./umtrx_lms.py --lms 1 --reg 0x75 --data 0xf0 ./umtrx_lms.py --lms 1 --reg 0x65 --data 10 TX LPF control ./umtrx_lms.py --lms 1 --reg 0x34 --data 0x3e LO leakage cancellation (calibration data values may vary) ./umtrx_lms.py --lms 1 --reg 0x42 --data 0x67 ./umtrx_lms.py --lms 1 --reg 0x43 --data 0x89 TX/RX PLL charge pump current ./umtrx_lms.py --lms 1 --reg 0x16 --data 0x93 Tuning ./umtrx_lms.py --lms 1 --lms-rx-pll-tune 925.2e6 ./umtrx_lms.py --lms 1 --lms-tx-pll-tune 880.2e6 TXVGA2 gain to max and enable PA ./umtrx_lms.py --lms 1 --reg 0x45 --data 0xc8 ./umtrx_lms.py --lms 1 --lms-pa-on 2 Running OpenBTS ============== Follow standard instructions. http://wush.net/trac/rangepublic/wiki/BuildInstallRun Thomas

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Running OpenBTS with UmTRX
by Alexander Chemeris 22 Jul '12

22 Jul '12

Hi Thomas, Could you hack together a quick guide how to run OpenBTS with UmTRX at the wiki? http://code.google.com/p/umtrx/wiki/RunningOpenBTS This should basically include which branch to use, what patches to apply (if any), and a script for umtrx_lms.py to tune LMS to the correct frequency. I was meaning to write this for about a week, but turns out it's very hard to allocate enough time to do that accurately. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ООО УмРадио http://fairwaves.ru

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Testing reception
by Alexander Chemeris 22 Jul '12

22 Jul '12

Andrey Sviyazov, You wanted to know how to plot received signal under Windows without installing Matlab or something as big and as expensive. Dmitri Stolnikov recommended to use a free version of Signals Analyzer software which should be very powerful. You could download it as "SA free" here: http://signals.radioscanner.ru/info/item1/ Dmitri says that the free version of SA could only import .wav files, so you will need to convert raw files into .wav files. My preferred way to do this is to use 'sox' command line utility like that: sox -r 270833 -e signed -b 16 -c 2 record.cfile record.wav Windows binaries of 'sox' is available from the official web-site: http://sox.sourceforge.net/ -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ООО УмРадио http://fairwaves.ru

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UmTRX dual-channel Rx
by Andrey Sviyazov 21 Jul '12

21 Jul '12

Hi all. I found that both Rx divercity switches have zero state for A and B control inputs. Thus both LNA and LNA-D connectors are not switched to Rx inputs of the LMS's. To proceed Rx testing I suggest to set the next fixed states in the FPGA: DIVSW1_P = 1, DIVSW1_N = 0, DIVSW2_P = 1, DIVSW2_N = 0. In this case LMS1 will be switched to LNA connector, but LMS2 to LNA-D. Andrew Karpenkov, would you please to make this kind changes, until DIVSW will controled by host? Best regards, Andrey Sviyazov.

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Attachment size
by Alexander Chemeris 21 Jul '12

21 Jul '12

Hi all, I've set maximum message size for this mailing list to 1Mb. This means that you can't send big files or images to this mailing list. If you need to do so - upload files to some external server and provide a link. Project members could use our project hosting, others could upload to some other public services. At the same time limitation of 1Mb should be big enough to allow you to post screenshots of your measurements, schematics pictures, etc. Please make sure that you send big files as an attachments, even if they are textual. Subscribers (myself included) sometimes work from GPRS/EDGE connections and downloading huge e-mails is a true pain. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ООО УмРадио http://fairwaves.ru

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Re: Dual-channel Tx
by Andrew Karpenkov 17 Jul '12

17 Jul '12

Hi All, I added one more RX and TX units and connected them to the second LMS chip. You can find fpga sources with full supply (both, receive and transmit) of dual channel at akarpenkov/dual-channel branch of github repository. Also, we need to make some changes in HOST code: - SR_RX_FRONT0 (base adress of RX0 frontend) was changed from 24 to 20 (dec) - SR_RX_FRONT1 (base adress of RX1 frontend) was added with value = 25 (dec) - SR_TX_FRONT (base adress of TX0 frontend) was changed from 128 to 110 (dec) - SR_TX_CTRL (base adress of control logic of TX0 channel) was changed from 144 to 126 (dec) - SR_TX_DSP (base adress of DSP TX0 unit) was changed from 160 to 135 (dec) - SR_TX1_FRONT (base adress of TX1 frontend) was added with value = 145 (dec) - SR_TX1_CTRL (base adress of control logic of TX1 channel) was added with value = 161 (dec) - SR_TX1_DSP (base adress of TX1 channel) was added with value = 170 (dec) - Setting register to program the UDP TX DSP port (16 + 1 in dec) are now 32 bit wide (udp dst0 port - lower 16 bits, udp dst1 port - higher 16 bits). I sent flash for FPGA to Alexander and he must publish files on the site soon. I should say, I have not tested work of the project. Please report any issues. Regards , Andrew Karpenkov

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LMS6002D documentation
by Alexander Chemeris 17 Jul '12

17 Jul '12

Hi all, I've pushed more public documentation for LMS6002D to the repository: https://github.com/chemeris/lms6002-documentation FAQ should be very interesting for everyone - recommended reading. -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ООО УмРадио http://fairwaves.ru

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