Hi,

I checked out the git found the GPS 1pps signal was terminated to FPGA, and wonder how the discipline algorithm was implemented. Someone would give me a hint or introductory?

Simple PID control. Look at the ZPU firmware (soft cpu core inside the FPGA).

We don't need a "time-nut" level of accuracy here so this simple control works well. Could be improved to handle corner cases though.

Cheers,

Sylvain