Re: umtrx fpga internal clocking

I see. I just got lost in the ifdefs. Those are the changes I was looking for. I see, the input clock is 26 MHz, ok makes sense. Thanks! So let me propose one more idea for thought. To avoid clock domain crossing completely: We can use the existing usrp2 style design at 26 MHz. The rx/tx DSP, and vita framer/deframer all run at 26 MHz. The only change needed is to pace the DSPs. For example, the rx input is only good every other 26 MHz cycle, so add an input strobe to the RX DSP. Similarly the TX DSP would have its input paced to take data every other cycle. That way the 32-bit vita framers will have 2x clock cycles to do the framing/deframing even when the DSP is running at full rate. 104MHz fifo bus in -> cross clock fifo to 26 MHz -> vita tx deframer -> paced tx dsp -> out to dac in from adc -> paced rx dsp -> vita rx deframer -> cross clock fifo to 104 MHz -> 104 MHz fifo bus out Just a thought, -josh