Something like the attached Taiten VCTCXO @ 30.72 MHz + ADF4002 Phase Detector/PLL synthesizer might work. I have no idea how much the oscillator costs. (The Pletronics oscillator on the UmTRX and the GAPfiller GSM900 isn't available at this frequency.)
http://www.analog.com/en/rfif-components/pll-synthesizersvcos/adf4002/produc...http://www.analog.com/en/rfif-components/pll-synthesizersvcos/adf4002/products/product.html#product-designtools-nav
-Robin
On Sat, Oct 13, 2012 at 11:54 PM, Alexander Chemeris < alexander.chemeris@gmail.com> wrote:
John,
On Sun, Oct 14, 2012 at 12:24 AM, John Orlando john@epiqsolutions.com wrote:
On Sat, Oct 13, 2012 at 4:30 PM, Alexander Chemeris alexander.chemeris@gmail.com wrote:
Hi John,
On Sat, Oct 13, 2012 at 11:11 PM, John Orlando john@epiqsolutions.com
wrote:
On Sat, Oct 13, 2012 at 3:47 PM, Alexander Chemeris alexander.chemeris@gmail.com wrote:
Hi Srdjan,
We're looking into re-purposing UmTRX for LTE and there a few things
which
we need to understand better.
- Is it possible to support 15MHz and 20MHz LTE channel bandwidths?
To
achieve this we at least need to sample at 23.04Msps and 30.72Msps respectively. LMS6002D datasheet specifies the maximum I/Q samplerate
of
14Msps, which is not enough. But at the same time, datasheet claims
that ADC
and DAC are specified up to 50Msps. How does this fits together?
Alexander, Can you provide a reference to where the datasheet calls out a max I/Q sample rate of 14 Msps? The analog low pass filters support a max bandwidth of 14 MHz (which leads to 28 MHz RF bandwidth assuming zero-IF operation)...is this what you're referencing?
The datasheet is not very clear on this topic. I'm referring to the following line at the Table 1: Baseband Bandwidth 14MHz
Originally I read this line as "digital I/Q bus has limitation of 14Msps" and this is what confuses me.
Yes, this refers to the analog baseband filter bandwidth.
Ok, thanks for the clarification.
We run the A/D converters in the LMS6002d at sample rates greater than 14 Msps all the time, including 30.72 Msps.
Just to be sure - do you mean you feed RX_CLK and TX_CLK of LMS6002D with 61.44MHz clock? It's divided by 2 internally, so if you feed them with 30.72MHz clock you actually get only 15.36Msps out of LMS6002D.
Correct, when running the A/D at 30.72 Msps, the RX_CLK signal needs to run at 61.44 MHz.
Great! In case you know a good 61.44 MHz oscillator with a reasonable price - I would appreciate a pointer.
-- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ООО УмРадио http://fairwaves.ru