Thomas,
Do you have an idea why we get this messages when running OpenBTS?
Also we configured OpenBTS to output all received bursts to a screen
and it looks like it starts receiving a lot of noise. Then this noise
almost stops and shows only sometimes.
$ tail -f syslog
Sep 6 19:13:16 kluchnikov transceiver:
ERR 3043572592 UHDDevice.cpp:785:recv_async_msg: An internal send buffer
has emptied at 826.035 sec.
Sep 6 19:13:16 kluchnikov transceiver:
ERR 3043572592 UHDDevice.cpp:785:recv_async_msg: Packet time was too late
or too early at 826.037 sec.
Sep 6 19:13:47 kluchnikov transceiver:
ERR 3043572592 UHDDevice.cpp:785:recv_async_msg: An internal send buffer
has emptied at 856.255 sec.
Sep 6 19:13:47 kluchnikov transceiver:
ERR 3043572592 UHDDevice.cpp:785:recv_async_msg: Packet time was too late
or too early at 856.257 sec.
Sep 6 19:13:47 kluchnikov transceiver:
ERR 3043572592 UHDDevice.cpp:785:recv_async_msg: Packet time was too late
or too early at 856.257 sec.
Sep 6 19:14:04 kluchnikov transceiver:
ERR 3043572592 UHDDevice.cpp:785:recv_async_msg: An internal send buffer
has emptied at 874.005 sec.
Sep 6 19:14:04 kluchnikov transceiver:
ERR 3043572592 UHDDevice.cpp:785:recv_async_msg: Packet time was too late
or too early at 874.009 sec.
Sep 6 19:14:04 kluchnikov transceiver:
ERR 3043572592 UHDDevice.cpp:785:recv_async_msg: Packet time was too late
or too early at 874.009 sec.
Sep 6 19:14:07 kluchnikov transceiver:
ERR 3043572592 UHDDevice.cpp:785:recv_async_msg: An internal send buffer
has emptied at 877.01 sec.
Sep 6 19:14:07 kluchnikov transceiver:
ERR 3043572592 UHDDevice.cpp:785:recv_async_msg: Packet time was too late
or too early at 877.013 sec.
Sep 6 19:14:07 kluchnikov transceiver:
ERR 3043572592 UHDDevice.cpp:785:recv_async_msg: Packet time was too late
or too early at 877.013 sec.
Sep 6 19:14:09 kluchnikov transceiver:
ERR 3043572592 UHDDevice.cpp:785:recv_async_msg: An internal send buffer
has emptied at 878.466 sec.
Sep 6 19:14:09 kluchnikov transceiver: ERR 3043572592
UHDDevice.cpp:785:recv_async_msg: Packet time was too late or too early at
878.468 sec.
--
Regards,
Alexander Chemeris.
CEO, Fairwaves LLC / ООО УмРадио
http://fairwaves.ru
Hi All,
I added control logic of LMS reset pins into ZPU firmware (commit
25a89e337b98f89d542a8bd51a3bfb6dc2a9f441
<https://github.com/chemeris/UHD-Fairwaves/commit/25a89e337b98f89d542a8bd51a…>at
the akarpenkov/dual-channel branch).
I need to take control under Diversity switches and LMS reset pins from
host. As I understand, python script "umtrx_ctrl.py" is not able write FPGA
registers, it's can talk only with SPI devices.
Max, Sylvain or anyone else, can you help me get access to FPGA registers
(they connected to wishbone bus) from host? I'm not very good at
programming on python..
UHD can do this (example here: host\lib\usrp\usrp2\usrp2_impl.cpp:530).
Also I added second RX and TX channels to the FPGA firmware and according
with that changed memory maps in ZPU and HOST firmwares (all changes at
the akarpenkov/dual-channel branch on github).
Work of TX and RX DSP 2 units I can't check due to complete lack of support
in the HOST software. Could anyone make needed changes at HOST firmware?
Regards,
Andrew Karpenkov
