Deployed GMR-1 devices typically run the A5 algorithm family in a dedicated cipher peripheral rather than in software. Record the observed register layout in the public Doxygen block so users reading captures or building capture-side analysis tools have a reference.
Register layout (16-bit words at fixed offsets from a per-device base address):
+0x00 .. +0x06 : four 16-bit parameter words (key / IV material) +0x08 : 16-bit selector / frame word +0x0a : 16-bit auxiliary parameter +0x0c : 16-bit mode / control word with bit fields: 0x0001 : start 0x0002 : direction (1 = decipher, 0 = encipher) 0x0004 / 0x0008 : algorithm-family selector (mutually exclusive bases)
The peripheral typically exposes at least one additional algorithm-family slot beyond A5-GMR-1, consistent with a shared multi-cipher accelerator. The software reimplementation in this module is the reference for off-line SDR / capture analysis; it is unrelated to any specific hardware implementation.
Purely cosmetic, no behavioral change.
Signed-off-by: Dominik Bay eimann@etherkiller.de --- include/osmocom/gmr1/l1/a5.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+)
diff --git a/include/osmocom/gmr1/l1/a5.h b/include/osmocom/gmr1/l1/a5.h index d15efd5..d3fe3a7 100644 --- a/include/osmocom/gmr1/l1/a5.h +++ b/include/osmocom/gmr1/l1/a5.h @@ -45,6 +45,27 @@ * enables cross-validation of gmr1_a5_1() against an * independently-sourced TEA1 implementation. * + * \par Typical hardware implementations + * Deployed GMR-1 devices typically run the A5 algorithm family in a + * dedicated cipher peripheral rather than in software. The observed + * register layout is a 16-bit window at a per-device base address: + * \verbatim + * +0x00 .. +0x06 : four 16-bit parameter words (key / IV material) + * +0x08 : 16-bit selector / frame word + * +0x0a : 16-bit auxiliary parameter + * +0x0c : 16-bit mode / control word, bit fields: + * 0x0001 : start + * 0x0002 : direction (1 = decipher, 0 = encipher) + * 0x0004 / 0x0008 : algorithm-family selector + * (mutually exclusive bases) + * \endverbatim + * The peripheral typically exposes at least one additional + * algorithm-family slot beyond A5-GMR-1, consistent with a shared + * multi-cipher accelerator. The software reimplementation in this + * module is the reference for off-line SDR / capture analysis and + * for generating test vectors; it is unrelated to any specific + * hardware implementation. + * * @{ */