fixeria has posted comments on this change by fixeria. ( https://gerrit.osmocom.org/c/osmocom-bb/+/41906?usp=email )
Change subject: trxcon/fsm: handle_dch_est_req(): do not reset the scheduler
......................................................................
Patch Set 2: Code-Review+2
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fixeria has submitted this change. ( https://gerrit.osmocom.org/c/osmo-ttcn3-hacks/+/41898?usp=email )
Change subject: bts: TC_rsl_chan_initial_ta: misc improvements
......................................................................
bts: TC_rsl_chan_initial_ta: misc improvements
Change-Id: Ifc2c850104b3710679485042ab5b7a758d0ae000
Related: OS#6919
---
M bts/BTS_Tests.ttcn
1 file changed, 7 insertions(+), 9 deletions(-)
Approvals:
osmith: Looks good to me, but someone else must approve
pespin: Looks good to me, but someone else must approve
Jenkins Builder: Verified
fixeria: Looks good to me, approved
diff --git a/bts/BTS_Tests.ttcn b/bts/BTS_Tests.ttcn
index b060cbd..a4f7ba2 100644
--- a/bts/BTS_Tests.ttcn
+++ b/bts/BTS_Tests.ttcn
@@ -3899,7 +3899,7 @@
/* establish DChan, verify that the BTS sets the TA in the first SACCH L1 header.
TA for the IMM ASS messages is still controlled by g_pars.l1_pars.ms_actual_ta! */
private function f_tc_rsl_chan_initial_ta(charstring id) runs on ConnHdlr {
- var uint5_t ta_to_test := 16;
+ const uint5_t ta_to_test := 16;
var SacchL1Header l1h;
f_l1_tune(L1CTL);
@@ -3910,18 +3910,16 @@
f_est_dchan(more_ies :={valueof(t_RSL_IE(RSL_IE_TIMING_ADVANCE, RSL_IE_Body:{timing_adv := ta_to_test}))} );
-
+ /* wait for a single DL SACCH block */
alt {
- [] as_l1_sacch_l1h(l1h, do_apply := false) {
- if (l1h.actual_ta != ta_to_test) {
- setverdict(fail, "TA in L1 header does not match the signaled (RSL) TA.");
- }
-
- }
-
+ [] as_l1_sacch_l1h(l1h, do_apply := false);
/* Ignore all other blocks */
[] L1CTL.receive { repeat; }
+ }
+ if (l1h.actual_ta != ta_to_test) {
+ setverdict(fail, "TA=", l1h.actual_ta, " in the DL SACCH does not match ",
+ "the signaled (RSL) TA=", ta_to_test);
}
f_rsl_chan_deact();
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fixeria has submitted this change. ( https://gerrit.osmocom.org/c/osmo-ttcn3-hacks/+/41899?usp=email )
Change subject: bts: TC_rsl_chan_initial_ta: fix sporadic failures
......................................................................
bts: TC_rsl_chan_initial_ta: fix sporadic failures
It may happen that an UL SACCH block is received by the BTS before a DL
SACCH block is generated and delivered to the testcase. In this case,
the Timing Advance control loop may update the initial TA value that
was set during RSL CHANnel ACTIVation.
By default, trxcon transmits UL SACCH blocks with TA=0, which is exactly
what triggers the TA control loop in this situation.
To avoid this, we explicitly signal the expected TA value to trxcon by
pre-populating the UL SACCH cache. This is done by sending a DATA.req
containing a measurement report in advance, before establishing DCCH,
so that subsequent UL SACCH blocks carry the correct TA and do not
activate the control loop.
Additionally, take the opportunity to add missing f_L1CTL_PARAM().
This compensates for the artificial delay introduced by
f_trxc_fake_toffs256(), further reducing the risk of triggering
the TA control loop.
Change-Id: Iebb043ccc710750dff937e2281c23d343b85bda1
Related: OS#6919
---
M bts/BTS_Tests.ttcn
1 file changed, 7 insertions(+), 0 deletions(-)
Approvals:
fixeria: Looks good to me, approved
osmith: Looks good to me, but someone else must approve
pespin: Looks good to me, but someone else must approve
Jenkins Builder: Verified
diff --git a/bts/BTS_Tests.ttcn b/bts/BTS_Tests.ttcn
index a4f7ba2..6277cf3 100644
--- a/bts/BTS_Tests.ttcn
+++ b/bts/BTS_Tests.ttcn
@@ -3907,6 +3907,13 @@
/* tell fake_trx to use a given timing offset for all bursts */
f_trxc_fake_toffs256(ta_to_test*256);
+ /* tell trxcon to use a given TA for UL bursts */
+ g_pars.l1_pars.ms_actual_ta := ta_to_test;
+ f_L1CTL_PARAM(L1CTL, g_pars.l1_pars.ms_actual_ta,
+ g_pars.l1_pars.ms_power_level);
+ /* tell trxcon to use a given TA in UL SACCH blocks
+ * this is achieved by populating UL SACCH cache before doing f_l1ctl_est_dchan() */
+ f_send_meas_rep(ts_MeasurementResults);
f_est_dchan(more_ies :={valueof(t_RSL_IE(RSL_IE_TIMING_ADVANCE, RSL_IE_Body:{timing_adv := ta_to_test}))} );
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Attention is currently required from: pespin.
fixeria has posted comments on this change by fixeria. ( https://gerrit.osmocom.org/c/osmo-ttcn3-hacks/+/41897?usp=email )
Change subject: bts: use existing API in as_l1_sacch_loop()
......................................................................
Patch Set 2:
(1 comment)
File bts/BTS_Tests.ttcn:
https://gerrit.osmocom.org/c/osmo-ttcn3-hacks/+/41897/comment/cc4de594_17a2… :
PS2, Line 2172: private altstep as_l1_sacch_loop(boolean do_apply := false) runs on ConnHdlr {
> Isn't it a bit confusing that as_l1_sacch_l1h() has do_apply := true and this one has do_apply := fa […]
I had to change it to `false` because `true` breaks a bunch of testcases, basically all `BTS_Tests.TC_meas_res_*` (and probably more). Prior to this patch, `as_l1_sacch_loop()` did not apply the received TA/PWR values, so `false` keeps the existing behavior unchanged.
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Attention is currently required from: dexter.
laforge has posted comments on this change by dexter. ( https://gerrit.osmocom.org/c/pysim/+/41874?usp=email )
Change subject: esim/http_json_api: extend JSON API with server functionality
......................................................................
Patch Set 3: Code-Review+1
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