fixeria has uploaded this change for review. ( https://gerrit.osmocom.org/c/osmocom-bb/+/41906?usp=email )
Change subject: trxcon/fsm: handle_dch_est_req(): do not reset the scheduler
......................................................................
trxcon/fsm: handle_dch_est_req(): do not reset the scheduler
Calling l1sched_reset() results in resetting the UL SACCH cache,
that may have been populated prior to sending L1CTL_DM_EST_REQ.
Instead, do what the comment says - call l1sched_del_all_ts().
Change-Id: Iff03fa5b90ac1ec30b7937cea6bd09c6ececb5f6
Fixes: c6fe9c3f ("trxcon: trxcon_fsm: permit loop [P]DCH transitions")
Related: 15877ba05 ("trxcon: allow populating global SACCH cache via L1CTL")
Related: OS#6919
---
M src/host/trxcon/src/trxcon_fsm.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://gerrit.osmocom.org:29418/osmocom-bb refs/changes/06/41906/1
diff --git a/src/host/trxcon/src/trxcon_fsm.c b/src/host/trxcon/src/trxcon_fsm.c
index 34ca21b..fa0584d 100644
--- a/src/host/trxcon/src/trxcon_fsm.c
+++ b/src/host/trxcon/src/trxcon_fsm.c
@@ -352,7 +352,7 @@
}
/* Remove all active timeslots */
- l1sched_reset(trxcon->sched);
+ l1sched_del_all_ts(trxcon->sched);
rc = l1sched_configure_ts(trxcon->sched, req->chan_nr & 0x07, config);
if (rc)
--
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Gerrit-Change-Id: Iff03fa5b90ac1ec30b7937cea6bd09c6ececb5f6
Gerrit-Change-Number: 41906
Gerrit-PatchSet: 1
Gerrit-Owner: fixeria <vyanitskiy(a)sysmocom.de>
fixeria has uploaded this change for review. ( https://gerrit.osmocom.org/c/osmo-ttcn3-hacks/+/41899?usp=email )
Change subject: bts: TC_rsl_chan_initial_ta: fix sporadic failures
......................................................................
bts: TC_rsl_chan_initial_ta: fix sporadic failures
It may happen that an UL SACCH block is received by the BTS before a DL
SACCH block is generated and delivered to the testcase. In this case,
the Timing Advance control loop may update the initial TA value that
was set during RSL CHANnel ACTIVation.
By default, trxcon transmits UL SACCH blocks with TA=0, which is exactly
what triggers the TA control loop in this situation.
To avoid this, we explicitly signal the expected TA value to trxcon by
pre-populating the UL SACCH cache. This is done by sending a DATA.req
containing a measurement report in advance, before establishing DCCH,
so that subsequent UL SACCH blocks carry the correct TA and do not
activate the control loop.
Additionally, take the opportunity to add missing f_L1CTL_PARAM().
This compensates for the artificial delay introduced by
f_trxc_fake_toffs256(), further reducing the risk of triggering
the TA control loop.
Change-Id: Iebb043ccc710750dff937e2281c23d343b85bda1
Related: OS#6919
---
M bts/BTS_Tests.ttcn
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://gerrit.osmocom.org:29418/osmo-ttcn3-hacks refs/changes/99/41899/1
diff --git a/bts/BTS_Tests.ttcn b/bts/BTS_Tests.ttcn
index e574cd4..3403863 100644
--- a/bts/BTS_Tests.ttcn
+++ b/bts/BTS_Tests.ttcn
@@ -3891,6 +3891,13 @@
/* tell fake_trx to use a given timing offset for all bursts */
f_trxc_fake_toffs256(ta_to_test*256);
+ /* tell trxcon to use a given TA for UL bursts */
+ g_pars.l1_pars.ms_actual_ta := ta_to_test;
+ f_L1CTL_PARAM(L1CTL, g_pars.l1_pars.ms_actual_ta,
+ g_pars.l1_pars.ms_power_level);
+ /* tell trxcon to use a given TA in UL SACCH blocks
+ * this is achieved by populating UL SACCH cache before doing f_l1ctl_est_dchan() */
+ f_send_meas_rep(ts_MeasurementResults);
f_est_dchan(more_ies :={valueof(t_RSL_IE(RSL_IE_TIMING_ADVANCE, RSL_IE_Body:{timing_adv := ta_to_test}))} );
--
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Gerrit-Change-Id: Iebb043ccc710750dff937e2281c23d343b85bda1
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Gerrit-Owner: fixeria <vyanitskiy(a)sysmocom.de>
fixeria has uploaded this change for review. ( https://gerrit.osmocom.org/c/osmo-ttcn3-hacks/+/41898?usp=email )
Change subject: bts: TC_rsl_chan_initial_ta: misc improvements
......................................................................
bts: TC_rsl_chan_initial_ta: misc improvements
Change-Id: Ifc2c850104b3710679485042ab5b7a758d0ae000
Related: OS#6919
---
M bts/BTS_Tests.ttcn
1 file changed, 7 insertions(+), 9 deletions(-)
git pull ssh://gerrit.osmocom.org:29418/osmo-ttcn3-hacks refs/changes/98/41898/1
diff --git a/bts/BTS_Tests.ttcn b/bts/BTS_Tests.ttcn
index 20c16a3..e574cd4 100644
--- a/bts/BTS_Tests.ttcn
+++ b/bts/BTS_Tests.ttcn
@@ -3883,7 +3883,7 @@
/* establish DChan, verify that the BTS sets the TA in the first SACCH L1 header.
TA for the IMM ASS messages is still controlled by g_pars.l1_pars.ms_actual_ta! */
private function f_tc_rsl_chan_initial_ta(charstring id) runs on ConnHdlr {
- var uint5_t ta_to_test := 16;
+ const uint5_t ta_to_test := 16;
var SacchL1Header l1h;
f_l1_tune(L1CTL);
@@ -3894,18 +3894,16 @@
f_est_dchan(more_ies :={valueof(t_RSL_IE(RSL_IE_TIMING_ADVANCE, RSL_IE_Body:{timing_adv := ta_to_test}))} );
-
+ /* wait for a single DL SACCH block */
alt {
- [] as_l1_sacch_l1h(l1h, do_apply := false) {
- if (l1h.actual_ta != ta_to_test) {
- setverdict(fail, "TA in L1 header does not match the signaled (RSL) TA.");
- }
-
- }
-
+ [] as_l1_sacch_l1h(l1h, do_apply := false);
/* Ignore all other blocks */
[] L1CTL.receive { repeat; }
+ }
+ if (l1h.actual_ta != ta_to_test) {
+ setverdict(fail, "TA=", l1h.actual_ta, " in the DL SACCH does not match ",
+ "the signaled (RSL) TA=", ta_to_test);
}
f_rsl_chan_deact();
--
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