Re: TST PIN and SIMtrace Schematic question

Hi Holger,

On Mon, Aug 15, 2011 at 03:16:56PM +0200, Holger Hans Peter Freyther wrote:

I have a stupid schematic question. I read section 6.2 of the SAM7 datasheet (as in the git tree) and it mentions that besides TST high also PA0, PA1 and PA2 needs to be high, and PA0, PA1 should not be low as this leads to unpredictable results.

Yes, this is correct.

So I wonder about the following:

• PA0 is not connected, default state should be high
• PA1 is connected with a trace that leads to PA6
• PA2 is connected with a trace that leads to PA4

will PA4, PA6 work like a pull down (I am not sure of Table 10-3)?

All GPIO of the SAM7 have internal pull-up resistors which are enabled at boot. Thus, they should all be in high state.