[M] Change in libosmo-gprs[master]: rlcmac: cfg_ul_tbf_req: indicate USF for each active timeslot
fixeria has uploaded this change for review. ( https://gerrit.osmocom.org/c/libosmo-gprs/+/32413 )
Change subject: rlcmac: cfg_ul_tbf_req: indicate USF for each active timeslot ......................................................................
rlcmac: cfg_ul_tbf_req: indicate USF for each active timeslot
According to 3GPP TS 45.002, section 6.3.2.2.1, in the case of multi- slot Uplink TBF allocation, a USF (Uplink State Flag) is given for each PDCH allocated to the MS. Thus we need to indicate a USF value for each PDCH to the lower layers: add ul_usf[8] to cfg_ul_tbf_req.
According to 3GPP TS 44.060, section 5.2.2, in the case of multi-slot Downlink TBF allocation, a DL TFI (Temporary Flow Identity) given to the MS is not limited to the scope of a single PDCH and applies to all timeslots allocated. We're already doing this fine.
Change-Id: I1dda0b4eedcaca7e93f832fc875507028c3ff3eb Related: OS#5500 --- M include/osmocom/gprs/rlcmac/rlcmac_prim.h M src/rlcmac/tbf_ul_fsm.c M tests/rlcmac/rlcmac_prim_test.err 3 files changed, 86 insertions(+), 54 deletions(-)
git pull ssh://gerrit.osmocom.org:29418/libosmo-gprs refs/changes/13/32413/1
diff --git a/include/osmocom/gprs/rlcmac/rlcmac_prim.h b/include/osmocom/gprs/rlcmac/rlcmac_prim.h index cca27f6..9c0bb3c 100644 --- a/include/osmocom/gprs/rlcmac/rlcmac_prim.h +++ b/include/osmocom/gprs/rlcmac/rlcmac_prim.h @@ -155,12 +155,13 @@ struct { uint8_t ul_tbf_nr; uint8_t ul_slotmask; + uint8_t ul_usf[8]; /* USF for each PDCH indicated in the slotmask */ } cfg_ul_tbf_req; /* OSMO_GPRS_RLCMAC_L1CTL_CFG_DL_TBF | Req */ struct { uint8_t dl_tbf_nr; uint8_t dl_slotmask; - uint8_t dl_tfi; + uint8_t dl_tfi; /* DL TFI for all PDCHs indicated in the slotmask */ } cfg_dl_tbf_req; }; }; diff --git a/src/rlcmac/tbf_ul_fsm.c b/src/rlcmac/tbf_ul_fsm.c index dbc5954..e713085 100644 --- a/src/rlcmac/tbf_ul_fsm.c +++ b/src/rlcmac/tbf_ul_fsm.c @@ -56,29 +56,40 @@ g_rlcmac_ctx->T_defs, \ -1)
-static uint8_t ul_tbf_ul_slotmask(struct gprs_rlcmac_ul_tbf *ul_tbf) -{ - uint8_t i; - uint8_t ul_slotmask = 0; - - for (i = 0; i < 8; i++) { - if (ul_tbf->cur_alloc.ts[i].allocated) - ul_slotmask |= (1 << i); - } - - return ul_slotmask; -} - -static int configure_ul_tbf(struct gprs_rlcmac_tbf_ul_fsm_ctx *ctx, bool release) +static int configure_ul_tbf(const struct gprs_rlcmac_tbf_ul_fsm_ctx *ctx) { struct osmo_gprs_rlcmac_prim *rlcmac_prim; - uint8_t ul_slotmask;
- ul_slotmask = release ? 0 : ul_tbf_ul_slotmask(ctx->ul_tbf); + rlcmac_prim = gprs_rlcmac_prim_alloc_l1ctl_cfg_ul_tbf_req(ctx->tbf->nr, 0x00);
- LOGPFSML(ctx->fi, LOGL_INFO, "Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=%u ul_slotmask=0x%02x %s\n", - ctx->tbf->nr, ul_slotmask, release ? "(release)" : "(reconf)"); - rlcmac_prim = gprs_rlcmac_prim_alloc_l1ctl_cfg_ul_tbf_req(ctx->tbf->nr, ul_slotmask); + for (unsigned int tn = 0; tn < ARRAY_SIZE(ctx->ul_tbf->cur_alloc.ts); tn++) { + const struct gprs_rlcmac_ul_tbf_allocation_ts *ts; + + ts = &ctx->ul_tbf->cur_alloc.ts[tn]; + if (!ts->allocated) + continue; + rlcmac_prim->l1ctl.cfg_ul_tbf_req.ul_slotmask |= (1 << tn); + rlcmac_prim->l1ctl.cfg_ul_tbf_req.ul_usf[tn] = ts->usf; + } + + LOGPFSML(ctx->fi, LOGL_INFO, + "Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=%u ul_slotmask=0x%02x\n", + rlcmac_prim->l1ctl.cfg_ul_tbf_req.ul_tbf_nr, + rlcmac_prim->l1ctl.cfg_ul_tbf_req.ul_slotmask); + + return gprs_rlcmac_prim_call_down_cb(rlcmac_prim); +} + +static int release_ul_tbf(const struct gprs_rlcmac_tbf_ul_fsm_ctx *ctx) +{ + struct osmo_gprs_rlcmac_prim *rlcmac_prim; + + rlcmac_prim = gprs_rlcmac_prim_alloc_l1ctl_cfg_ul_tbf_req(ctx->tbf->nr, 0x00); + + LOGPFSML(ctx->fi, LOGL_INFO, + "Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=%u (release)\n", + rlcmac_prim->l1ctl.cfg_ul_tbf_req.ul_tbf_nr); + return gprs_rlcmac_prim_call_down_cb(rlcmac_prim); }
@@ -127,7 +138,7 @@ /* Mark everything we transmitted so far as NACKed: */ gprs_rlcmac_rlc_ul_window_mark_for_resend(ctx->ul_tbf->ulw); /* Make sure the lower layers realize this tbf_nr has no longer any assigned resource: */ - configure_ul_tbf(ctx, true); + release_ul_tbf(ctx); }
static void st_new(struct osmo_fsm_inst *fi, uint32_t event, void *data) @@ -148,7 +159,7 @@ switch (event) { case GPRS_RLCMAC_TBF_UL_EV_UL_ASS_COMPL: /* Configure UL TBF on the lower MAC side: */ - configure_ul_tbf(ctx, false); + configure_ul_tbf(ctx); tbf_ul_fsm_state_chg(fi, GPRS_RLCMAC_TBF_UL_ST_FLOW); break; default: @@ -385,7 +396,7 @@ struct gprs_rlcmac_tbf_ul_fsm_ctx *ctx = &ul_tbf->state_fsm;
/* Make sure the lower layers realize this tbf_nr has no longer any assigned resource: */ - configure_ul_tbf(ctx, true); + release_ul_tbf(ctx);
osmo_fsm_inst_free(ctx->fi); ctx->fi = NULL; diff --git a/tests/rlcmac/rlcmac_prim_test.err b/tests/rlcmac/rlcmac_prim_test.err index 47f4cbc..bf0506d 100644 --- a/tests/rlcmac/rlcmac_prim_test.err +++ b/tests/rlcmac/rlcmac_prim_test.err @@ -15,7 +15,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 (reconf) +DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -63,7 +63,7 @@ DLGLOBAL DEBUG (ts=7,fn=21,usf=0) Tx Pkt Control Ack (UL ACK/NACK poll) DLGLOBAL DEBUG GRE(00002342) Tx Packet Control Ack DLGLOBAL INFO UL_TBF_ASS{IDLE}: Deallocated -DLGLOBAL INFO UL_TBF{RELEASING}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x00 (release) +DLGLOBAL INFO UL_TBF{RELEASING}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 (release) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{RELEASING}: Deallocated DLGLOBAL DEBUG Tx to lower layers: L1CTL-PDCH_DATA.request @@ -85,14 +85,14 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 (reconf) +DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE DLGLOBAL INFO UL_TBF{FLOW}: Timeout of T3164 DLGLOBAL INFO UL_TBF{FLOW}: T3164 timeout attempts=1 DLGLOBAL INFO UL_TBF{FLOW}: state_chg to NEW -DLGLOBAL INFO UL_TBF{NEW}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x00 (reconf) +DLGLOBAL INFO UL_TBF{NEW}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 (release) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF_ASS{IDLE}: Received Event START DLGLOBAL INFO UL_TBF{NEW}: Received Event UL_ASS_START @@ -106,14 +106,14 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 (reconf) +DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE DLGLOBAL INFO UL_TBF{FLOW}: Timeout of T3164 DLGLOBAL INFO UL_TBF{FLOW}: T3164 timeout attempts=2 DLGLOBAL INFO UL_TBF{FLOW}: state_chg to NEW -DLGLOBAL INFO UL_TBF{NEW}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x00 (reconf) +DLGLOBAL INFO UL_TBF{NEW}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 (release) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF_ASS{IDLE}: Received Event START DLGLOBAL INFO UL_TBF{NEW}: Received Event UL_ASS_START @@ -127,14 +127,14 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 (reconf) +DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE DLGLOBAL INFO UL_TBF{FLOW}: Timeout of T3164 DLGLOBAL INFO UL_TBF{FLOW}: T3164 timeout attempts=3 DLGLOBAL INFO UL_TBF{FLOW}: state_chg to NEW -DLGLOBAL INFO UL_TBF{NEW}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x00 (reconf) +DLGLOBAL INFO UL_TBF{NEW}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 (release) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF_ASS{IDLE}: Received Event START DLGLOBAL INFO UL_TBF{NEW}: Received Event UL_ASS_START @@ -148,7 +148,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 (reconf) +DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -156,7 +156,7 @@ DLGLOBAL INFO UL_TBF{FLOW}: T3164 timeout attempts=4 DLGLOBAL NOTICE UL_TBF{FLOW}: TBF establishment failure (T3164 timeout attempts=4) DLGLOBAL INFO UL_TBF_ASS{IDLE}: Deallocated -DLGLOBAL INFO UL_TBF{FLOW}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x00 (release) +DLGLOBAL INFO UL_TBF{FLOW}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 (release) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{FLOW}: Deallocated DLGLOBAL INFO DL_TBF_ASS{IDLE}: Deallocated @@ -177,7 +177,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 (reconf) +DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -198,7 +198,7 @@ DLGLOBAL INFO UL_TBF{FLOW}: Timeout of T3166 DLGLOBAL INFO UL_TBF{FLOW}: T3166 timeout attempts=1 DLGLOBAL INFO UL_TBF{FLOW}: state_chg to NEW -DLGLOBAL INFO UL_TBF{NEW}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x00 (reconf) +DLGLOBAL INFO UL_TBF{NEW}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 (release) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF_ASS{IDLE}: Received Event START DLGLOBAL INFO UL_TBF{NEW}: Received Event UL_ASS_START @@ -212,7 +212,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 (reconf) +DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -230,7 +230,7 @@ DLGLOBAL INFO UL_TBF{FLOW}: Timeout of T3166 DLGLOBAL INFO UL_TBF{FLOW}: T3166 timeout attempts=2 DLGLOBAL INFO UL_TBF{FLOW}: state_chg to NEW -DLGLOBAL INFO UL_TBF{NEW}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x00 (reconf) +DLGLOBAL INFO UL_TBF{NEW}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 (release) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF_ASS{IDLE}: Received Event START DLGLOBAL INFO UL_TBF{NEW}: Received Event UL_ASS_START @@ -244,7 +244,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 (reconf) +DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -262,7 +262,7 @@ DLGLOBAL INFO UL_TBF{FLOW}: Timeout of T3166 DLGLOBAL INFO UL_TBF{FLOW}: T3166 timeout attempts=3 DLGLOBAL INFO UL_TBF{FLOW}: state_chg to NEW -DLGLOBAL INFO UL_TBF{NEW}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x00 (reconf) +DLGLOBAL INFO UL_TBF{NEW}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 (release) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF_ASS{IDLE}: Received Event START DLGLOBAL INFO UL_TBF{NEW}: Received Event UL_ASS_START @@ -276,7 +276,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 (reconf) +DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -295,7 +295,7 @@ DLGLOBAL INFO UL_TBF{FLOW}: T3166 timeout attempts=4 DLGLOBAL NOTICE UL_TBF{FLOW}: TBF establishment failure (T3166 timeout attempts=4) DLGLOBAL INFO UL_TBF_ASS{IDLE}: Deallocated -DLGLOBAL INFO UL_TBF{FLOW}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x00 (release) +DLGLOBAL INFO UL_TBF{FLOW}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 (release) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{FLOW}: Deallocated DLGLOBAL INFO DL_TBF_ASS{IDLE}: Deallocated @@ -318,7 +318,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 (reconf) +DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -417,7 +417,7 @@ DLGLOBAL NOTICE TBF(UL:NR-0:TLLI-00002342) N3104_MAX (9) reached DLGLOBAL INFO UL_TBF{FINISHED}: Received Event N3104_MAX DLGLOBAL INFO UL_TBF{FINISHED}: state_chg to NEW -DLGLOBAL INFO UL_TBF{NEW}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x00 (reconf) +DLGLOBAL INFO UL_TBF{NEW}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 (release) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF_ASS{IDLE}: Received Event START DLGLOBAL INFO UL_TBF{NEW}: Received Event UL_ASS_START @@ -432,13 +432,13 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 (reconf) +DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE DLGLOBAL INFO DL_TBF_ASS{IDLE}: Deallocated DLGLOBAL INFO UL_TBF_ASS{IDLE}: Deallocated -DLGLOBAL INFO UL_TBF{FLOW}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x00 (release) +DLGLOBAL INFO UL_TBF{FLOW}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 (release) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{FLOW}: Deallocated DLGLOBAL INFO Rx from upper layers: GRR-UNITDATA.request @@ -458,7 +458,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 (reconf) +DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -500,7 +500,7 @@ DLGLOBAL DEBUG Tx to lower layers: L1CTL-PDCH_DATA.request DLGLOBAL INFO UL_TBF{FINISHED}: Timeout of T3182 DLGLOBAL INFO UL_TBF_ASS{IDLE}: Deallocated -DLGLOBAL INFO UL_TBF{FINISHED}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x00 (release) +DLGLOBAL INFO UL_TBF{FINISHED}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 (release) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{FINISHED}: Deallocated DLGLOBAL INFO DL_TBF_ASS{IDLE}: Deallocated @@ -521,7 +521,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 (reconf) +DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -606,7 +606,7 @@ DLGLOBAL INFO UL_TBF{FINISHED}: Last UL block sent (CV=0), start T3182 DLGLOBAL NOTICE UL_TBF{FINISHED}: TBF establishment failure (Data block with CV=0 retransmit attempts=4) DLGLOBAL INFO UL_TBF_ASS{IDLE}: Deallocated -DLGLOBAL INFO UL_TBF{FINISHED}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x00 (release) +DLGLOBAL INFO UL_TBF{FINISHED}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 (release) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{FINISHED}: Deallocated DLGLOBAL DEBUG Tx to lower layers: L1CTL-PDCH_DATA.request @@ -628,7 +628,7 @@ DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: ImmAss DynamicAlloc (1phase access) ts_nr=7 usf=0 DLGLOBAL INFO UL_TBF_ASS{WAIT_CCCH_IMM_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 (reconf) +DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x80 DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -671,7 +671,7 @@ DLGLOBAL INFO UL_TBF{NEW}: state_chg to ASSIGN DLGLOBAL INFO UL_TBF_ASS{IDLE}: state_chg to SCHED_PKT_RES_REQ DLGLOBAL INFO UL_TBF_ASS{IDLE}: Deallocated -DLGLOBAL INFO UL_TBF{RELEASING}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x00 (release) +DLGLOBAL INFO UL_TBF{RELEASING}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 (release) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{RELEASING}: Deallocated DLGLOBAL INFO UL_TBF_ASS{SCHED_PKT_RES_REQ}: Received Event CREATE_RLCMAC_MSG @@ -679,7 +679,7 @@ DLGLOBAL DEBUG Tx to lower layers: L1CTL-PDCH_DATA.request DLGLOBAL INFO DL_TBF_ASS{IDLE}: Deallocated DLGLOBAL INFO UL_TBF_ASS{WAIT_PKT_UL_ASS}: Deallocated -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=1 ul_slotmask=0x00 (release) +DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=1 (release) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: Deallocated DLGLOBAL INFO Rx from upper layers: GMMRR-ASSIGN.request @@ -765,7 +765,7 @@ DLGLOBAL DEBUG Register POLL (TS=7 FN=43, reason=UL_ASS) DLGLOBAL INFO UL_TBF_ASS{WAIT_PKT_UL_ASS}: state_chg to COMPLETED DLGLOBAL INFO UL_TBF{ASSIGN}: Received Event UL_ASS_COMPL -DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0xc0 (reconf) +DLGLOBAL INFO UL_TBF{ASSIGN}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0xc0 DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{ASSIGN}: state_chg to FLOW DLGLOBAL INFO UL_TBF_ASS{COMPLETED}: state_chg to IDLE @@ -793,6 +793,6 @@ DLGLOBAL INFO DL_TBF_ASS{IDLE}: Deallocated DLGLOBAL INFO DL_TBF{FINISHED}: Deallocated DLGLOBAL INFO UL_TBF_ASS{IDLE}: Deallocated -DLGLOBAL INFO UL_TBF{FINISHED}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 ul_slotmask=0x00 (release) +DLGLOBAL INFO UL_TBF{FINISHED}: Send L1CTL-CFG_UL_TBF.req ul_tbf_nr=0 (release) DLGLOBAL DEBUG Tx to lower layers: L1CTL-CFG_UL_TBF.request DLGLOBAL INFO UL_TBF{FINISHED}: Deallocated
-
fixeria