tnt has uploaded this change for review. ( https://gerrit.osmocom.org/c/osmo-e1-hardware/+/28008 )
Change subject: gateware/common: Unify a bit with other repo ......................................................................
gateware/common: Unify a bit with other repo
This just pulls in some small update in various files shared by several repository. It's mostly comment and formatting, nothing functionnal really.
Signed-off-by: Sylvain Munaut tnt@246tNt.com Change-Id: Icb7bea1cf7243e9ace819cd567eb006fcc71c808 --- M gateware/common/fw/Makefile D gateware/common/fw/bin2hex.py M gateware/common/fw/boot.S M gateware/common/rtl/soc_picorv32_bridge.v 4 files changed, 72 insertions(+), 41 deletions(-)
git pull ssh://gerrit.osmocom.org:29418/osmo-e1-hardware refs/changes/08/28008/1
diff --git a/gateware/common/fw/Makefile b/gateware/common/fw/Makefile index 3fef9a5..52889ee 100644 --- a/gateware/common/fw/Makefile +++ b/gateware/common/fw/Makefile @@ -1,12 +1,14 @@ -CROSS = riscv-none-embed- +CROSS ?= riscv-none-embed-
CC := $(CROSS)gcc OBJCOPY := $(CROSS)objcopy
-CFLAGS=-Wall -Os -march=rv32i -mabi=ilp32 -ffreestanding -flto -nostartfiles -fomit-frame-pointer -Wl,--gc-section +CFLAGS=-Wall -Os -march=rv32i -mabi=ilp32 -ffreestanding -flto -nostartfiles -fomit-frame-pointer -Wl,--gc-section --specs=nano.specs +
all: boot.hex
+ boot.elf: lnk-boot.lds boot.S $(CC) $(CFLAGS) -Wl,-Bstatic,-T,lnk-boot.lds,--strip-debug -DAPP_FLASH_ADDR=0x000a0000 -o $@ boot.S
@@ -14,7 +16,7 @@ $(OBJCOPY) -O binary $< $@
%.hex: %.bin - ./bin2hex.py $< $@ + hexdump boot.bin -ve '1/4 "%08x\n"' $< > $@
clean: rm -f *.bin *.hex *.elf *.o diff --git a/gateware/common/fw/bin2hex.py b/gateware/common/fw/bin2hex.py deleted file mode 100755 index 43ba263..0000000 --- a/gateware/common/fw/bin2hex.py +++ /dev/null @@ -1,22 +0,0 @@ -#!/usr/bin/env python3 -# -# Converts binary into something that can be used by `readmemh` -# -# Copyright (C) 2020 Sylvain Munaut tnt@246tNt.com -# SPDX-License-Identifier: MIT -# - -import struct -import sys - - -def main(argv0, in_name, out_name): - with open(in_name, 'rb') as in_fh, open(out_name, 'w') as out_fh: - while True: - b = in_fh.read(4) - if len(b) < 4: - break - out_fh.write('%08x\n' % struct.unpack('<I', b)) - -if __name__ == '__main__': - main(*sys.argv) diff --git a/gateware/common/fw/boot.S b/gateware/common/fw/boot.S index df4f41b..b01fc80 100644 --- a/gateware/common/fw/boot.S +++ b/gateware/common/fw/boot.S @@ -3,10 +3,13 @@ * * SPI boot code * - * Copyright (C) 2020 Sylvain Munaut tnt@246tNt.com + * Copyright (C) 2020-2022 Sylvain Munaut tnt@246tNt.com * SPDX-License-Identifier: MIT */
+// #define BOOT_DEBUG +// (also set UART_DIV for the board below !) + #ifndef APP_FLASH_ADDR #define APP_FLASH_ADDR 0x00100000 #endif @@ -19,18 +22,50 @@ #define APP_SIZE 0x00010000 #endif
+ .equ UART_BASE, 0x81000000 + .equ UART_DIV, 29 // 30.72 MHz / (29+2) ~= 1 Mbaud (icE1usb) + //.equ UART_DIV, 22 // 24 MHz / (22+2) ~= 1 Mbaud (e1-tracer) + .section .text.start .global _start _start: + // Debug +#ifdef BOOT_DEBUG + // Set UART divisor + li a0, UART_BASE + li a1, UART_DIV + sw a1, 4(a0) + + // Output 'a' + li a1, 97 + sw a1, 0(a0) +#endif + // SPI init jal spi_init
+ // Debug +#ifdef BOOT_DEBUG + // Output 'b' + li a0, UART_BASE + li a1, 98 + sw a1, 0(a0) +#endif + // Read from flash to SRAM li a0, APP_SRAM_ADDR li a1, APP_SIZE li a2, APP_FLASH_ADDR jal spi_flash_read
+ // Debug +#ifdef BOOT_DEBUG + // Output 'c' + li a0, UART_BASE + li a1, 99 + sw a1, 0(a0) +#endif + // Setup reboot code li t0, 0x0002006f sw t0, 0(zero) @@ -39,16 +74,27 @@ j APP_SRAM_ADDR
- .equ SPI_BASE, 0x80000000 - .equ SPICR0, 4 * 0x08 - .equ SPICR1, 4 * 0x09 - .equ SPICR2, 4 * 0x0a - .equ SPIBR, 4 * 0x0b - .equ SPISR, 4 * 0x0c - .equ SPITXDR, 4 * 0x0d - .equ SPIRXDR, 4 * 0x0e - .equ SPICSR, 4 * 0x0f +// --------------------------------------------------------------------------- +// SB_SPI driver code +// ---------------------------------------------------------------------------
+// Register definitions + + .equ SPI_BASE, 0x80000000 + + .equ SPICR0, 4 * 0x08 + .equ SPICR1, 4 * 0x09 + .equ SPICR2, 4 * 0x0a + .equ SPIBR, 4 * 0x0b + .equ SPISR, 4 * 0x0c + .equ SPITXDR, 4 * 0x0d + .equ SPIRXDR, 4 * 0x0e + .equ SPICSR, 4 * 0x0f + + +// Initializes te SPI hardware +// +// Clobbers a0, a1
spi_init: li a0, SPI_BASE @@ -71,11 +117,13 @@ ret
+// Reads a block of memory from SPI flash +// // Params: // a0 - destination pointer // a1 - length (bytes) // a2 - flash offset -// +// Clobbers t0, t1, s0, s1, s2
spi_flash_read: // Save params @@ -121,9 +169,12 @@ jr s2
+// Performs a single 8 bit SPI xfer +// // Params: a0 - Data to TX // Returns: a0 - RX data // Clobbers t0, t1 + _spi_do_one: li t0, SPI_BASE li t1, 0x08 diff --git a/gateware/common/rtl/soc_picorv32_bridge.v b/gateware/common/rtl/soc_picorv32_bridge.v index c0860fe..282a950 100644 --- a/gateware/common/rtl/soc_picorv32_bridge.v +++ b/gateware/common/rtl/soc_picorv32_bridge.v @@ -10,11 +10,11 @@ `default_nettype none
module soc_picorv32_bridge #( - parameter integer WB_N = 8, - parameter integer WB_DW = 32, - parameter integer WB_AW = 16, - parameter integer WB_AI = 2, - parameter integer WB_REG = 0 // [0] = cyc / [1] = addr/wdata/wstrb / [2] = ack/rdata + parameter integer WB_N = 8, + parameter integer WB_DW = 32, + parameter integer WB_AW = 16, + parameter integer WB_AI = 2, + parameter integer WB_REG = 0 // [0] = cyc / [1] = addr/wdata/wstrb / [2] = ack/rdata )( /* PicoRV32 bus */ input wire [31:0] pb_addr,
-
tnt