v2 Prototype issues and fixes

Hi, The v2 prototype I still had a couple of issues so I'll describe them here and the corresponding fixes: - Bad TVS Diode: There is a diode that's supposed to protect against ESD near the antenna connector. Turns out that the component supplier swapped reels IIRC and so that's not a TVS diode that was mounted. My board had the rework to fix this already done. I don't know if any board shipped with the wrong part. It's the small ~ 0603 sized component near the antenna connector and it's supposed to be greenish. The result of this is a ~ 10-15 dB attenuation of the input signal. - Missing LNA bias inductor: The v2 has a LNA at the input but it's missing it's bias inductor which means it's powered off. So instead of boosting the signal by 18 dB, it actually attenuates it quite a lot. Solution is simple: Solder a 0603 bias inductor. Schematics call for a 470nH inductor and make sure to choose a good RF rated one and not random junk. - FPGA 1.2V LDO Oscillation: The output capacitor of the LP3965 regulator generating the 1.2V for the FPGA core has too low an ESR (a ceramic cap is mounted). This regulator needs a capacitor with an ESR greater than 0.5 ohm and lower than 5 ohm for it to be stable. Without this, the LDO is unstable and has high spectral content at 55 kHz and harmonics. This noise is present at the output but also leaks to the input voltage of the LDO which is the 3.3V rail that powers the LNA ... This is causing unwanted images of the signal at f +- 55kHz f+- 110 kHz ... The solution is simple: replace the cap by a tantalum one within the right ESR range. ( I used a TR3A106K016C1700 from Farnell ). This is before the fix: http://i.imgur.com/rRDDQ.png and this is after : http://i.imgur.com/VlOW7.png - Impedance mismatch between E4K output and ADC input: Ideally we'd like to imagine that the E4K IQ output have very low impedance and that the ADC input have very high impedance. Turns out that neither is true: The E4K has a ~ 500 ohm output impedance and the ADC is a track and hold type and the capacitance of the input changes when you start sampling, causing a small current flow. The combination of the 2 creates a noise at the sampling frequency on the IQ lines ... The effect of this is currently unknown and is being investigated ... it might be possible to lower the noise floor a bit and get less DC offset with this. But it certainly doesn't have as much impact as the 3 erratas above for sure. See for components location. http://i.imgur.com/M4Lvt.jpg Cheers, Sylvain