AW: BS-11 PLL clock source / calibration

[Andreas.Eversberg]

just find pin 118 of the E1 controller on the pcm bus (connector) and compare the clock (4096khz) with pin 54 on the HFC-S PCI ISDN controller. use an oscilloscope and sync it to ISDN interface. one pin higher (on both controllers) you will find 8khz frame clock signal.

if the clock differs by 1ppm, the phase of both signals cycles about four times a second. for rough calibration, i would suggest the 8khz signal. it will take 125 seconds for a full phase shift at 1ppm clock skew.


-----Ursprüngliche Nachricht-----
Von: Dieter Spaar [mailto:spaar at mirider.augusta.de] 
Gesendet: Freitag, 17. April 2009 15:03
An: Andreas.Eversberg
Cc: openbsc at lists.gnumonks.org
Betreff: Re: AW: BS-11 PLL clock source / calibration

Hello Andreas,

On Fri, 17 Apr 2009 12:45:50 +0200, "Andreas.Eversberg" <Andreas.Eversberg at versatel.de> wrote:
> if you need clock signals, you can use the C4IO clock line of the ISDN
> cards. they clock 4096khz. you can use them to transfer clock from one
> card to another or to mesure the clock. the E1 card has this clock on
> one pin of the PCM connector. (see data sheet) the C4IO is also
> available on the HFC-PCI single port card. with an oscilloscope you can
> compare.
> 
> in order to retieve the clock from E1 interface in NT-mode, you need to:
> 
> modprobe hfcmulti port=0x200 debug=0x40000
> 
> watch the dmesg about init process of controller. this will override the
> default behavior: provide clock to the NT interface.
> 
> i would suggest to use a resistor of 1K to protect the e1 card. the
> signal must not look good, we just need the shift of both signals.

Thanks for this tip. I already though about the E1 clock, but its
below the 10 MHz limit of the HP8922. I think I have to build a
simple frequency counter (I don't have one) and use the reference
clock of the HP8922. BTW, there is also a GSM frame pulse available
at one of the connectors (one of the J01 pins, I have to look
it up).

OK, maybe a simple frequency counter is a good reason to finally do
something usefull with my FPGA boards ;-)

Best regards,
  Dieter
-- 
Dieter Spaar, Germany                           spaar at mirider.augusta.de