Change in osmo-ccid-firmware[master]: add ISO7816 peripherals

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Kévin Redon gerrit-no-reply at lists.osmocom.org
Thu Feb 7 16:08:17 UTC 2019 

Kévin Redon has submitted this change and it was merged. ( https://gerrit.osmocom.org/12811 )

Change subject: add ISO7816 peripherals
......................................................................

add ISO7816 peripherals

configure SERCOM 0 to 6 peripherals to communicate using the
ISO7816 T=0 protocol.
SERCOM7 should be for the 8th SIM card, but for now it is used as
UART debug output.
Auto-detection between SERCOM for the 8th SIM and debug UART will
be done later.

Change-Id: I3f1411ec5bc2ed7dfa714550d041f52be665132a
---
M sysmoOCTSIM/atmel_start_config.atstart
M sysmoOCTSIM/atmel_start_pins.h
M sysmoOCTSIM/config/hpl_sercom_config.h
M sysmoOCTSIM/config/peripheral_clk_config.h
M sysmoOCTSIM/driver_init.c
M sysmoOCTSIM/driver_init.h
M sysmoOCTSIM/examples/driver_examples.c
M sysmoOCTSIM/examples/driver_examples.h
M sysmoOCTSIM/hpl/sercom/hpl_sercom.c
9 files changed, 3,619 insertions(+), 0 deletions(-)

Approvals:
  Jenkins Builder: Verified
  Harald Welte: Looks good to me, approved



diff --git a/sysmoOCTSIM/atmel_start_config.atstart b/sysmoOCTSIM/atmel_start_config.atstart
index b6303f9..975423d 100644
--- a/sysmoOCTSIM/atmel_start_config.atstart
+++ b/sysmoOCTSIM/atmel_start_config.atstart
@@ -943,6 +943,307 @@
     variant: null
     clocks:
       domain_group: null
+  SIM0:
+    user_label: SIM0
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM0::driver_config_definition::USART.with.ISO7816::HAL:Driver:USART.Async
+    functionality: USART
+    api: HAL:Driver:USART_Async
+    configuration:
+      usart_advanced: false
+      usart_arch_clock_mode: USART with internal clock
+      usart_arch_cloden: false
+      usart_arch_dbgstop: Keep running
+      usart_arch_dord: LSB is transmitted first
+      usart_arch_ibon: false
+      usart_arch_runstdby: false
+      usart_arch_sfde: false
+      usart_baud_rate: 9600
+      usart_character_size: 8 bits
+      usart_dsnack: The successive receive NACK is disable.
+      usart_gtime: 2-bit times
+      usart_inack: NACK is transmitted when a parity error is received.
+      usart_inverse_enabled: false
+      usart_iso7816_type: T=0
+      usart_maxiter: 7
+      usart_parity: Even parity
+      usart_rx_enable: true
+      usart_stop_bit: One stop bit
+      usart_tx_enable: true
+    optional_signals: []
+    variant:
+      specification: TXPO=2, RXPO=0
+      required_signals:
+      - name: SERCOM0/PAD/0
+        pad: PA04
+        label: RX/TX
+    clocks:
+      domain_group:
+        nodes:
+        - name: Core
+          input: Generic clock generator 2
+        - name: Slow
+          input: Generic clock generator 3
+        configuration:
+          core_gclk_selection: Generic clock generator 2
+          slow_gclk_selection: Generic clock generator 3
+  SIM1:
+    user_label: SIM1
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM1::driver_config_definition::USART.with.ISO7816::HAL:Driver:USART.Async
+    functionality: USART
+    api: HAL:Driver:USART_Async
+    configuration:
+      usart_advanced: false
+      usart_arch_clock_mode: USART with internal clock
+      usart_arch_cloden: false
+      usart_arch_dbgstop: Keep running
+      usart_arch_dord: LSB is transmitted first
+      usart_arch_ibon: false
+      usart_arch_runstdby: false
+      usart_arch_sfde: false
+      usart_baud_rate: 9600
+      usart_character_size: 8 bits
+      usart_dsnack: The successive receive NACK is disable.
+      usart_gtime: 2-bit times
+      usart_inack: NACK is transmitted when a parity error is received.
+      usart_inverse_enabled: false
+      usart_iso7816_type: T=0
+      usart_maxiter: 7
+      usart_parity: Even parity
+      usart_rx_enable: true
+      usart_stop_bit: One stop bit
+      usart_tx_enable: true
+    optional_signals: []
+    variant:
+      specification: TXPO=2, RXPO=0
+      required_signals:
+      - name: SERCOM1/PAD/0
+        pad: PA16
+        label: RX/TX
+    clocks:
+      domain_group:
+        nodes:
+        - name: Core
+          input: Generic clock generator 2
+        - name: Slow
+          input: Generic clock generator 3
+        configuration:
+          core_gclk_selection: Generic clock generator 2
+          slow_gclk_selection: Generic clock generator 3
+  SIM2:
+    user_label: SIM2
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM2::driver_config_definition::USART.with.ISO7816::HAL:Driver:USART.Async
+    functionality: USART
+    api: HAL:Driver:USART_Async
+    configuration:
+      usart_advanced: false
+      usart_arch_clock_mode: USART with internal clock
+      usart_arch_cloden: false
+      usart_arch_dbgstop: Keep running
+      usart_arch_dord: LSB is transmitted first
+      usart_arch_ibon: false
+      usart_arch_runstdby: false
+      usart_arch_sfde: false
+      usart_baud_rate: 9600
+      usart_character_size: 8 bits
+      usart_dsnack: The successive receive NACK is disable.
+      usart_gtime: 2-bit times
+      usart_inack: NACK is transmitted when a parity error is received.
+      usart_inverse_enabled: false
+      usart_iso7816_type: T=0
+      usart_maxiter: 7
+      usart_parity: Even parity
+      usart_rx_enable: true
+      usart_stop_bit: One stop bit
+      usart_tx_enable: true
+    optional_signals: []
+    variant:
+      specification: TXPO=2, RXPO=0
+      required_signals:
+      - name: SERCOM2/PAD/0
+        pad: PA09
+        label: RX/TX
+    clocks:
+      domain_group:
+        nodes:
+        - name: Core
+          input: Generic clock generator 2
+        - name: Slow
+          input: Generic clock generator 3
+        configuration:
+          core_gclk_selection: Generic clock generator 2
+          slow_gclk_selection: Generic clock generator 3
+  SIM3:
+    user_label: SIM3
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM3::driver_config_definition::USART.with.ISO7816::HAL:Driver:USART.Async
+    functionality: USART
+    api: HAL:Driver:USART_Async
+    configuration:
+      usart_advanced: false
+      usart_arch_clock_mode: USART with internal clock
+      usart_arch_cloden: false
+      usart_arch_dbgstop: Keep running
+      usart_arch_dord: LSB is transmitted first
+      usart_arch_ibon: false
+      usart_arch_runstdby: false
+      usart_arch_sfde: false
+      usart_baud_rate: 9600
+      usart_character_size: 8 bits
+      usart_dsnack: The successive receive NACK is disable.
+      usart_gtime: 2-bit times
+      usart_inack: NACK is transmitted when a parity error is received.
+      usart_inverse_enabled: false
+      usart_iso7816_type: T=0
+      usart_maxiter: 7
+      usart_parity: Even parity
+      usart_rx_enable: true
+      usart_stop_bit: One stop bit
+      usart_tx_enable: true
+    optional_signals: []
+    variant:
+      specification: TXPO=2, RXPO=0
+      required_signals:
+      - name: SERCOM3/PAD/0
+        pad: PB20
+        label: RX/TX
+    clocks:
+      domain_group:
+        nodes:
+        - name: Core
+          input: Generic clock generator 2
+        - name: Slow
+          input: Generic clock generator 3
+        configuration:
+          core_gclk_selection: Generic clock generator 2
+          slow_gclk_selection: Generic clock generator 3
+  SIM4:
+    user_label: SIM4
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM4::driver_config_definition::USART.with.ISO7816::HAL:Driver:USART.Async
+    functionality: USART
+    api: HAL:Driver:USART_Async
+    configuration:
+      usart_advanced: false
+      usart_arch_clock_mode: USART with internal clock
+      usart_arch_cloden: false
+      usart_arch_dbgstop: Keep running
+      usart_arch_dord: LSB is transmitted first
+      usart_arch_ibon: false
+      usart_arch_runstdby: false
+      usart_arch_sfde: false
+      usart_baud_rate: 9600
+      usart_character_size: 8 bits
+      usart_dsnack: The successive receive NACK is disable.
+      usart_gtime: 2-bit times
+      usart_inack: NACK is transmitted when a parity error is received.
+      usart_inverse_enabled: false
+      usart_iso7816_type: T=0
+      usart_maxiter: 7
+      usart_parity: Even parity
+      usart_rx_enable: true
+      usart_stop_bit: One stop bit
+      usart_tx_enable: true
+    optional_signals: []
+    variant:
+      specification: TXPO=2, RXPO=0
+      required_signals:
+      - name: SERCOM4/PAD/0
+        pad: PB08
+        label: RX/TX
+    clocks:
+      domain_group:
+        nodes:
+        - name: Core
+          input: Generic clock generator 2
+        - name: Slow
+          input: Generic clock generator 3
+        configuration:
+          core_gclk_selection: Generic clock generator 2
+          slow_gclk_selection: Generic clock generator 3
+  SIM5:
+    user_label: SIM5
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM5::driver_config_definition::USART.with.ISO7816::HAL:Driver:USART.Async
+    functionality: USART
+    api: HAL:Driver:USART_Async
+    configuration:
+      usart_advanced: false
+      usart_arch_clock_mode: USART with internal clock
+      usart_arch_cloden: false
+      usart_arch_dbgstop: Keep running
+      usart_arch_dord: LSB is transmitted first
+      usart_arch_ibon: false
+      usart_arch_runstdby: false
+      usart_arch_sfde: false
+      usart_baud_rate: 9600
+      usart_character_size: 8 bits
+      usart_dsnack: The successive receive NACK is disable.
+      usart_gtime: 2-bit times
+      usart_inack: NACK is transmitted when a parity error is received.
+      usart_inverse_enabled: false
+      usart_iso7816_type: T=0
+      usart_maxiter: 7
+      usart_parity: Even parity
+      usart_rx_enable: true
+      usart_stop_bit: One stop bit
+      usart_tx_enable: true
+    optional_signals: []
+    variant:
+      specification: TXPO=2, RXPO=0
+      required_signals:
+      - name: SERCOM5/PAD/0
+        pad: PB16
+        label: RX/TX
+    clocks:
+      domain_group:
+        nodes:
+        - name: Core
+          input: Generic clock generator 2
+        - name: Slow
+          input: Generic clock generator 3
+        configuration:
+          core_gclk_selection: Generic clock generator 2
+          slow_gclk_selection: Generic clock generator 3
+  SIM6:
+    user_label: SIM6
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM6::driver_config_definition::USART.with.ISO7816::HAL:Driver:USART.Async
+    functionality: USART
+    api: HAL:Driver:USART_Async
+    configuration:
+      usart_advanced: false
+      usart_arch_clock_mode: USART with internal clock
+      usart_arch_cloden: false
+      usart_arch_dbgstop: Keep running
+      usart_arch_dord: LSB is transmitted first
+      usart_arch_ibon: false
+      usart_arch_runstdby: false
+      usart_arch_sfde: false
+      usart_baud_rate: 9600
+      usart_character_size: 8 bits
+      usart_dsnack: The successive receive NACK is disable.
+      usart_gtime: 2-bit times
+      usart_inack: NACK is transmitted when a parity error is received.
+      usart_inverse_enabled: false
+      usart_iso7816_type: T=0
+      usart_maxiter: 7
+      usart_parity: Even parity
+      usart_rx_enable: true
+      usart_stop_bit: One stop bit
+      usart_tx_enable: true
+    optional_signals: []
+    variant:
+      specification: TXPO=2, RXPO=0
+      required_signals:
+      - name: SERCOM6/PAD/0
+        pad: PC16
+        label: RX/TX
+    clocks:
+      domain_group:
+        nodes:
+        - name: Core
+          input: Generic clock generator 2
+        - name: Slow
+          input: Generic clock generator 3
+        configuration:
+          core_gclk_selection: Generic clock generator 2
+          slow_gclk_selection: Generic clock generator 3
   UART_debug:
     user_label: UART_debug
     definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM7::driver_config_definition::UART::HAL:Driver:USART.Async
@@ -1030,6 +1331,24 @@
         configuration:
           usb_gclk_selection: Generic clock generator 1
 pads:
+  SIM4_IO:
+    name: PB08
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PB08
+    mode: Peripheral IO
+    user_label: SIM4_IO
+    configuration: null
+  SIM0_IO:
+    name: PA04
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA04
+    mode: Peripheral IO
+    user_label: SIM0_IO
+    configuration: null
+  SIM2_IO:
+    name: PA09
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA09
+    mode: Peripheral IO
+    user_label: SIM2_IO
+    configuration: null
   SIMCLK_20MHZ:
     name: PA11
     definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA11
@@ -1046,6 +1365,30 @@
     mode: Digital input
     user_label: SWITCH
     configuration: null
+  SIM1_IO:
+    name: PA16
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA16
+    mode: Peripheral IO
+    user_label: SIM1_IO
+    configuration: null
+  SIM6_IO:
+    name: PC16
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PC16
+    mode: Peripheral IO
+    user_label: SIM6_IO
+    configuration: null
+  SIM5_IO:
+    name: PB16
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PB16
+    mode: Peripheral IO
+    user_label: SIM5_IO
+    configuration: null
+  SIM3_IO:
+    name: PB20
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PB20
+    mode: Peripheral IO
+    user_label: SIM3_IO
+    configuration: null
   VB0:
     name: PA20
     definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA20
diff --git a/sysmoOCTSIM/atmel_start_pins.h b/sysmoOCTSIM/atmel_start_pins.h
index fea4388..ad5f27b 100644
--- a/sysmoOCTSIM/atmel_start_pins.h
+++ b/sysmoOCTSIM/atmel_start_pins.h
@@ -27,16 +27,23 @@
 #define GPIO_PIN_FUNCTION_M 12
 #define GPIO_PIN_FUNCTION_N 13
 
+#define SIM0_IO GPIO(GPIO_PORTA, 4)
+#define SIM2_IO GPIO(GPIO_PORTA, 9)
 #define SIMCLK_20MHZ GPIO(GPIO_PORTA, 11)
+#define SIM1_IO GPIO(GPIO_PORTA, 16)
 #define VB0 GPIO(GPIO_PORTA, 20)
 #define VB1 GPIO(GPIO_PORTA, 21)
 #define VB2 GPIO(GPIO_PORTA, 22)
 #define VB3 GPIO(GPIO_PORTA, 23)
 #define USBUP_D_N GPIO(GPIO_PORTA, 24)
 #define USBUP_D_P GPIO(GPIO_PORTA, 25)
+#define SIM4_IO GPIO(GPIO_PORTB, 8)
+#define SIM5_IO GPIO(GPIO_PORTB, 16)
+#define SIM3_IO GPIO(GPIO_PORTB, 20)
 #define UART_TX GPIO(GPIO_PORTB, 30)
 #define UART_RX GPIO(GPIO_PORTB, 31)
 #define SWITCH GPIO(GPIO_PORTC, 14)
+#define SIM6_IO GPIO(GPIO_PORTC, 16)
 #define USER_LED GPIO(GPIO_PORTC, 26)
 
 #endif // ATMEL_START_PINS_H_INCLUDED
diff --git a/sysmoOCTSIM/config/hpl_sercom_config.h b/sysmoOCTSIM/config/hpl_sercom_config.h
index 2a8c023..735fdc2 100644
--- a/sysmoOCTSIM/config/hpl_sercom_config.h
+++ b/sysmoOCTSIM/config/hpl_sercom_config.h
@@ -6,6 +6,1910 @@
 
 #include <peripheral_clk_config.h>
 
+#ifndef CONF_SERCOM_0_USART_ENABLE
+#define CONF_SERCOM_0_USART_ENABLE 1
+#endif
+
+// <h> Basic Configuration
+
+// <q> Receive buffer enable
+// <i> Enable input buffer in SERCOM module
+// <id> usart_rx_enable
+#ifndef CONF_SERCOM_0_USART_RXEN
+#define CONF_SERCOM_0_USART_RXEN 1
+#endif
+
+// <q> Transmitt buffer enable
+// <i> Enable output buffer in SERCOM module
+// <id> usart_tx_enable
+#ifndef CONF_SERCOM_0_USART_TXEN
+#define CONF_SERCOM_0_USART_TXEN 1
+#endif
+
+// <o> Frame parity
+// <0x1=>Even parity
+// <i> Parity bit mode for USART frame
+// <id> usart_parity
+#ifndef CONF_SERCOM_0_USART_PARITY
+#define CONF_SERCOM_0_USART_PARITY 1
+#endif
+
+// <o> Character Size
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <0x5=>5 bits
+// <0x6=>6 bits
+// <0x7=>7 bits
+// <i> Data character size in USART frame
+// <id> usart_character_size
+#ifndef CONF_SERCOM_0_USART_CHSIZE
+#define CONF_SERCOM_0_USART_CHSIZE 0x0
+#endif
+
+// <o> Stop Bit
+// <0=>One stop bit
+// <1=>Two stop bits
+// <i> Number of stop bits in USART frame
+// <id> usart_stop_bit
+#ifndef CONF_SERCOM_0_USART_SBMODE
+#define CONF_SERCOM_0_USART_SBMODE 0
+#endif
+
+// <o> Baud rate <1-3000000>
+// <i> USART baud rate setting
+// <id> usart_baud_rate
+#ifndef CONF_SERCOM_0_USART_BAUD
+#define CONF_SERCOM_0_USART_BAUD 9600
+#endif
+// </h>
+
+// <h> ISO7816 configuration
+// <o> ISO7816 Protocol Type
+// <0x1=> T=0
+// <0x0=> T=1
+// <i> Define ISO7816 protocol type as 0.
+// <id> usart_iso7816_type
+#ifndef CONF_SERCOM_0_USART_ISO7816_PROTOCOL_T
+#define CONF_SERCOM_0_USART_ISO7816_PROTOCOL_T 0x1
+#endif
+
+// <o> ISO7816 Inhibit Not Acknowledge
+// <0x0=> NACK is transmitted when a parity error is received.
+// <0x1=> NACK is not transmitted when a parity error is received.
+// <i> Define whether a NACK is transmitted when a parity error is received.
+// <id> usart_inack
+#ifndef CONF_SERCOM_0_USART_INACK
+#define CONF_SERCOM_0_USART_INACK 0x0
+#endif
+
+// <o> ISO7816 Disable Successive Not Acknowledge
+// <0x0=> The successive receive NACK is disable.
+// <0x1=> The successive receive NACK is enable.
+// <i> Define whether NACK will be sent on parity error reception.
+// <id> usart_dsnack
+#ifndef CONF_SERCOM_0_USART_DSNACK
+#define CONF_SERCOM_0_USART_DSNACK 0x0
+#endif
+
+// <o> ISO7816 Maximum Iterations<0-7>
+// <i> Define the maximum number of retransmit iterations.
+// <id> usart_maxiter
+#ifndef CONF_SERCOM_0_USART_MAXITER
+#define CONF_SERCOM_0_USART_MAXITER 0x7
+#endif
+
+// <o> ISO7816 Guard Time
+// <0x2=> 2-bit times
+// <0x3=> 3-bit times
+// <0x4=> 4-bit times
+// <0x5=> 5-bit times
+// <0x6=> 6-bit times
+// <0x7=> 7-bit times
+// <i> Define the guard time.
+// <id> usart_gtime
+#ifndef CONF_SERCOM_0_USART_GTIME
+#define CONF_SERCOM_0_USART_GTIME 0x2
+#endif
+
+// <q> Inverse transmission and reception enabled
+// <i> Define inverse transmission and reception enabled.
+// <id> usart_inverse_enabled
+#ifndef CONF_SERCOM_0_USART_INVERSE_ENABLED
+#define CONF_SERCOM_0_USART_INVERSE_ENABLED 0x0
+#endif
+
+#if (CONF_SERCOM_0_USART_INVERSE_ENABLED == 1)
+#define CONF_SERCOM_0_USART_RXINV 0x1
+#define CONF_SERCOM_0_USART_TXINV 0x1
+#else
+#define CONF_SERCOM_0_USART_RXINV 0x0
+#define CONF_SERCOM_0_USART_TXINV 0x0
+#endif
+
+// </h>
+
+// <e> Advanced configuration
+// <id> usart_advanced
+#ifndef CONF_SERCOM_0_USART_ADVANCED_CONFIG
+#define CONF_SERCOM_0_USART_ADVANCED_CONFIG 0
+#endif
+
+// <q> Run in stand-by
+// <i> Keep the module running in standby sleep mode
+// <id> usart_arch_runstdby
+#ifndef CONF_SERCOM_0_USART_RUNSTDBY
+#define CONF_SERCOM_0_USART_RUNSTDBY 0
+#endif
+
+// <q> Immediate Buffer Overflow Notification
+// <i> Controls when the BUFOVF status bit is asserted
+// <id> usart_arch_ibon
+#ifndef CONF_SERCOM_0_USART_IBON
+#define CONF_SERCOM_0_USART_IBON 0
+#endif
+
+// <q> Start of Frame Detection Enable
+// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
+// <id> usart_arch_sfde
+#ifndef CONF_SERCOM_0_USART_SFDE
+#define CONF_SERCOM_0_USART_SFDE 0
+#endif
+
+// <q> Collision Detection Enable
+// <i> Collision detection enable
+// <id> usart_arch_cloden
+#ifndef CONF_SERCOM_0_USART_CLODEN
+#define CONF_SERCOM_0_USART_CLODEN 0
+#endif
+
+// <o> Operating Mode
+// <0x1=>USART with internal clock
+// <i> Drive the shift register by an internal clock generated by the baud rate generator.
+// <id> usart_arch_clock_mode
+#ifndef CONF_SERCOM_0_USART_MODE
+#define CONF_SERCOM_0_USART_MODE 0x1
+#endif
+
+// <o> Data Order
+// <0=>MSB is transmitted first
+// <1=>LSB is transmitted first
+// <i> Data order of the data bits in the frame
+// <id> usart_arch_dord
+#ifndef CONF_SERCOM_0_USART_DORD
+#define CONF_SERCOM_0_USART_DORD 1
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
+// <0=>Keep running
+// <1=>Halt
+// <id> usart_arch_dbgstop
+#ifndef CONF_SERCOM_0_USART_DEBUG_STOP_MODE
+#define CONF_SERCOM_0_USART_DEBUG_STOP_MODE 0
+#endif
+
+// Does not do anything in USRT mode
+#define CONF_SERCOM_0_USART_SAMPR 0x0
+#define CONF_SERCOM_0_USART_SAMPA 0x0
+#define CONF_SERCOM_0_USART_FRACTIONAL 0x0
+
+// Does not do anything in UART mode
+#define CONF_SERCOM_0_USART_CPOL 0
+
+// Does not do anything in USRT mode
+#define CONF_SERCOM_0_USART_ENC 0
+
+// </e>
+
+#ifndef CONF_SERCOM_0_USART_CMODE
+#define CONF_SERCOM_0_USART_CMODE CONF_SERCOM_0_USART_ISO7816_PROTOCOL_T
+#endif
+
+/* RX is on PIN_PA04 */
+#ifndef CONF_SERCOM_0_USART_RXPO
+#define CONF_SERCOM_0_USART_RXPO 0
+#endif
+
+/* TX uses the same pin with RX */
+#ifndef CONF_SERCOM_0_USART_TXPO
+#define CONF_SERCOM_0_USART_TXPO 2
+#endif
+
+/* Set iso7816 mode */
+#define CONF_SERCOM_0_USART_PMODE (CONF_SERCOM_0_USART_PARITY - 1)
+#define CONF_SERCOM_0_USART_FORM 7
+
+#if CONF_SERCOM_0_USART_CMODE == 0
+// Calculate BAUD register value in UART mode
+#if CONF_SERCOM_0_USART_SAMPR == 0
+#ifndef CONF_SERCOM_0_USART_BAUD_RATE
+#define CONF_SERCOM_0_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 16.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_0_USART_SAMPR == 1
+#ifndef CONF_SERCOM_0_USART_BAUD_RATE
+#define CONF_SERCOM_0_USART_BAUD_RATE                                                                                  \
+	((CONF_GCLK_SERCOM0_CORE_FREQUENCY) / (CONF_SERCOM_0_USART_BAUD * 16)) - (CONF_SERCOM_0_USART_FRACTIONAL / 8)
+#endif
+#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_0_USART_SAMPR == 2
+#ifndef CONF_SERCOM_0_USART_BAUD_RATE
+#define CONF_SERCOM_0_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 8.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_0_USART_SAMPR == 3
+#ifndef CONF_SERCOM_0_USART_BAUD_RATE
+#define CONF_SERCOM_0_USART_BAUD_RATE                                                                                  \
+	((CONF_GCLK_SERCOM0_CORE_FREQUENCY) / (CONF_SERCOM_0_USART_BAUD * 8)) - (CONF_SERCOM_0_USART_FRACTIONAL / 8)
+#endif
+#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_0_USART_SAMPR == 4
+#ifndef CONF_SERCOM_0_USART_BAUD_RATE
+#define CONF_SERCOM_0_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 3.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#endif
+
+#elif CONF_SERCOM_0_USART_CMODE == 1
+#ifndef CONF_SERCOM_0_USART_BAUD_RATE
+// Calculate BAUD register value in USRT mode
+#define CONF_SERCOM_0_USART_BAUD_RATE (CONF_GCLK_SERCOM0_CORE_FREQUENCY) / (2 * CONF_SERCOM_0_USART_BAUD) - 1
+#endif
+
+#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#else
+#error CMODE value for SERCOM 0 in USART mode not known
+#endif
+
+#include <peripheral_clk_config.h>
+
+#ifndef CONF_SERCOM_1_USART_ENABLE
+#define CONF_SERCOM_1_USART_ENABLE 1
+#endif
+
+// <h> Basic Configuration
+
+// <q> Receive buffer enable
+// <i> Enable input buffer in SERCOM module
+// <id> usart_rx_enable
+#ifndef CONF_SERCOM_1_USART_RXEN
+#define CONF_SERCOM_1_USART_RXEN 1
+#endif
+
+// <q> Transmitt buffer enable
+// <i> Enable output buffer in SERCOM module
+// <id> usart_tx_enable
+#ifndef CONF_SERCOM_1_USART_TXEN
+#define CONF_SERCOM_1_USART_TXEN 1
+#endif
+
+// <o> Frame parity
+// <0x1=>Even parity
+// <i> Parity bit mode for USART frame
+// <id> usart_parity
+#ifndef CONF_SERCOM_1_USART_PARITY
+#define CONF_SERCOM_1_USART_PARITY 1
+#endif
+
+// <o> Character Size
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <0x5=>5 bits
+// <0x6=>6 bits
+// <0x7=>7 bits
+// <i> Data character size in USART frame
+// <id> usart_character_size
+#ifndef CONF_SERCOM_1_USART_CHSIZE
+#define CONF_SERCOM_1_USART_CHSIZE 0x0
+#endif
+
+// <o> Stop Bit
+// <0=>One stop bit
+// <1=>Two stop bits
+// <i> Number of stop bits in USART frame
+// <id> usart_stop_bit
+#ifndef CONF_SERCOM_1_USART_SBMODE
+#define CONF_SERCOM_1_USART_SBMODE 0
+#endif
+
+// <o> Baud rate <1-3000000>
+// <i> USART baud rate setting
+// <id> usart_baud_rate
+#ifndef CONF_SERCOM_1_USART_BAUD
+#define CONF_SERCOM_1_USART_BAUD 9600
+#endif
+// </h>
+
+// <h> ISO7816 configuration
+// <o> ISO7816 Protocol Type
+// <0x1=> T=0
+// <0x0=> T=1
+// <i> Define ISO7816 protocol type as 0.
+// <id> usart_iso7816_type
+#ifndef CONF_SERCOM_1_USART_ISO7816_PROTOCOL_T
+#define CONF_SERCOM_1_USART_ISO7816_PROTOCOL_T 0x1
+#endif
+
+// <o> ISO7816 Inhibit Not Acknowledge
+// <0x0=> NACK is transmitted when a parity error is received.
+// <0x1=> NACK is not transmitted when a parity error is received.
+// <i> Define whether a NACK is transmitted when a parity error is received.
+// <id> usart_inack
+#ifndef CONF_SERCOM_1_USART_INACK
+#define CONF_SERCOM_1_USART_INACK 0x0
+#endif
+
+// <o> ISO7816 Disable Successive Not Acknowledge
+// <0x0=> The successive receive NACK is disable.
+// <0x1=> The successive receive NACK is enable.
+// <i> Define whether NACK will be sent on parity error reception.
+// <id> usart_dsnack
+#ifndef CONF_SERCOM_1_USART_DSNACK
+#define CONF_SERCOM_1_USART_DSNACK 0x0
+#endif
+
+// <o> ISO7816 Maximum Iterations<0-7>
+// <i> Define the maximum number of retransmit iterations.
+// <id> usart_maxiter
+#ifndef CONF_SERCOM_1_USART_MAXITER
+#define CONF_SERCOM_1_USART_MAXITER 0x7
+#endif
+
+// <o> ISO7816 Guard Time
+// <0x2=> 2-bit times
+// <0x3=> 3-bit times
+// <0x4=> 4-bit times
+// <0x5=> 5-bit times
+// <0x6=> 6-bit times
+// <0x7=> 7-bit times
+// <i> Define the guard time.
+// <id> usart_gtime
+#ifndef CONF_SERCOM_1_USART_GTIME
+#define CONF_SERCOM_1_USART_GTIME 0x2
+#endif
+
+// <q> Inverse transmission and reception enabled
+// <i> Define inverse transmission and reception enabled.
+// <id> usart_inverse_enabled
+#ifndef CONF_SERCOM_1_USART_INVERSE_ENABLED
+#define CONF_SERCOM_1_USART_INVERSE_ENABLED 0x0
+#endif
+
+#if (CONF_SERCOM_1_USART_INVERSE_ENABLED == 1)
+#define CONF_SERCOM_1_USART_RXINV 0x1
+#define CONF_SERCOM_1_USART_TXINV 0x1
+#else
+#define CONF_SERCOM_1_USART_RXINV 0x0
+#define CONF_SERCOM_1_USART_TXINV 0x0
+#endif
+
+// </h>
+
+// <e> Advanced configuration
+// <id> usart_advanced
+#ifndef CONF_SERCOM_1_USART_ADVANCED_CONFIG
+#define CONF_SERCOM_1_USART_ADVANCED_CONFIG 0
+#endif
+
+// <q> Run in stand-by
+// <i> Keep the module running in standby sleep mode
+// <id> usart_arch_runstdby
+#ifndef CONF_SERCOM_1_USART_RUNSTDBY
+#define CONF_SERCOM_1_USART_RUNSTDBY 0
+#endif
+
+// <q> Immediate Buffer Overflow Notification
+// <i> Controls when the BUFOVF status bit is asserted
+// <id> usart_arch_ibon
+#ifndef CONF_SERCOM_1_USART_IBON
+#define CONF_SERCOM_1_USART_IBON 0
+#endif
+
+// <q> Start of Frame Detection Enable
+// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
+// <id> usart_arch_sfde
+#ifndef CONF_SERCOM_1_USART_SFDE
+#define CONF_SERCOM_1_USART_SFDE 0
+#endif
+
+// <q> Collision Detection Enable
+// <i> Collision detection enable
+// <id> usart_arch_cloden
+#ifndef CONF_SERCOM_1_USART_CLODEN
+#define CONF_SERCOM_1_USART_CLODEN 0
+#endif
+
+// <o> Operating Mode
+// <0x1=>USART with internal clock
+// <i> Drive the shift register by an internal clock generated by the baud rate generator.
+// <id> usart_arch_clock_mode
+#ifndef CONF_SERCOM_1_USART_MODE
+#define CONF_SERCOM_1_USART_MODE 0x1
+#endif
+
+// <o> Data Order
+// <0=>MSB is transmitted first
+// <1=>LSB is transmitted first
+// <i> Data order of the data bits in the frame
+// <id> usart_arch_dord
+#ifndef CONF_SERCOM_1_USART_DORD
+#define CONF_SERCOM_1_USART_DORD 1
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
+// <0=>Keep running
+// <1=>Halt
+// <id> usart_arch_dbgstop
+#ifndef CONF_SERCOM_1_USART_DEBUG_STOP_MODE
+#define CONF_SERCOM_1_USART_DEBUG_STOP_MODE 0
+#endif
+
+// Does not do anything in USRT mode
+#define CONF_SERCOM_1_USART_SAMPR 0x0
+#define CONF_SERCOM_1_USART_SAMPA 0x0
+#define CONF_SERCOM_1_USART_FRACTIONAL 0x0
+
+// Does not do anything in UART mode
+#define CONF_SERCOM_1_USART_CPOL 0
+
+// Does not do anything in USRT mode
+#define CONF_SERCOM_1_USART_ENC 0
+
+// </e>
+
+#ifndef CONF_SERCOM_1_USART_CMODE
+#define CONF_SERCOM_1_USART_CMODE CONF_SERCOM_1_USART_ISO7816_PROTOCOL_T
+#endif
+
+/* RX is on PIN_PA16 */
+#ifndef CONF_SERCOM_1_USART_RXPO
+#define CONF_SERCOM_1_USART_RXPO 0
+#endif
+
+/* TX uses the same pin with RX */
+#ifndef CONF_SERCOM_1_USART_TXPO
+#define CONF_SERCOM_1_USART_TXPO 2
+#endif
+
+/* Set iso7816 mode */
+#define CONF_SERCOM_1_USART_PMODE (CONF_SERCOM_1_USART_PARITY - 1)
+#define CONF_SERCOM_1_USART_FORM 7
+
+#if CONF_SERCOM_1_USART_CMODE == 0
+// Calculate BAUD register value in UART mode
+#if CONF_SERCOM_1_USART_SAMPR == 0
+#ifndef CONF_SERCOM_1_USART_BAUD_RATE
+#define CONF_SERCOM_1_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 16.0f * CONF_SERCOM_1_USART_BAUD) / CONF_GCLK_SERCOM1_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_1_USART_SAMPR == 1
+#ifndef CONF_SERCOM_1_USART_BAUD_RATE
+#define CONF_SERCOM_1_USART_BAUD_RATE                                                                                  \
+	((CONF_GCLK_SERCOM1_CORE_FREQUENCY) / (CONF_SERCOM_1_USART_BAUD * 16)) - (CONF_SERCOM_1_USART_FRACTIONAL / 8)
+#endif
+#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_1_USART_SAMPR == 2
+#ifndef CONF_SERCOM_1_USART_BAUD_RATE
+#define CONF_SERCOM_1_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 8.0f * CONF_SERCOM_1_USART_BAUD) / CONF_GCLK_SERCOM1_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_1_USART_SAMPR == 3
+#ifndef CONF_SERCOM_1_USART_BAUD_RATE
+#define CONF_SERCOM_1_USART_BAUD_RATE                                                                                  \
+	((CONF_GCLK_SERCOM1_CORE_FREQUENCY) / (CONF_SERCOM_1_USART_BAUD * 8)) - (CONF_SERCOM_1_USART_FRACTIONAL / 8)
+#endif
+#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_1_USART_SAMPR == 4
+#ifndef CONF_SERCOM_1_USART_BAUD_RATE
+#define CONF_SERCOM_1_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 3.0f * CONF_SERCOM_1_USART_BAUD) / CONF_GCLK_SERCOM1_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#endif
+
+#elif CONF_SERCOM_1_USART_CMODE == 1
+#ifndef CONF_SERCOM_1_USART_BAUD_RATE
+// Calculate BAUD register value in USRT mode
+#define CONF_SERCOM_1_USART_BAUD_RATE (CONF_GCLK_SERCOM1_CORE_FREQUENCY) / (2 * CONF_SERCOM_1_USART_BAUD) - 1
+#endif
+
+#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#else
+#error CMODE value for SERCOM 1 in USART mode not known
+#endif
+
+#include <peripheral_clk_config.h>
+
+#ifndef CONF_SERCOM_2_USART_ENABLE
+#define CONF_SERCOM_2_USART_ENABLE 1
+#endif
+
+// <h> Basic Configuration
+
+// <q> Receive buffer enable
+// <i> Enable input buffer in SERCOM module
+// <id> usart_rx_enable
+#ifndef CONF_SERCOM_2_USART_RXEN
+#define CONF_SERCOM_2_USART_RXEN 1
+#endif
+
+// <q> Transmitt buffer enable
+// <i> Enable output buffer in SERCOM module
+// <id> usart_tx_enable
+#ifndef CONF_SERCOM_2_USART_TXEN
+#define CONF_SERCOM_2_USART_TXEN 1
+#endif
+
+// <o> Frame parity
+// <0x1=>Even parity
+// <i> Parity bit mode for USART frame
+// <id> usart_parity
+#ifndef CONF_SERCOM_2_USART_PARITY
+#define CONF_SERCOM_2_USART_PARITY 1
+#endif
+
+// <o> Character Size
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <0x5=>5 bits
+// <0x6=>6 bits
+// <0x7=>7 bits
+// <i> Data character size in USART frame
+// <id> usart_character_size
+#ifndef CONF_SERCOM_2_USART_CHSIZE
+#define CONF_SERCOM_2_USART_CHSIZE 0x0
+#endif
+
+// <o> Stop Bit
+// <0=>One stop bit
+// <1=>Two stop bits
+// <i> Number of stop bits in USART frame
+// <id> usart_stop_bit
+#ifndef CONF_SERCOM_2_USART_SBMODE
+#define CONF_SERCOM_2_USART_SBMODE 0
+#endif
+
+// <o> Baud rate <1-3000000>
+// <i> USART baud rate setting
+// <id> usart_baud_rate
+#ifndef CONF_SERCOM_2_USART_BAUD
+#define CONF_SERCOM_2_USART_BAUD 9600
+#endif
+// </h>
+
+// <h> ISO7816 configuration
+// <o> ISO7816 Protocol Type
+// <0x1=> T=0
+// <0x0=> T=1
+// <i> Define ISO7816 protocol type as 0.
+// <id> usart_iso7816_type
+#ifndef CONF_SERCOM_2_USART_ISO7816_PROTOCOL_T
+#define CONF_SERCOM_2_USART_ISO7816_PROTOCOL_T 0x1
+#endif
+
+// <o> ISO7816 Inhibit Not Acknowledge
+// <0x0=> NACK is transmitted when a parity error is received.
+// <0x1=> NACK is not transmitted when a parity error is received.
+// <i> Define whether a NACK is transmitted when a parity error is received.
+// <id> usart_inack
+#ifndef CONF_SERCOM_2_USART_INACK
+#define CONF_SERCOM_2_USART_INACK 0x0
+#endif
+
+// <o> ISO7816 Disable Successive Not Acknowledge
+// <0x0=> The successive receive NACK is disable.
+// <0x1=> The successive receive NACK is enable.
+// <i> Define whether NACK will be sent on parity error reception.
+// <id> usart_dsnack
+#ifndef CONF_SERCOM_2_USART_DSNACK
+#define CONF_SERCOM_2_USART_DSNACK 0x0
+#endif
+
+// <o> ISO7816 Maximum Iterations<0-7>
+// <i> Define the maximum number of retransmit iterations.
+// <id> usart_maxiter
+#ifndef CONF_SERCOM_2_USART_MAXITER
+#define CONF_SERCOM_2_USART_MAXITER 0x7
+#endif
+
+// <o> ISO7816 Guard Time
+// <0x2=> 2-bit times
+// <0x3=> 3-bit times
+// <0x4=> 4-bit times
+// <0x5=> 5-bit times
+// <0x6=> 6-bit times
+// <0x7=> 7-bit times
+// <i> Define the guard time.
+// <id> usart_gtime
+#ifndef CONF_SERCOM_2_USART_GTIME
+#define CONF_SERCOM_2_USART_GTIME 0x2
+#endif
+
+// <q> Inverse transmission and reception enabled
+// <i> Define inverse transmission and reception enabled.
+// <id> usart_inverse_enabled
+#ifndef CONF_SERCOM_2_USART_INVERSE_ENABLED
+#define CONF_SERCOM_2_USART_INVERSE_ENABLED 0x0
+#endif
+
+#if (CONF_SERCOM_2_USART_INVERSE_ENABLED == 1)
+#define CONF_SERCOM_2_USART_RXINV 0x1
+#define CONF_SERCOM_2_USART_TXINV 0x1
+#else
+#define CONF_SERCOM_2_USART_RXINV 0x0
+#define CONF_SERCOM_2_USART_TXINV 0x0
+#endif
+
+// </h>
+
+// <e> Advanced configuration
+// <id> usart_advanced
+#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG
+#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0
+#endif
+
+// <q> Run in stand-by
+// <i> Keep the module running in standby sleep mode
+// <id> usart_arch_runstdby
+#ifndef CONF_SERCOM_2_USART_RUNSTDBY
+#define CONF_SERCOM_2_USART_RUNSTDBY 0
+#endif
+
+// <q> Immediate Buffer Overflow Notification
+// <i> Controls when the BUFOVF status bit is asserted
+// <id> usart_arch_ibon
+#ifndef CONF_SERCOM_2_USART_IBON
+#define CONF_SERCOM_2_USART_IBON 0
+#endif
+
+// <q> Start of Frame Detection Enable
+// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
+// <id> usart_arch_sfde
+#ifndef CONF_SERCOM_2_USART_SFDE
+#define CONF_SERCOM_2_USART_SFDE 0
+#endif
+
+// <q> Collision Detection Enable
+// <i> Collision detection enable
+// <id> usart_arch_cloden
+#ifndef CONF_SERCOM_2_USART_CLODEN
+#define CONF_SERCOM_2_USART_CLODEN 0
+#endif
+
+// <o> Operating Mode
+// <0x1=>USART with internal clock
+// <i> Drive the shift register by an internal clock generated by the baud rate generator.
+// <id> usart_arch_clock_mode
+#ifndef CONF_SERCOM_2_USART_MODE
+#define CONF_SERCOM_2_USART_MODE 0x1
+#endif
+
+// <o> Data Order
+// <0=>MSB is transmitted first
+// <1=>LSB is transmitted first
+// <i> Data order of the data bits in the frame
+// <id> usart_arch_dord
+#ifndef CONF_SERCOM_2_USART_DORD
+#define CONF_SERCOM_2_USART_DORD 1
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
+// <0=>Keep running
+// <1=>Halt
+// <id> usart_arch_dbgstop
+#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE
+#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0
+#endif
+
+// Does not do anything in USRT mode
+#define CONF_SERCOM_2_USART_SAMPR 0x0
+#define CONF_SERCOM_2_USART_SAMPA 0x0
+#define CONF_SERCOM_2_USART_FRACTIONAL 0x0
+
+// Does not do anything in UART mode
+#define CONF_SERCOM_2_USART_CPOL 0
+
+// Does not do anything in USRT mode
+#define CONF_SERCOM_2_USART_ENC 0
+
+// </e>
+
+#ifndef CONF_SERCOM_2_USART_CMODE
+#define CONF_SERCOM_2_USART_CMODE CONF_SERCOM_2_USART_ISO7816_PROTOCOL_T
+#endif
+
+/* RX is on PIN_PA09 */
+#ifndef CONF_SERCOM_2_USART_RXPO
+#define CONF_SERCOM_2_USART_RXPO 0
+#endif
+
+/* TX uses the same pin with RX */
+#ifndef CONF_SERCOM_2_USART_TXPO
+#define CONF_SERCOM_2_USART_TXPO 2
+#endif
+
+/* Set iso7816 mode */
+#define CONF_SERCOM_2_USART_PMODE (CONF_SERCOM_2_USART_PARITY - 1)
+#define CONF_SERCOM_2_USART_FORM 7
+
+#if CONF_SERCOM_2_USART_CMODE == 0
+// Calculate BAUD register value in UART mode
+#if CONF_SERCOM_2_USART_SAMPR == 0
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_2_USART_SAMPR == 1
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE                                                                                  \
+	((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
+#endif
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_2_USART_SAMPR == 2
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_2_USART_SAMPR == 3
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE                                                                                  \
+	((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)
+#endif
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_2_USART_SAMPR == 4
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+#define CONF_SERCOM_2_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#endif
+
+#elif CONF_SERCOM_2_USART_CMODE == 1
+#ifndef CONF_SERCOM_2_USART_BAUD_RATE
+// Calculate BAUD register value in USRT mode
+#define CONF_SERCOM_2_USART_BAUD_RATE (CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (2 * CONF_SERCOM_2_USART_BAUD) - 1
+#endif
+
+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#else
+#error CMODE value for SERCOM 2 in USART mode not known
+#endif
+
+#include <peripheral_clk_config.h>
+
+#ifndef CONF_SERCOM_3_USART_ENABLE
+#define CONF_SERCOM_3_USART_ENABLE 1
+#endif
+
+// <h> Basic Configuration
+
+// <q> Receive buffer enable
+// <i> Enable input buffer in SERCOM module
+// <id> usart_rx_enable
+#ifndef CONF_SERCOM_3_USART_RXEN
+#define CONF_SERCOM_3_USART_RXEN 1
+#endif
+
+// <q> Transmitt buffer enable
+// <i> Enable output buffer in SERCOM module
+// <id> usart_tx_enable
+#ifndef CONF_SERCOM_3_USART_TXEN
+#define CONF_SERCOM_3_USART_TXEN 1
+#endif
+
+// <o> Frame parity
+// <0x1=>Even parity
+// <i> Parity bit mode for USART frame
+// <id> usart_parity
+#ifndef CONF_SERCOM_3_USART_PARITY
+#define CONF_SERCOM_3_USART_PARITY 1
+#endif
+
+// <o> Character Size
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <0x5=>5 bits
+// <0x6=>6 bits
+// <0x7=>7 bits
+// <i> Data character size in USART frame
+// <id> usart_character_size
+#ifndef CONF_SERCOM_3_USART_CHSIZE
+#define CONF_SERCOM_3_USART_CHSIZE 0x0
+#endif
+
+// <o> Stop Bit
+// <0=>One stop bit
+// <1=>Two stop bits
+// <i> Number of stop bits in USART frame
+// <id> usart_stop_bit
+#ifndef CONF_SERCOM_3_USART_SBMODE
+#define CONF_SERCOM_3_USART_SBMODE 0
+#endif
+
+// <o> Baud rate <1-3000000>
+// <i> USART baud rate setting
+// <id> usart_baud_rate
+#ifndef CONF_SERCOM_3_USART_BAUD
+#define CONF_SERCOM_3_USART_BAUD 9600
+#endif
+// </h>
+
+// <h> ISO7816 configuration
+// <o> ISO7816 Protocol Type
+// <0x1=> T=0
+// <0x0=> T=1
+// <i> Define ISO7816 protocol type as 0.
+// <id> usart_iso7816_type
+#ifndef CONF_SERCOM_3_USART_ISO7816_PROTOCOL_T
+#define CONF_SERCOM_3_USART_ISO7816_PROTOCOL_T 0x1
+#endif
+
+// <o> ISO7816 Inhibit Not Acknowledge
+// <0x0=> NACK is transmitted when a parity error is received.
+// <0x1=> NACK is not transmitted when a parity error is received.
+// <i> Define whether a NACK is transmitted when a parity error is received.
+// <id> usart_inack
+#ifndef CONF_SERCOM_3_USART_INACK
+#define CONF_SERCOM_3_USART_INACK 0x0
+#endif
+
+// <o> ISO7816 Disable Successive Not Acknowledge
+// <0x0=> The successive receive NACK is disable.
+// <0x1=> The successive receive NACK is enable.
+// <i> Define whether NACK will be sent on parity error reception.
+// <id> usart_dsnack
+#ifndef CONF_SERCOM_3_USART_DSNACK
+#define CONF_SERCOM_3_USART_DSNACK 0x0
+#endif
+
+// <o> ISO7816 Maximum Iterations<0-7>
+// <i> Define the maximum number of retransmit iterations.
+// <id> usart_maxiter
+#ifndef CONF_SERCOM_3_USART_MAXITER
+#define CONF_SERCOM_3_USART_MAXITER 0x7
+#endif
+
+// <o> ISO7816 Guard Time
+// <0x2=> 2-bit times
+// <0x3=> 3-bit times
+// <0x4=> 4-bit times
+// <0x5=> 5-bit times
+// <0x6=> 6-bit times
+// <0x7=> 7-bit times
+// <i> Define the guard time.
+// <id> usart_gtime
+#ifndef CONF_SERCOM_3_USART_GTIME
+#define CONF_SERCOM_3_USART_GTIME 0x2
+#endif
+
+// <q> Inverse transmission and reception enabled
+// <i> Define inverse transmission and reception enabled.
+// <id> usart_inverse_enabled
+#ifndef CONF_SERCOM_3_USART_INVERSE_ENABLED
+#define CONF_SERCOM_3_USART_INVERSE_ENABLED 0x0
+#endif
+
+#if (CONF_SERCOM_3_USART_INVERSE_ENABLED == 1)
+#define CONF_SERCOM_3_USART_RXINV 0x1
+#define CONF_SERCOM_3_USART_TXINV 0x1
+#else
+#define CONF_SERCOM_3_USART_RXINV 0x0
+#define CONF_SERCOM_3_USART_TXINV 0x0
+#endif
+
+// </h>
+
+// <e> Advanced configuration
+// <id> usart_advanced
+#ifndef CONF_SERCOM_3_USART_ADVANCED_CONFIG
+#define CONF_SERCOM_3_USART_ADVANCED_CONFIG 0
+#endif
+
+// <q> Run in stand-by
+// <i> Keep the module running in standby sleep mode
+// <id> usart_arch_runstdby
+#ifndef CONF_SERCOM_3_USART_RUNSTDBY
+#define CONF_SERCOM_3_USART_RUNSTDBY 0
+#endif
+
+// <q> Immediate Buffer Overflow Notification
+// <i> Controls when the BUFOVF status bit is asserted
+// <id> usart_arch_ibon
+#ifndef CONF_SERCOM_3_USART_IBON
+#define CONF_SERCOM_3_USART_IBON 0
+#endif
+
+// <q> Start of Frame Detection Enable
+// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
+// <id> usart_arch_sfde
+#ifndef CONF_SERCOM_3_USART_SFDE
+#define CONF_SERCOM_3_USART_SFDE 0
+#endif
+
+// <q> Collision Detection Enable
+// <i> Collision detection enable
+// <id> usart_arch_cloden
+#ifndef CONF_SERCOM_3_USART_CLODEN
+#define CONF_SERCOM_3_USART_CLODEN 0
+#endif
+
+// <o> Operating Mode
+// <0x1=>USART with internal clock
+// <i> Drive the shift register by an internal clock generated by the baud rate generator.
+// <id> usart_arch_clock_mode
+#ifndef CONF_SERCOM_3_USART_MODE
+#define CONF_SERCOM_3_USART_MODE 0x1
+#endif
+
+// <o> Data Order
+// <0=>MSB is transmitted first
+// <1=>LSB is transmitted first
+// <i> Data order of the data bits in the frame
+// <id> usart_arch_dord
+#ifndef CONF_SERCOM_3_USART_DORD
+#define CONF_SERCOM_3_USART_DORD 1
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
+// <0=>Keep running
+// <1=>Halt
+// <id> usart_arch_dbgstop
+#ifndef CONF_SERCOM_3_USART_DEBUG_STOP_MODE
+#define CONF_SERCOM_3_USART_DEBUG_STOP_MODE 0
+#endif
+
+// Does not do anything in USRT mode
+#define CONF_SERCOM_3_USART_SAMPR 0x0
+#define CONF_SERCOM_3_USART_SAMPA 0x0
+#define CONF_SERCOM_3_USART_FRACTIONAL 0x0
+
+// Does not do anything in UART mode
+#define CONF_SERCOM_3_USART_CPOL 0
+
+// Does not do anything in USRT mode
+#define CONF_SERCOM_3_USART_ENC 0
+
+// </e>
+
+#ifndef CONF_SERCOM_3_USART_CMODE
+#define CONF_SERCOM_3_USART_CMODE CONF_SERCOM_3_USART_ISO7816_PROTOCOL_T
+#endif
+
+/* RX is on PIN_PB20 */
+#ifndef CONF_SERCOM_3_USART_RXPO
+#define CONF_SERCOM_3_USART_RXPO 0
+#endif
+
+/* TX uses the same pin with RX */
+#ifndef CONF_SERCOM_3_USART_TXPO
+#define CONF_SERCOM_3_USART_TXPO 2
+#endif
+
+/* Set iso7816 mode */
+#define CONF_SERCOM_3_USART_PMODE (CONF_SERCOM_3_USART_PARITY - 1)
+#define CONF_SERCOM_3_USART_FORM 7
+
+#if CONF_SERCOM_3_USART_CMODE == 0
+// Calculate BAUD register value in UART mode
+#if CONF_SERCOM_3_USART_SAMPR == 0
+#ifndef CONF_SERCOM_3_USART_BAUD_RATE
+#define CONF_SERCOM_3_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 16.0f * CONF_SERCOM_3_USART_BAUD) / CONF_GCLK_SERCOM3_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_3_USART_SAMPR == 1
+#ifndef CONF_SERCOM_3_USART_BAUD_RATE
+#define CONF_SERCOM_3_USART_BAUD_RATE                                                                                  \
+	((CONF_GCLK_SERCOM3_CORE_FREQUENCY) / (CONF_SERCOM_3_USART_BAUD * 16)) - (CONF_SERCOM_3_USART_FRACTIONAL / 8)
+#endif
+#ifndef CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_3_USART_SAMPR == 2
+#ifndef CONF_SERCOM_3_USART_BAUD_RATE
+#define CONF_SERCOM_3_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 8.0f * CONF_SERCOM_3_USART_BAUD) / CONF_GCLK_SERCOM3_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_3_USART_SAMPR == 3
+#ifndef CONF_SERCOM_3_USART_BAUD_RATE
+#define CONF_SERCOM_3_USART_BAUD_RATE                                                                                  \
+	((CONF_GCLK_SERCOM3_CORE_FREQUENCY) / (CONF_SERCOM_3_USART_BAUD * 8)) - (CONF_SERCOM_3_USART_FRACTIONAL / 8)
+#endif
+#ifndef CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_3_USART_SAMPR == 4
+#ifndef CONF_SERCOM_3_USART_BAUD_RATE
+#define CONF_SERCOM_3_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 3.0f * CONF_SERCOM_3_USART_BAUD) / CONF_GCLK_SERCOM3_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#endif
+
+#elif CONF_SERCOM_3_USART_CMODE == 1
+#ifndef CONF_SERCOM_3_USART_BAUD_RATE
+// Calculate BAUD register value in USRT mode
+#define CONF_SERCOM_3_USART_BAUD_RATE (CONF_GCLK_SERCOM3_CORE_FREQUENCY) / (2 * CONF_SERCOM_3_USART_BAUD) - 1
+#endif
+
+#ifndef CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#else
+#error CMODE value for SERCOM 3 in USART mode not known
+#endif
+
+#include <peripheral_clk_config.h>
+
+#ifndef CONF_SERCOM_4_USART_ENABLE
+#define CONF_SERCOM_4_USART_ENABLE 1
+#endif
+
+// <h> Basic Configuration
+
+// <q> Receive buffer enable
+// <i> Enable input buffer in SERCOM module
+// <id> usart_rx_enable
+#ifndef CONF_SERCOM_4_USART_RXEN
+#define CONF_SERCOM_4_USART_RXEN 1
+#endif
+
+// <q> Transmitt buffer enable
+// <i> Enable output buffer in SERCOM module
+// <id> usart_tx_enable
+#ifndef CONF_SERCOM_4_USART_TXEN
+#define CONF_SERCOM_4_USART_TXEN 1
+#endif
+
+// <o> Frame parity
+// <0x1=>Even parity
+// <i> Parity bit mode for USART frame
+// <id> usart_parity
+#ifndef CONF_SERCOM_4_USART_PARITY
+#define CONF_SERCOM_4_USART_PARITY 1
+#endif
+
+// <o> Character Size
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <0x5=>5 bits
+// <0x6=>6 bits
+// <0x7=>7 bits
+// <i> Data character size in USART frame
+// <id> usart_character_size
+#ifndef CONF_SERCOM_4_USART_CHSIZE
+#define CONF_SERCOM_4_USART_CHSIZE 0x0
+#endif
+
+// <o> Stop Bit
+// <0=>One stop bit
+// <1=>Two stop bits
+// <i> Number of stop bits in USART frame
+// <id> usart_stop_bit
+#ifndef CONF_SERCOM_4_USART_SBMODE
+#define CONF_SERCOM_4_USART_SBMODE 0
+#endif
+
+// <o> Baud rate <1-3000000>
+// <i> USART baud rate setting
+// <id> usart_baud_rate
+#ifndef CONF_SERCOM_4_USART_BAUD
+#define CONF_SERCOM_4_USART_BAUD 9600
+#endif
+// </h>
+
+// <h> ISO7816 configuration
+// <o> ISO7816 Protocol Type
+// <0x1=> T=0
+// <0x0=> T=1
+// <i> Define ISO7816 protocol type as 0.
+// <id> usart_iso7816_type
+#ifndef CONF_SERCOM_4_USART_ISO7816_PROTOCOL_T
+#define CONF_SERCOM_4_USART_ISO7816_PROTOCOL_T 0x1
+#endif
+
+// <o> ISO7816 Inhibit Not Acknowledge
+// <0x0=> NACK is transmitted when a parity error is received.
+// <0x1=> NACK is not transmitted when a parity error is received.
+// <i> Define whether a NACK is transmitted when a parity error is received.
+// <id> usart_inack
+#ifndef CONF_SERCOM_4_USART_INACK
+#define CONF_SERCOM_4_USART_INACK 0x0
+#endif
+
+// <o> ISO7816 Disable Successive Not Acknowledge
+// <0x0=> The successive receive NACK is disable.
+// <0x1=> The successive receive NACK is enable.
+// <i> Define whether NACK will be sent on parity error reception.
+// <id> usart_dsnack
+#ifndef CONF_SERCOM_4_USART_DSNACK
+#define CONF_SERCOM_4_USART_DSNACK 0x0
+#endif
+
+// <o> ISO7816 Maximum Iterations<0-7>
+// <i> Define the maximum number of retransmit iterations.
+// <id> usart_maxiter
+#ifndef CONF_SERCOM_4_USART_MAXITER
+#define CONF_SERCOM_4_USART_MAXITER 0x7
+#endif
+
+// <o> ISO7816 Guard Time
+// <0x2=> 2-bit times
+// <0x3=> 3-bit times
+// <0x4=> 4-bit times
+// <0x5=> 5-bit times
+// <0x6=> 6-bit times
+// <0x7=> 7-bit times
+// <i> Define the guard time.
+// <id> usart_gtime
+#ifndef CONF_SERCOM_4_USART_GTIME
+#define CONF_SERCOM_4_USART_GTIME 0x2
+#endif
+
+// <q> Inverse transmission and reception enabled
+// <i> Define inverse transmission and reception enabled.
+// <id> usart_inverse_enabled
+#ifndef CONF_SERCOM_4_USART_INVERSE_ENABLED
+#define CONF_SERCOM_4_USART_INVERSE_ENABLED 0x0
+#endif
+
+#if (CONF_SERCOM_4_USART_INVERSE_ENABLED == 1)
+#define CONF_SERCOM_4_USART_RXINV 0x1
+#define CONF_SERCOM_4_USART_TXINV 0x1
+#else
+#define CONF_SERCOM_4_USART_RXINV 0x0
+#define CONF_SERCOM_4_USART_TXINV 0x0
+#endif
+
+// </h>
+
+// <e> Advanced configuration
+// <id> usart_advanced
+#ifndef CONF_SERCOM_4_USART_ADVANCED_CONFIG
+#define CONF_SERCOM_4_USART_ADVANCED_CONFIG 0
+#endif
+
+// <q> Run in stand-by
+// <i> Keep the module running in standby sleep mode
+// <id> usart_arch_runstdby
+#ifndef CONF_SERCOM_4_USART_RUNSTDBY
+#define CONF_SERCOM_4_USART_RUNSTDBY 0
+#endif
+
+// <q> Immediate Buffer Overflow Notification
+// <i> Controls when the BUFOVF status bit is asserted
+// <id> usart_arch_ibon
+#ifndef CONF_SERCOM_4_USART_IBON
+#define CONF_SERCOM_4_USART_IBON 0
+#endif
+
+// <q> Start of Frame Detection Enable
+// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
+// <id> usart_arch_sfde
+#ifndef CONF_SERCOM_4_USART_SFDE
+#define CONF_SERCOM_4_USART_SFDE 0
+#endif
+
+// <q> Collision Detection Enable
+// <i> Collision detection enable
+// <id> usart_arch_cloden
+#ifndef CONF_SERCOM_4_USART_CLODEN
+#define CONF_SERCOM_4_USART_CLODEN 0
+#endif
+
+// <o> Operating Mode
+// <0x1=>USART with internal clock
+// <i> Drive the shift register by an internal clock generated by the baud rate generator.
+// <id> usart_arch_clock_mode
+#ifndef CONF_SERCOM_4_USART_MODE
+#define CONF_SERCOM_4_USART_MODE 0x1
+#endif
+
+// <o> Data Order
+// <0=>MSB is transmitted first
+// <1=>LSB is transmitted first
+// <i> Data order of the data bits in the frame
+// <id> usart_arch_dord
+#ifndef CONF_SERCOM_4_USART_DORD
+#define CONF_SERCOM_4_USART_DORD 1
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
+// <0=>Keep running
+// <1=>Halt
+// <id> usart_arch_dbgstop
+#ifndef CONF_SERCOM_4_USART_DEBUG_STOP_MODE
+#define CONF_SERCOM_4_USART_DEBUG_STOP_MODE 0
+#endif
+
+// Does not do anything in USRT mode
+#define CONF_SERCOM_4_USART_SAMPR 0x0
+#define CONF_SERCOM_4_USART_SAMPA 0x0
+#define CONF_SERCOM_4_USART_FRACTIONAL 0x0
+
+// Does not do anything in UART mode
+#define CONF_SERCOM_4_USART_CPOL 0
+
+// Does not do anything in USRT mode
+#define CONF_SERCOM_4_USART_ENC 0
+
+// </e>
+
+#ifndef CONF_SERCOM_4_USART_CMODE
+#define CONF_SERCOM_4_USART_CMODE CONF_SERCOM_4_USART_ISO7816_PROTOCOL_T
+#endif
+
+/* RX is on PIN_PB08 */
+#ifndef CONF_SERCOM_4_USART_RXPO
+#define CONF_SERCOM_4_USART_RXPO 0
+#endif
+
+/* TX uses the same pin with RX */
+#ifndef CONF_SERCOM_4_USART_TXPO
+#define CONF_SERCOM_4_USART_TXPO 2
+#endif
+
+/* Set iso7816 mode */
+#define CONF_SERCOM_4_USART_PMODE (CONF_SERCOM_4_USART_PARITY - 1)
+#define CONF_SERCOM_4_USART_FORM 7
+
+#if CONF_SERCOM_4_USART_CMODE == 0
+// Calculate BAUD register value in UART mode
+#if CONF_SERCOM_4_USART_SAMPR == 0
+#ifndef CONF_SERCOM_4_USART_BAUD_RATE
+#define CONF_SERCOM_4_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 16.0f * CONF_SERCOM_4_USART_BAUD) / CONF_GCLK_SERCOM4_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_4_USART_SAMPR == 1
+#ifndef CONF_SERCOM_4_USART_BAUD_RATE
+#define CONF_SERCOM_4_USART_BAUD_RATE                                                                                  \
+	((CONF_GCLK_SERCOM4_CORE_FREQUENCY) / (CONF_SERCOM_4_USART_BAUD * 16)) - (CONF_SERCOM_4_USART_FRACTIONAL / 8)
+#endif
+#ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_4_USART_SAMPR == 2
+#ifndef CONF_SERCOM_4_USART_BAUD_RATE
+#define CONF_SERCOM_4_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 8.0f * CONF_SERCOM_4_USART_BAUD) / CONF_GCLK_SERCOM4_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_4_USART_SAMPR == 3
+#ifndef CONF_SERCOM_4_USART_BAUD_RATE
+#define CONF_SERCOM_4_USART_BAUD_RATE                                                                                  \
+	((CONF_GCLK_SERCOM4_CORE_FREQUENCY) / (CONF_SERCOM_4_USART_BAUD * 8)) - (CONF_SERCOM_4_USART_FRACTIONAL / 8)
+#endif
+#ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_4_USART_SAMPR == 4
+#ifndef CONF_SERCOM_4_USART_BAUD_RATE
+#define CONF_SERCOM_4_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 3.0f * CONF_SERCOM_4_USART_BAUD) / CONF_GCLK_SERCOM4_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#endif
+
+#elif CONF_SERCOM_4_USART_CMODE == 1
+#ifndef CONF_SERCOM_4_USART_BAUD_RATE
+// Calculate BAUD register value in USRT mode
+#define CONF_SERCOM_4_USART_BAUD_RATE (CONF_GCLK_SERCOM4_CORE_FREQUENCY) / (2 * CONF_SERCOM_4_USART_BAUD) - 1
+#endif
+
+#ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#else
+#error CMODE value for SERCOM 4 in USART mode not known
+#endif
+
+#include <peripheral_clk_config.h>
+
+#ifndef CONF_SERCOM_5_USART_ENABLE
+#define CONF_SERCOM_5_USART_ENABLE 1
+#endif
+
+// <h> Basic Configuration
+
+// <q> Receive buffer enable
+// <i> Enable input buffer in SERCOM module
+// <id> usart_rx_enable
+#ifndef CONF_SERCOM_5_USART_RXEN
+#define CONF_SERCOM_5_USART_RXEN 1
+#endif
+
+// <q> Transmitt buffer enable
+// <i> Enable output buffer in SERCOM module
+// <id> usart_tx_enable
+#ifndef CONF_SERCOM_5_USART_TXEN
+#define CONF_SERCOM_5_USART_TXEN 1
+#endif
+
+// <o> Frame parity
+// <0x1=>Even parity
+// <i> Parity bit mode for USART frame
+// <id> usart_parity
+#ifndef CONF_SERCOM_5_USART_PARITY
+#define CONF_SERCOM_5_USART_PARITY 1
+#endif
+
+// <o> Character Size
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <0x5=>5 bits
+// <0x6=>6 bits
+// <0x7=>7 bits
+// <i> Data character size in USART frame
+// <id> usart_character_size
+#ifndef CONF_SERCOM_5_USART_CHSIZE
+#define CONF_SERCOM_5_USART_CHSIZE 0x0
+#endif
+
+// <o> Stop Bit
+// <0=>One stop bit
+// <1=>Two stop bits
+// <i> Number of stop bits in USART frame
+// <id> usart_stop_bit
+#ifndef CONF_SERCOM_5_USART_SBMODE
+#define CONF_SERCOM_5_USART_SBMODE 0
+#endif
+
+// <o> Baud rate <1-3000000>
+// <i> USART baud rate setting
+// <id> usart_baud_rate
+#ifndef CONF_SERCOM_5_USART_BAUD
+#define CONF_SERCOM_5_USART_BAUD 9600
+#endif
+// </h>
+
+// <h> ISO7816 configuration
+// <o> ISO7816 Protocol Type
+// <0x1=> T=0
+// <0x0=> T=1
+// <i> Define ISO7816 protocol type as 0.
+// <id> usart_iso7816_type
+#ifndef CONF_SERCOM_5_USART_ISO7816_PROTOCOL_T
+#define CONF_SERCOM_5_USART_ISO7816_PROTOCOL_T 0x1
+#endif
+
+// <o> ISO7816 Inhibit Not Acknowledge
+// <0x0=> NACK is transmitted when a parity error is received.
+// <0x1=> NACK is not transmitted when a parity error is received.
+// <i> Define whether a NACK is transmitted when a parity error is received.
+// <id> usart_inack
+#ifndef CONF_SERCOM_5_USART_INACK
+#define CONF_SERCOM_5_USART_INACK 0x0
+#endif
+
+// <o> ISO7816 Disable Successive Not Acknowledge
+// <0x0=> The successive receive NACK is disable.
+// <0x1=> The successive receive NACK is enable.
+// <i> Define whether NACK will be sent on parity error reception.
+// <id> usart_dsnack
+#ifndef CONF_SERCOM_5_USART_DSNACK
+#define CONF_SERCOM_5_USART_DSNACK 0x0
+#endif
+
+// <o> ISO7816 Maximum Iterations<0-7>
+// <i> Define the maximum number of retransmit iterations.
+// <id> usart_maxiter
+#ifndef CONF_SERCOM_5_USART_MAXITER
+#define CONF_SERCOM_5_USART_MAXITER 0x7
+#endif
+
+// <o> ISO7816 Guard Time
+// <0x2=> 2-bit times
+// <0x3=> 3-bit times
+// <0x4=> 4-bit times
+// <0x5=> 5-bit times
+// <0x6=> 6-bit times
+// <0x7=> 7-bit times
+// <i> Define the guard time.
+// <id> usart_gtime
+#ifndef CONF_SERCOM_5_USART_GTIME
+#define CONF_SERCOM_5_USART_GTIME 0x2
+#endif
+
+// <q> Inverse transmission and reception enabled
+// <i> Define inverse transmission and reception enabled.
+// <id> usart_inverse_enabled
+#ifndef CONF_SERCOM_5_USART_INVERSE_ENABLED
+#define CONF_SERCOM_5_USART_INVERSE_ENABLED 0x0
+#endif
+
+#if (CONF_SERCOM_5_USART_INVERSE_ENABLED == 1)
+#define CONF_SERCOM_5_USART_RXINV 0x1
+#define CONF_SERCOM_5_USART_TXINV 0x1
+#else
+#define CONF_SERCOM_5_USART_RXINV 0x0
+#define CONF_SERCOM_5_USART_TXINV 0x0
+#endif
+
+// </h>
+
+// <e> Advanced configuration
+// <id> usart_advanced
+#ifndef CONF_SERCOM_5_USART_ADVANCED_CONFIG
+#define CONF_SERCOM_5_USART_ADVANCED_CONFIG 0
+#endif
+
+// <q> Run in stand-by
+// <i> Keep the module running in standby sleep mode
+// <id> usart_arch_runstdby
+#ifndef CONF_SERCOM_5_USART_RUNSTDBY
+#define CONF_SERCOM_5_USART_RUNSTDBY 0
+#endif
+
+// <q> Immediate Buffer Overflow Notification
+// <i> Controls when the BUFOVF status bit is asserted
+// <id> usart_arch_ibon
+#ifndef CONF_SERCOM_5_USART_IBON
+#define CONF_SERCOM_5_USART_IBON 0
+#endif
+
+// <q> Start of Frame Detection Enable
+// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
+// <id> usart_arch_sfde
+#ifndef CONF_SERCOM_5_USART_SFDE
+#define CONF_SERCOM_5_USART_SFDE 0
+#endif
+
+// <q> Collision Detection Enable
+// <i> Collision detection enable
+// <id> usart_arch_cloden
+#ifndef CONF_SERCOM_5_USART_CLODEN
+#define CONF_SERCOM_5_USART_CLODEN 0
+#endif
+
+// <o> Operating Mode
+// <0x1=>USART with internal clock
+// <i> Drive the shift register by an internal clock generated by the baud rate generator.
+// <id> usart_arch_clock_mode
+#ifndef CONF_SERCOM_5_USART_MODE
+#define CONF_SERCOM_5_USART_MODE 0x1
+#endif
+
+// <o> Data Order
+// <0=>MSB is transmitted first
+// <1=>LSB is transmitted first
+// <i> Data order of the data bits in the frame
+// <id> usart_arch_dord
+#ifndef CONF_SERCOM_5_USART_DORD
+#define CONF_SERCOM_5_USART_DORD 1
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
+// <0=>Keep running
+// <1=>Halt
+// <id> usart_arch_dbgstop
+#ifndef CONF_SERCOM_5_USART_DEBUG_STOP_MODE
+#define CONF_SERCOM_5_USART_DEBUG_STOP_MODE 0
+#endif
+
+// Does not do anything in USRT mode
+#define CONF_SERCOM_5_USART_SAMPR 0x0
+#define CONF_SERCOM_5_USART_SAMPA 0x0
+#define CONF_SERCOM_5_USART_FRACTIONAL 0x0
+
+// Does not do anything in UART mode
+#define CONF_SERCOM_5_USART_CPOL 0
+
+// Does not do anything in USRT mode
+#define CONF_SERCOM_5_USART_ENC 0
+
+// </e>
+
+#ifndef CONF_SERCOM_5_USART_CMODE
+#define CONF_SERCOM_5_USART_CMODE CONF_SERCOM_5_USART_ISO7816_PROTOCOL_T
+#endif
+
+/* RX is on PIN_PB16 */
+#ifndef CONF_SERCOM_5_USART_RXPO
+#define CONF_SERCOM_5_USART_RXPO 0
+#endif
+
+/* TX uses the same pin with RX */
+#ifndef CONF_SERCOM_5_USART_TXPO
+#define CONF_SERCOM_5_USART_TXPO 2
+#endif
+
+/* Set iso7816 mode */
+#define CONF_SERCOM_5_USART_PMODE (CONF_SERCOM_5_USART_PARITY - 1)
+#define CONF_SERCOM_5_USART_FORM 7
+
+#if CONF_SERCOM_5_USART_CMODE == 0
+// Calculate BAUD register value in UART mode
+#if CONF_SERCOM_5_USART_SAMPR == 0
+#ifndef CONF_SERCOM_5_USART_BAUD_RATE
+#define CONF_SERCOM_5_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 16.0f * CONF_SERCOM_5_USART_BAUD) / CONF_GCLK_SERCOM5_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_5_USART_SAMPR == 1
+#ifndef CONF_SERCOM_5_USART_BAUD_RATE
+#define CONF_SERCOM_5_USART_BAUD_RATE                                                                                  \
+	((CONF_GCLK_SERCOM5_CORE_FREQUENCY) / (CONF_SERCOM_5_USART_BAUD * 16)) - (CONF_SERCOM_5_USART_FRACTIONAL / 8)
+#endif
+#ifndef CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_5_USART_SAMPR == 2
+#ifndef CONF_SERCOM_5_USART_BAUD_RATE
+#define CONF_SERCOM_5_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 8.0f * CONF_SERCOM_5_USART_BAUD) / CONF_GCLK_SERCOM5_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_5_USART_SAMPR == 3
+#ifndef CONF_SERCOM_5_USART_BAUD_RATE
+#define CONF_SERCOM_5_USART_BAUD_RATE                                                                                  \
+	((CONF_GCLK_SERCOM5_CORE_FREQUENCY) / (CONF_SERCOM_5_USART_BAUD * 8)) - (CONF_SERCOM_5_USART_FRACTIONAL / 8)
+#endif
+#ifndef CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_5_USART_SAMPR == 4
+#ifndef CONF_SERCOM_5_USART_BAUD_RATE
+#define CONF_SERCOM_5_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 3.0f * CONF_SERCOM_5_USART_BAUD) / CONF_GCLK_SERCOM5_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#endif
+
+#elif CONF_SERCOM_5_USART_CMODE == 1
+#ifndef CONF_SERCOM_5_USART_BAUD_RATE
+// Calculate BAUD register value in USRT mode
+#define CONF_SERCOM_5_USART_BAUD_RATE (CONF_GCLK_SERCOM5_CORE_FREQUENCY) / (2 * CONF_SERCOM_5_USART_BAUD) - 1
+#endif
+
+#ifndef CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#else
+#error CMODE value for SERCOM 5 in USART mode not known
+#endif
+
+#include <peripheral_clk_config.h>
+
+#ifndef CONF_SERCOM_6_USART_ENABLE
+#define CONF_SERCOM_6_USART_ENABLE 1
+#endif
+
+// <h> Basic Configuration
+
+// <q> Receive buffer enable
+// <i> Enable input buffer in SERCOM module
+// <id> usart_rx_enable
+#ifndef CONF_SERCOM_6_USART_RXEN
+#define CONF_SERCOM_6_USART_RXEN 1
+#endif
+
+// <q> Transmitt buffer enable
+// <i> Enable output buffer in SERCOM module
+// <id> usart_tx_enable
+#ifndef CONF_SERCOM_6_USART_TXEN
+#define CONF_SERCOM_6_USART_TXEN 1
+#endif
+
+// <o> Frame parity
+// <0x1=>Even parity
+// <i> Parity bit mode for USART frame
+// <id> usart_parity
+#ifndef CONF_SERCOM_6_USART_PARITY
+#define CONF_SERCOM_6_USART_PARITY 1
+#endif
+
+// <o> Character Size
+// <0x0=>8 bits
+// <0x1=>9 bits
+// <0x5=>5 bits
+// <0x6=>6 bits
+// <0x7=>7 bits
+// <i> Data character size in USART frame
+// <id> usart_character_size
+#ifndef CONF_SERCOM_6_USART_CHSIZE
+#define CONF_SERCOM_6_USART_CHSIZE 0x0
+#endif
+
+// <o> Stop Bit
+// <0=>One stop bit
+// <1=>Two stop bits
+// <i> Number of stop bits in USART frame
+// <id> usart_stop_bit
+#ifndef CONF_SERCOM_6_USART_SBMODE
+#define CONF_SERCOM_6_USART_SBMODE 0
+#endif
+
+// <o> Baud rate <1-3000000>
+// <i> USART baud rate setting
+// <id> usart_baud_rate
+#ifndef CONF_SERCOM_6_USART_BAUD
+#define CONF_SERCOM_6_USART_BAUD 9600
+#endif
+// </h>
+
+// <h> ISO7816 configuration
+// <o> ISO7816 Protocol Type
+// <0x1=> T=0
+// <0x0=> T=1
+// <i> Define ISO7816 protocol type as 0.
+// <id> usart_iso7816_type
+#ifndef CONF_SERCOM_6_USART_ISO7816_PROTOCOL_T
+#define CONF_SERCOM_6_USART_ISO7816_PROTOCOL_T 0x1
+#endif
+
+// <o> ISO7816 Inhibit Not Acknowledge
+// <0x0=> NACK is transmitted when a parity error is received.
+// <0x1=> NACK is not transmitted when a parity error is received.
+// <i> Define whether a NACK is transmitted when a parity error is received.
+// <id> usart_inack
+#ifndef CONF_SERCOM_6_USART_INACK
+#define CONF_SERCOM_6_USART_INACK 0x0
+#endif
+
+// <o> ISO7816 Disable Successive Not Acknowledge
+// <0x0=> The successive receive NACK is disable.
+// <0x1=> The successive receive NACK is enable.
+// <i> Define whether NACK will be sent on parity error reception.
+// <id> usart_dsnack
+#ifndef CONF_SERCOM_6_USART_DSNACK
+#define CONF_SERCOM_6_USART_DSNACK 0x0
+#endif
+
+// <o> ISO7816 Maximum Iterations<0-7>
+// <i> Define the maximum number of retransmit iterations.
+// <id> usart_maxiter
+#ifndef CONF_SERCOM_6_USART_MAXITER
+#define CONF_SERCOM_6_USART_MAXITER 0x7
+#endif
+
+// <o> ISO7816 Guard Time
+// <0x2=> 2-bit times
+// <0x3=> 3-bit times
+// <0x4=> 4-bit times
+// <0x5=> 5-bit times
+// <0x6=> 6-bit times
+// <0x7=> 7-bit times
+// <i> Define the guard time.
+// <id> usart_gtime
+#ifndef CONF_SERCOM_6_USART_GTIME
+#define CONF_SERCOM_6_USART_GTIME 0x2
+#endif
+
+// <q> Inverse transmission and reception enabled
+// <i> Define inverse transmission and reception enabled.
+// <id> usart_inverse_enabled
+#ifndef CONF_SERCOM_6_USART_INVERSE_ENABLED
+#define CONF_SERCOM_6_USART_INVERSE_ENABLED 0x0
+#endif
+
+#if (CONF_SERCOM_6_USART_INVERSE_ENABLED == 1)
+#define CONF_SERCOM_6_USART_RXINV 0x1
+#define CONF_SERCOM_6_USART_TXINV 0x1
+#else
+#define CONF_SERCOM_6_USART_RXINV 0x0
+#define CONF_SERCOM_6_USART_TXINV 0x0
+#endif
+
+// </h>
+
+// <e> Advanced configuration
+// <id> usart_advanced
+#ifndef CONF_SERCOM_6_USART_ADVANCED_CONFIG
+#define CONF_SERCOM_6_USART_ADVANCED_CONFIG 0
+#endif
+
+// <q> Run in stand-by
+// <i> Keep the module running in standby sleep mode
+// <id> usart_arch_runstdby
+#ifndef CONF_SERCOM_6_USART_RUNSTDBY
+#define CONF_SERCOM_6_USART_RUNSTDBY 0
+#endif
+
+// <q> Immediate Buffer Overflow Notification
+// <i> Controls when the BUFOVF status bit is asserted
+// <id> usart_arch_ibon
+#ifndef CONF_SERCOM_6_USART_IBON
+#define CONF_SERCOM_6_USART_IBON 0
+#endif
+
+// <q> Start of Frame Detection Enable
+// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)
+// <id> usart_arch_sfde
+#ifndef CONF_SERCOM_6_USART_SFDE
+#define CONF_SERCOM_6_USART_SFDE 0
+#endif
+
+// <q> Collision Detection Enable
+// <i> Collision detection enable
+// <id> usart_arch_cloden
+#ifndef CONF_SERCOM_6_USART_CLODEN
+#define CONF_SERCOM_6_USART_CLODEN 0
+#endif
+
+// <o> Operating Mode
+// <0x1=>USART with internal clock
+// <i> Drive the shift register by an internal clock generated by the baud rate generator.
+// <id> usart_arch_clock_mode
+#ifndef CONF_SERCOM_6_USART_MODE
+#define CONF_SERCOM_6_USART_MODE 0x1
+#endif
+
+// <o> Data Order
+// <0=>MSB is transmitted first
+// <1=>LSB is transmitted first
+// <i> Data order of the data bits in the frame
+// <id> usart_arch_dord
+#ifndef CONF_SERCOM_6_USART_DORD
+#define CONF_SERCOM_6_USART_DORD 1
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
+// <0=>Keep running
+// <1=>Halt
+// <id> usart_arch_dbgstop
+#ifndef CONF_SERCOM_6_USART_DEBUG_STOP_MODE
+#define CONF_SERCOM_6_USART_DEBUG_STOP_MODE 0
+#endif
+
+// Does not do anything in USRT mode
+#define CONF_SERCOM_6_USART_SAMPR 0x0
+#define CONF_SERCOM_6_USART_SAMPA 0x0
+#define CONF_SERCOM_6_USART_FRACTIONAL 0x0
+
+// Does not do anything in UART mode
+#define CONF_SERCOM_6_USART_CPOL 0
+
+// Does not do anything in USRT mode
+#define CONF_SERCOM_6_USART_ENC 0
+
+// </e>
+
+#ifndef CONF_SERCOM_6_USART_CMODE
+#define CONF_SERCOM_6_USART_CMODE CONF_SERCOM_6_USART_ISO7816_PROTOCOL_T
+#endif
+
+/* RX is on PIN_PC16 */
+#ifndef CONF_SERCOM_6_USART_RXPO
+#define CONF_SERCOM_6_USART_RXPO 0
+#endif
+
+/* TX uses the same pin with RX */
+#ifndef CONF_SERCOM_6_USART_TXPO
+#define CONF_SERCOM_6_USART_TXPO 2
+#endif
+
+/* Set iso7816 mode */
+#define CONF_SERCOM_6_USART_PMODE (CONF_SERCOM_6_USART_PARITY - 1)
+#define CONF_SERCOM_6_USART_FORM 7
+
+#if CONF_SERCOM_6_USART_CMODE == 0
+// Calculate BAUD register value in UART mode
+#if CONF_SERCOM_6_USART_SAMPR == 0
+#ifndef CONF_SERCOM_6_USART_BAUD_RATE
+#define CONF_SERCOM_6_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 16.0f * CONF_SERCOM_6_USART_BAUD) / CONF_GCLK_SERCOM6_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_6_USART_SAMPR == 1
+#ifndef CONF_SERCOM_6_USART_BAUD_RATE
+#define CONF_SERCOM_6_USART_BAUD_RATE                                                                                  \
+	((CONF_GCLK_SERCOM6_CORE_FREQUENCY) / (CONF_SERCOM_6_USART_BAUD * 16)) - (CONF_SERCOM_6_USART_FRACTIONAL / 8)
+#endif
+#ifndef CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_6_USART_SAMPR == 2
+#ifndef CONF_SERCOM_6_USART_BAUD_RATE
+#define CONF_SERCOM_6_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 8.0f * CONF_SERCOM_6_USART_BAUD) / CONF_GCLK_SERCOM6_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_6_USART_SAMPR == 3
+#ifndef CONF_SERCOM_6_USART_BAUD_RATE
+#define CONF_SERCOM_6_USART_BAUD_RATE                                                                                  \
+	((CONF_GCLK_SERCOM6_CORE_FREQUENCY) / (CONF_SERCOM_6_USART_BAUD * 8)) - (CONF_SERCOM_6_USART_FRACTIONAL / 8)
+#endif
+#ifndef CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#elif CONF_SERCOM_6_USART_SAMPR == 4
+#ifndef CONF_SERCOM_6_USART_BAUD_RATE
+#define CONF_SERCOM_6_USART_BAUD_RATE                                                                                  \
+	65536 - ((65536 * 3.0f * CONF_SERCOM_6_USART_BAUD) / CONF_GCLK_SERCOM6_CORE_FREQUENCY)
+#endif
+#ifndef CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#endif
+
+#elif CONF_SERCOM_6_USART_CMODE == 1
+#ifndef CONF_SERCOM_6_USART_BAUD_RATE
+// Calculate BAUD register value in USRT mode
+#define CONF_SERCOM_6_USART_BAUD_RATE (CONF_GCLK_SERCOM6_CORE_FREQUENCY) / (2 * CONF_SERCOM_6_USART_BAUD) - 1
+#endif
+
+#ifndef CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH
+#define CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH 0
+#endif
+#else
+#error CMODE value for SERCOM 6 in USART mode not known
+#endif
+
+#include <peripheral_clk_config.h>
+
 #ifndef CONF_SERCOM_7_USART_ENABLE
 #define CONF_SERCOM_7_USART_ENABLE 1
 #endif
diff --git a/sysmoOCTSIM/config/peripheral_clk_config.h b/sysmoOCTSIM/config/peripheral_clk_config.h
index ce68abd..91c5c86 100644
--- a/sysmoOCTSIM/config/peripheral_clk_config.h
+++ b/sysmoOCTSIM/config/peripheral_clk_config.h
@@ -40,6 +40,566 @@
 // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
 
 // <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM0_CORE_SRC
+#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM0_SLOW_SRC
+#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY
+ * \brief SERCOM0's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 100000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY
+ * \brief SERCOM0's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768
+#endif
+
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM1_CORE_SRC
+#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM1_SLOW_SRC
+#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY
+ * \brief SERCOM1's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 100000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY
+ * \brief SERCOM1's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768
+#endif
+
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM2_CORE_SRC
+#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM2_SLOW_SRC
+#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY
+ * \brief SERCOM2's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 100000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY
+ * \brief SERCOM2's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768
+#endif
+
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM3_CORE_SRC
+#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM3_SLOW_SRC
+#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM3_CORE_FREQUENCY
+ * \brief SERCOM3's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 100000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY
+ * \brief SERCOM3's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768
+#endif
+
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM4_CORE_SRC
+#define CONF_GCLK_SERCOM4_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM4_SLOW_SRC
+#define CONF_GCLK_SERCOM4_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM4_CORE_FREQUENCY
+ * \brief SERCOM4's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM4_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 100000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM4_SLOW_FREQUENCY
+ * \brief SERCOM4's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM4_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM4_SLOW_FREQUENCY 32768
+#endif
+
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM5_CORE_SRC
+#define CONF_GCLK_SERCOM5_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM5_SLOW_SRC
+#define CONF_GCLK_SERCOM5_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM5_CORE_FREQUENCY
+ * \brief SERCOM5's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM5_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 100000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM5_SLOW_FREQUENCY
+ * \brief SERCOM5's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM5_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM5_SLOW_FREQUENCY 32768
+#endif
+
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM6_CORE_SRC
+#define CONF_GCLK_SERCOM6_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM6_SLOW_SRC
+#define CONF_GCLK_SERCOM6_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM6_CORE_FREQUENCY
+ * \brief SERCOM6's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM6_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM6_CORE_FREQUENCY 100000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM6_SLOW_FREQUENCY
+ * \brief SERCOM6's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM6_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM6_SLOW_FREQUENCY 32768
+#endif
+
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CORE.
 #ifndef CONF_GCLK_SERCOM7_CORE_SRC
 #define CONF_GCLK_SERCOM7_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val
 #endif
diff --git a/sysmoOCTSIM/driver_init.c b/sysmoOCTSIM/driver_init.c
index 4ab622f..a196791 100644
--- a/sysmoOCTSIM/driver_init.c
+++ b/sysmoOCTSIM/driver_init.c
@@ -12,10 +12,45 @@
 #include <hal_init.h>
 
 /*! The buffer size for USART */
+#define SIM0_BUFFER_SIZE 16
+
+/*! The buffer size for USART */
+#define SIM1_BUFFER_SIZE 16
+
+/*! The buffer size for USART */
+#define SIM2_BUFFER_SIZE 16
+
+/*! The buffer size for USART */
+#define SIM3_BUFFER_SIZE 16
+
+/*! The buffer size for USART */
+#define SIM4_BUFFER_SIZE 16
+
+/*! The buffer size for USART */
+#define SIM5_BUFFER_SIZE 16
+
+/*! The buffer size for USART */
+#define SIM6_BUFFER_SIZE 16
+
+/*! The buffer size for USART */
 #define UART_DEBUG_BUFFER_SIZE 16
 
+struct usart_async_descriptor SIM0;
+struct usart_async_descriptor SIM1;
+struct usart_async_descriptor SIM2;
+struct usart_async_descriptor SIM3;
+struct usart_async_descriptor SIM4;
+struct usart_async_descriptor SIM5;
+struct usart_async_descriptor SIM6;
 struct usart_async_descriptor UART_debug;
 
+static uint8_t SIM0_buffer[SIM0_BUFFER_SIZE];
+static uint8_t SIM1_buffer[SIM1_BUFFER_SIZE];
+static uint8_t SIM2_buffer[SIM2_BUFFER_SIZE];
+static uint8_t SIM3_buffer[SIM3_BUFFER_SIZE];
+static uint8_t SIM4_buffer[SIM4_BUFFER_SIZE];
+static uint8_t SIM5_buffer[SIM5_BUFFER_SIZE];
+static uint8_t SIM6_buffer[SIM6_BUFFER_SIZE];
 static uint8_t UART_debug_buffer[UART_DEBUG_BUFFER_SIZE];
 
 /**
@@ -23,6 +58,265 @@
  *
  * Enables register interface and peripheral clock
  */
+void SIM0_CLOCK_init()
+{
+
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+	hri_mclk_set_APBAMASK_SERCOM0_bit(MCLK);
+}
+
+/**
+ * \brief USART pinmux initialization function
+ *
+ * Set each required pin to USART functionality
+ */
+void SIM0_PORT_init()
+{
+
+	gpio_set_pin_function(SIM0_IO, PINMUX_PA04D_SERCOM0_PAD0);
+}
+
+/**
+ * \brief USART initialization function
+ *
+ * Enables USART peripheral, clocks and initializes USART driver
+ */
+void SIM0_init(void)
+{
+	SIM0_CLOCK_init();
+	usart_async_init(&SIM0, SERCOM0, SIM0_buffer, SIM0_BUFFER_SIZE, (void *)NULL);
+	SIM0_PORT_init();
+}
+
+/**
+ * \brief USART Clock initialization function
+ *
+ * Enables register interface and peripheral clock
+ */
+void SIM1_CLOCK_init()
+{
+
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_CORE, CONF_GCLK_SERCOM1_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_SLOW, CONF_GCLK_SERCOM1_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+	hri_mclk_set_APBAMASK_SERCOM1_bit(MCLK);
+}
+
+/**
+ * \brief USART pinmux initialization function
+ *
+ * Set each required pin to USART functionality
+ */
+void SIM1_PORT_init()
+{
+
+	gpio_set_pin_function(SIM1_IO, PINMUX_PA16C_SERCOM1_PAD0);
+}
+
+/**
+ * \brief USART initialization function
+ *
+ * Enables USART peripheral, clocks and initializes USART driver
+ */
+void SIM1_init(void)
+{
+	SIM1_CLOCK_init();
+	usart_async_init(&SIM1, SERCOM1, SIM1_buffer, SIM1_BUFFER_SIZE, (void *)NULL);
+	SIM1_PORT_init();
+}
+
+/**
+ * \brief USART Clock initialization function
+ *
+ * Enables register interface and peripheral clock
+ */
+void SIM2_CLOCK_init()
+{
+
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+	hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK);
+}
+
+/**
+ * \brief USART pinmux initialization function
+ *
+ * Set each required pin to USART functionality
+ */
+void SIM2_PORT_init()
+{
+
+	gpio_set_pin_function(SIM2_IO, PINMUX_PA09D_SERCOM2_PAD0);
+}
+
+/**
+ * \brief USART initialization function
+ *
+ * Enables USART peripheral, clocks and initializes USART driver
+ */
+void SIM2_init(void)
+{
+	SIM2_CLOCK_init();
+	usart_async_init(&SIM2, SERCOM2, SIM2_buffer, SIM2_BUFFER_SIZE, (void *)NULL);
+	SIM2_PORT_init();
+}
+
+/**
+ * \brief USART Clock initialization function
+ *
+ * Enables register interface and peripheral clock
+ */
+void SIM3_CLOCK_init()
+{
+
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_CORE, CONF_GCLK_SERCOM3_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_SLOW, CONF_GCLK_SERCOM3_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+	hri_mclk_set_APBBMASK_SERCOM3_bit(MCLK);
+}
+
+/**
+ * \brief USART pinmux initialization function
+ *
+ * Set each required pin to USART functionality
+ */
+void SIM3_PORT_init()
+{
+
+	gpio_set_pin_function(SIM3_IO, PINMUX_PB20C_SERCOM3_PAD0);
+}
+
+/**
+ * \brief USART initialization function
+ *
+ * Enables USART peripheral, clocks and initializes USART driver
+ */
+void SIM3_init(void)
+{
+	SIM3_CLOCK_init();
+	usart_async_init(&SIM3, SERCOM3, SIM3_buffer, SIM3_BUFFER_SIZE, (void *)NULL);
+	SIM3_PORT_init();
+}
+
+/**
+ * \brief USART Clock initialization function
+ *
+ * Enables register interface and peripheral clock
+ */
+void SIM4_CLOCK_init()
+{
+
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_CORE, CONF_GCLK_SERCOM4_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_SLOW, CONF_GCLK_SERCOM4_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+	hri_mclk_set_APBDMASK_SERCOM4_bit(MCLK);
+}
+
+/**
+ * \brief USART pinmux initialization function
+ *
+ * Set each required pin to USART functionality
+ */
+void SIM4_PORT_init()
+{
+
+	gpio_set_pin_function(SIM4_IO, PINMUX_PB08D_SERCOM4_PAD0);
+}
+
+/**
+ * \brief USART initialization function
+ *
+ * Enables USART peripheral, clocks and initializes USART driver
+ */
+void SIM4_init(void)
+{
+	SIM4_CLOCK_init();
+	usart_async_init(&SIM4, SERCOM4, SIM4_buffer, SIM4_BUFFER_SIZE, (void *)NULL);
+	SIM4_PORT_init();
+}
+
+/**
+ * \brief USART Clock initialization function
+ *
+ * Enables register interface and peripheral clock
+ */
+void SIM5_CLOCK_init()
+{
+
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM5_GCLK_ID_CORE, CONF_GCLK_SERCOM5_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM5_GCLK_ID_SLOW, CONF_GCLK_SERCOM5_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+	hri_mclk_set_APBDMASK_SERCOM5_bit(MCLK);
+}
+
+/**
+ * \brief USART pinmux initialization function
+ *
+ * Set each required pin to USART functionality
+ */
+void SIM5_PORT_init()
+{
+
+	gpio_set_pin_function(SIM5_IO, PINMUX_PB16C_SERCOM5_PAD0);
+}
+
+/**
+ * \brief USART initialization function
+ *
+ * Enables USART peripheral, clocks and initializes USART driver
+ */
+void SIM5_init(void)
+{
+	SIM5_CLOCK_init();
+	usart_async_init(&SIM5, SERCOM5, SIM5_buffer, SIM5_BUFFER_SIZE, (void *)NULL);
+	SIM5_PORT_init();
+}
+
+/**
+ * \brief USART Clock initialization function
+ *
+ * Enables register interface and peripheral clock
+ */
+void SIM6_CLOCK_init()
+{
+
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM6_GCLK_ID_CORE, CONF_GCLK_SERCOM6_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM6_GCLK_ID_SLOW, CONF_GCLK_SERCOM6_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+	hri_mclk_set_APBDMASK_SERCOM6_bit(MCLK);
+}
+
+/**
+ * \brief USART pinmux initialization function
+ *
+ * Set each required pin to USART functionality
+ */
+void SIM6_PORT_init()
+{
+
+	gpio_set_pin_function(SIM6_IO, PINMUX_PC16C_SERCOM6_PAD0);
+}
+
+/**
+ * \brief USART initialization function
+ *
+ * Enables USART peripheral, clocks and initializes USART driver
+ */
+void SIM6_init(void)
+{
+	SIM6_CLOCK_init();
+	usart_async_init(&SIM6, SERCOM6, SIM6_buffer, SIM6_BUFFER_SIZE, (void *)NULL);
+	SIM6_PORT_init();
+}
+
+/**
+ * \brief USART Clock initialization function
+ *
+ * Enables register interface and peripheral clock
+ */
 void UART_debug_CLOCK_init()
 {
 
@@ -312,6 +606,13 @@
 
 	gpio_set_pin_function(USER_LED, GPIO_PIN_FUNCTION_OFF);
 
+	SIM0_init();
+	SIM1_init();
+	SIM2_init();
+	SIM3_init();
+	SIM4_init();
+	SIM5_init();
+	SIM6_init();
 	UART_debug_init();
 
 	USB_DEVICE_INSTANCE_init();
diff --git a/sysmoOCTSIM/driver_init.h b/sysmoOCTSIM/driver_init.h
index 25e6370..a0fbb88 100644
--- a/sysmoOCTSIM/driver_init.h
+++ b/sysmoOCTSIM/driver_init.h
@@ -22,11 +22,53 @@
 #include <hal_sleep.h>
 
 #include <hal_usart_async.h>
+#include <hal_usart_async.h>
+#include <hal_usart_async.h>
+#include <hal_usart_async.h>
+#include <hal_usart_async.h>
+#include <hal_usart_async.h>
+#include <hal_usart_async.h>
+#include <hal_usart_async.h>
 
 #include "hal_usb_device.h"
 
+extern struct usart_async_descriptor SIM0;
+extern struct usart_async_descriptor SIM1;
+extern struct usart_async_descriptor SIM2;
+extern struct usart_async_descriptor SIM3;
+extern struct usart_async_descriptor SIM4;
+extern struct usart_async_descriptor SIM5;
+extern struct usart_async_descriptor SIM6;
 extern struct usart_async_descriptor UART_debug;
 
+void SIM0_PORT_init(void);
+void SIM0_CLOCK_init(void);
+void SIM0_init(void);
+
+void SIM1_PORT_init(void);
+void SIM1_CLOCK_init(void);
+void SIM1_init(void);
+
+void SIM2_PORT_init(void);
+void SIM2_CLOCK_init(void);
+void SIM2_init(void);
+
+void SIM3_PORT_init(void);
+void SIM3_CLOCK_init(void);
+void SIM3_init(void);
+
+void SIM4_PORT_init(void);
+void SIM4_CLOCK_init(void);
+void SIM4_init(void);
+
+void SIM5_PORT_init(void);
+void SIM5_CLOCK_init(void);
+void SIM5_init(void);
+
+void SIM6_PORT_init(void);
+void SIM6_CLOCK_init(void);
+void SIM6_init(void);
+
 void UART_debug_PORT_init(void);
 void UART_debug_CLOCK_init(void);
 void UART_debug_init(void);
diff --git a/sysmoOCTSIM/examples/driver_examples.c b/sysmoOCTSIM/examples/driver_examples.c
index 8384c87..14f1ae5 100644
--- a/sysmoOCTSIM/examples/driver_examples.c
+++ b/sysmoOCTSIM/examples/driver_examples.c
@@ -11,6 +11,209 @@
 #include "utils.h"
 
 /**
+ * Example of using SIM0 to write "Hello World" using the IO abstraction.
+ *
+ * Since the driver is asynchronous we need to use statically allocated memory for string
+ * because driver initiates transfer and then returns before the transmission is completed.
+ *
+ * Once transfer has been completed the tx_cb function will be called.
+ */
+
+static uint8_t example_SIM0[12] = "Hello World!";
+
+static void tx_cb_SIM0(const struct usart_async_descriptor *const io_descr)
+{
+	/* Transfer completed */
+}
+
+void SIM0_example(void)
+{
+	struct io_descriptor *io;
+
+	usart_async_register_callback(&SIM0, USART_ASYNC_TXC_CB, tx_cb_SIM0);
+	/*usart_async_register_callback(&SIM0, USART_ASYNC_RXC_CB, rx_cb);
+	usart_async_register_callback(&SIM0, USART_ASYNC_ERROR_CB, err_cb);*/
+	usart_async_get_io_descriptor(&SIM0, &io);
+	usart_async_enable(&SIM0);
+
+	io_write(io, example_SIM0, 12);
+}
+
+/**
+ * Example of using SIM1 to write "Hello World" using the IO abstraction.
+ *
+ * Since the driver is asynchronous we need to use statically allocated memory for string
+ * because driver initiates transfer and then returns before the transmission is completed.
+ *
+ * Once transfer has been completed the tx_cb function will be called.
+ */
+
+static uint8_t example_SIM1[12] = "Hello World!";
+
+static void tx_cb_SIM1(const struct usart_async_descriptor *const io_descr)
+{
+	/* Transfer completed */
+}
+
+void SIM1_example(void)
+{
+	struct io_descriptor *io;
+
+	usart_async_register_callback(&SIM1, USART_ASYNC_TXC_CB, tx_cb_SIM1);
+	/*usart_async_register_callback(&SIM1, USART_ASYNC_RXC_CB, rx_cb);
+	usart_async_register_callback(&SIM1, USART_ASYNC_ERROR_CB, err_cb);*/
+	usart_async_get_io_descriptor(&SIM1, &io);
+	usart_async_enable(&SIM1);
+
+	io_write(io, example_SIM1, 12);
+}
+
+/**
+ * Example of using SIM2 to write "Hello World" using the IO abstraction.
+ *
+ * Since the driver is asynchronous we need to use statically allocated memory for string
+ * because driver initiates transfer and then returns before the transmission is completed.
+ *
+ * Once transfer has been completed the tx_cb function will be called.
+ */
+
+static uint8_t example_SIM2[12] = "Hello World!";
+
+static void tx_cb_SIM2(const struct usart_async_descriptor *const io_descr)
+{
+	/* Transfer completed */
+}
+
+void SIM2_example(void)
+{
+	struct io_descriptor *io;
+
+	usart_async_register_callback(&SIM2, USART_ASYNC_TXC_CB, tx_cb_SIM2);
+	/*usart_async_register_callback(&SIM2, USART_ASYNC_RXC_CB, rx_cb);
+	usart_async_register_callback(&SIM2, USART_ASYNC_ERROR_CB, err_cb);*/
+	usart_async_get_io_descriptor(&SIM2, &io);
+	usart_async_enable(&SIM2);
+
+	io_write(io, example_SIM2, 12);
+}
+
+/**
+ * Example of using SIM3 to write "Hello World" using the IO abstraction.
+ *
+ * Since the driver is asynchronous we need to use statically allocated memory for string
+ * because driver initiates transfer and then returns before the transmission is completed.
+ *
+ * Once transfer has been completed the tx_cb function will be called.
+ */
+
+static uint8_t example_SIM3[12] = "Hello World!";
+
+static void tx_cb_SIM3(const struct usart_async_descriptor *const io_descr)
+{
+	/* Transfer completed */
+}
+
+void SIM3_example(void)
+{
+	struct io_descriptor *io;
+
+	usart_async_register_callback(&SIM3, USART_ASYNC_TXC_CB, tx_cb_SIM3);
+	/*usart_async_register_callback(&SIM3, USART_ASYNC_RXC_CB, rx_cb);
+	usart_async_register_callback(&SIM3, USART_ASYNC_ERROR_CB, err_cb);*/
+	usart_async_get_io_descriptor(&SIM3, &io);
+	usart_async_enable(&SIM3);
+
+	io_write(io, example_SIM3, 12);
+}
+
+/**
+ * Example of using SIM4 to write "Hello World" using the IO abstraction.
+ *
+ * Since the driver is asynchronous we need to use statically allocated memory for string
+ * because driver initiates transfer and then returns before the transmission is completed.
+ *
+ * Once transfer has been completed the tx_cb function will be called.
+ */
+
+static uint8_t example_SIM4[12] = "Hello World!";
+
+static void tx_cb_SIM4(const struct usart_async_descriptor *const io_descr)
+{
+	/* Transfer completed */
+}
+
+void SIM4_example(void)
+{
+	struct io_descriptor *io;
+
+	usart_async_register_callback(&SIM4, USART_ASYNC_TXC_CB, tx_cb_SIM4);
+	/*usart_async_register_callback(&SIM4, USART_ASYNC_RXC_CB, rx_cb);
+	usart_async_register_callback(&SIM4, USART_ASYNC_ERROR_CB, err_cb);*/
+	usart_async_get_io_descriptor(&SIM4, &io);
+	usart_async_enable(&SIM4);
+
+	io_write(io, example_SIM4, 12);
+}
+
+/**
+ * Example of using SIM5 to write "Hello World" using the IO abstraction.
+ *
+ * Since the driver is asynchronous we need to use statically allocated memory for string
+ * because driver initiates transfer and then returns before the transmission is completed.
+ *
+ * Once transfer has been completed the tx_cb function will be called.
+ */
+
+static uint8_t example_SIM5[12] = "Hello World!";
+
+static void tx_cb_SIM5(const struct usart_async_descriptor *const io_descr)
+{
+	/* Transfer completed */
+}
+
+void SIM5_example(void)
+{
+	struct io_descriptor *io;
+
+	usart_async_register_callback(&SIM5, USART_ASYNC_TXC_CB, tx_cb_SIM5);
+	/*usart_async_register_callback(&SIM5, USART_ASYNC_RXC_CB, rx_cb);
+	usart_async_register_callback(&SIM5, USART_ASYNC_ERROR_CB, err_cb);*/
+	usart_async_get_io_descriptor(&SIM5, &io);
+	usart_async_enable(&SIM5);
+
+	io_write(io, example_SIM5, 12);
+}
+
+/**
+ * Example of using SIM6 to write "Hello World" using the IO abstraction.
+ *
+ * Since the driver is asynchronous we need to use statically allocated memory for string
+ * because driver initiates transfer and then returns before the transmission is completed.
+ *
+ * Once transfer has been completed the tx_cb function will be called.
+ */
+
+static uint8_t example_SIM6[12] = "Hello World!";
+
+static void tx_cb_SIM6(const struct usart_async_descriptor *const io_descr)
+{
+	/* Transfer completed */
+}
+
+void SIM6_example(void)
+{
+	struct io_descriptor *io;
+
+	usart_async_register_callback(&SIM6, USART_ASYNC_TXC_CB, tx_cb_SIM6);
+	/*usart_async_register_callback(&SIM6, USART_ASYNC_RXC_CB, rx_cb);
+	usart_async_register_callback(&SIM6, USART_ASYNC_ERROR_CB, err_cb);*/
+	usart_async_get_io_descriptor(&SIM6, &io);
+	usart_async_enable(&SIM6);
+
+	io_write(io, example_SIM6, 12);
+}
+
+/**
  * Example of using UART_debug to write "Hello World" using the IO abstraction.
  *
  * Since the driver is asynchronous we need to use statically allocated memory for string
diff --git a/sysmoOCTSIM/examples/driver_examples.h b/sysmoOCTSIM/examples/driver_examples.h
index 7bb60eb..4f2ce98 100644
--- a/sysmoOCTSIM/examples/driver_examples.h
+++ b/sysmoOCTSIM/examples/driver_examples.h
@@ -12,6 +12,20 @@
 extern "C" {
 #endif
 
+void SIM0_example(void);
+
+void SIM1_example(void);
+
+void SIM2_example(void);
+
+void SIM3_example(void);
+
+void SIM4_example(void);
+
+void SIM5_example(void);
+
+void SIM6_example(void);
+
 void UART_debug_example(void);
 
 #ifdef __cplusplus
diff --git a/sysmoOCTSIM/hpl/sercom/hpl_sercom.c b/sysmoOCTSIM/hpl/sercom/hpl_sercom.c
index 535ebc6..f235115 100644
--- a/sysmoOCTSIM/hpl/sercom/hpl_sercom.c
+++ b/sysmoOCTSIM/hpl/sercom/hpl_sercom.c
@@ -163,6 +163,20 @@
 };
 #endif
 
+static struct _usart_async_device *_sercom0_dev = NULL;
+
+static struct _usart_async_device *_sercom1_dev = NULL;
+
+static struct _usart_async_device *_sercom2_dev = NULL;
+
+static struct _usart_async_device *_sercom3_dev = NULL;
+
+static struct _usart_async_device *_sercom4_dev = NULL;
+
+static struct _usart_async_device *_sercom5_dev = NULL;
+
+static struct _usart_async_device *_sercom6_dev = NULL;
+
 static struct _usart_async_device *_sercom7_dev = NULL;
 
 static uint8_t _get_sercom_index(const void *const hw);
@@ -626,6 +640,34 @@
 static void _sercom_init_irq_param(const void *const hw, void *dev)
 {
 
+	if (hw == SERCOM0) {
+		_sercom0_dev = (struct _usart_async_device *)dev;
+	}
+
+	if (hw == SERCOM1) {
+		_sercom1_dev = (struct _usart_async_device *)dev;
+	}
+
+	if (hw == SERCOM2) {
+		_sercom2_dev = (struct _usart_async_device *)dev;
+	}
+
+	if (hw == SERCOM3) {
+		_sercom3_dev = (struct _usart_async_device *)dev;
+	}
+
+	if (hw == SERCOM4) {
+		_sercom4_dev = (struct _usart_async_device *)dev;
+	}
+
+	if (hw == SERCOM5) {
+		_sercom5_dev = (struct _usart_async_device *)dev;
+	}
+
+	if (hw == SERCOM6) {
+		_sercom6_dev = (struct _usart_async_device *)dev;
+	}
+
 	if (hw == SERCOM7) {
 		_sercom7_dev = (struct _usart_async_device *)dev;
 	}
@@ -2392,6 +2434,209 @@
 /**
  * \internal Sercom interrupt handler
  */
+void SERCOM0_0_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom0_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM0_1_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom0_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM0_2_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom0_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM0_3_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom0_dev);
+}
+
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM1_0_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom1_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM1_1_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom1_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM1_2_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom1_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM1_3_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom1_dev);
+}
+
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM2_0_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom2_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM2_1_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom2_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM2_2_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom2_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM2_3_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom2_dev);
+}
+
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM3_0_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom3_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM3_1_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom3_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM3_2_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom3_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM3_3_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom3_dev);
+}
+
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM4_0_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom4_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM4_1_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom4_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM4_2_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom4_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM4_3_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom4_dev);
+}
+
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM5_0_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom5_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM5_1_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom5_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM5_2_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom5_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM5_3_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom5_dev);
+}
+
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM6_0_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom6_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM6_1_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom6_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM6_2_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom6_dev);
+}
+/**
+ * \internal Sercom interrupt handler
+ */
+void SERCOM6_3_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom6_dev);
+}
+
+/**
+ * \internal Sercom interrupt handler
+ */
 void SERCOM7_0_Handler(void)
 {
 	_sercom_usart_interrupt_handler(_sercom7_dev);

-- 
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Gerrit-Project: osmo-ccid-firmware
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: I3f1411ec5bc2ed7dfa714550d041f52be665132a
Gerrit-Change-Number: 12811
Gerrit-PatchSet: 2
Gerrit-Owner: Kévin Redon <kredon at sysmocom.de>
Gerrit-Reviewer: Harald Welte <laforge at gnumonks.org>
Gerrit-Reviewer: Jenkins Builder (1000002)
Gerrit-Reviewer: Kévin Redon <kredon at sysmocom.de>
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