<p>Kévin Redon <strong>merged</strong> this change.</p><p><a href="https://gerrit.osmocom.org/12811">View Change</a></p><div style="white-space:pre-wrap">Approvals:
Jenkins Builder: Verified
Harald Welte: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">add ISO7816 peripherals<br><br>configure SERCOM 0 to 6 peripherals to communicate using the<br>ISO7816 T=0 protocol.<br>SERCOM7 should be for the 8th SIM card, but for now it is used as<br>UART debug output.<br>Auto-detection between SERCOM for the 8th SIM and debug UART will<br>be done later.<br><br>Change-Id: I3f1411ec5bc2ed7dfa714550d041f52be665132a<br>---<br>M sysmoOCTSIM/atmel_start_config.atstart<br>M sysmoOCTSIM/atmel_start_pins.h<br>M sysmoOCTSIM/config/hpl_sercom_config.h<br>M sysmoOCTSIM/config/peripheral_clk_config.h<br>M sysmoOCTSIM/driver_init.c<br>M sysmoOCTSIM/driver_init.h<br>M sysmoOCTSIM/examples/driver_examples.c<br>M sysmoOCTSIM/examples/driver_examples.h<br>M sysmoOCTSIM/hpl/sercom/hpl_sercom.c<br>9 files changed, 3,619 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/sysmoOCTSIM/atmel_start_config.atstart b/sysmoOCTSIM/atmel_start_config.atstart</span><br><span>index b6303f9..975423d 100644</span><br><span>--- a/sysmoOCTSIM/atmel_start_config.atstart</span><br><span>+++ b/sysmoOCTSIM/atmel_start_config.atstart</span><br><span>@@ -943,6 +943,307 @@</span><br><span> variant: null</span><br><span> clocks:</span><br><span> domain_group: null</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM0:</span><br><span style="color: hsl(120, 100%, 40%);">+ user_label: SIM0</span><br><span style="color: hsl(120, 100%, 40%);">+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM0::driver_config_definition::USART.with.ISO7816::HAL:Driver:USART.Async</span><br><span style="color: hsl(120, 100%, 40%);">+ functionality: USART</span><br><span style="color: hsl(120, 100%, 40%);">+ api: HAL:Driver:USART_Async</span><br><span style="color: hsl(120, 100%, 40%);">+ configuration:</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_advanced: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_clock_mode: USART with internal clock</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_cloden: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_dbgstop: Keep running</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_dord: LSB is transmitted first</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_ibon: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_runstdby: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_sfde: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_baud_rate: 9600</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_character_size: 8 bits</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_dsnack: The successive receive NACK is disable.</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_gtime: 2-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_inack: NACK is transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_inverse_enabled: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_iso7816_type: T=0</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_maxiter: 7</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_parity: Even parity</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_rx_enable: true</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_stop_bit: One stop bit</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_tx_enable: true</span><br><span style="color: hsl(120, 100%, 40%);">+ optional_signals: []</span><br><span style="color: hsl(120, 100%, 40%);">+ variant:</span><br><span style="color: hsl(120, 100%, 40%);">+ specification: TXPO=2, RXPO=0</span><br><span style="color: hsl(120, 100%, 40%);">+ required_signals:</span><br><span style="color: hsl(120, 100%, 40%);">+ - name: SERCOM0/PAD/0</span><br><span style="color: hsl(120, 100%, 40%);">+ pad: PA04</span><br><span style="color: hsl(120, 100%, 40%);">+ label: RX/TX</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks:</span><br><span style="color: hsl(120, 100%, 40%);">+ domain_group:</span><br><span style="color: hsl(120, 100%, 40%);">+ nodes:</span><br><span style="color: hsl(120, 100%, 40%);">+ - name: Core</span><br><span style="color: hsl(120, 100%, 40%);">+ input: Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+ - name: Slow</span><br><span style="color: hsl(120, 100%, 40%);">+ input: Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+ configuration:</span><br><span style="color: hsl(120, 100%, 40%);">+ core_gclk_selection: Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+ slow_gclk_selection: Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM1:</span><br><span style="color: hsl(120, 100%, 40%);">+ user_label: SIM1</span><br><span style="color: hsl(120, 100%, 40%);">+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM1::driver_config_definition::USART.with.ISO7816::HAL:Driver:USART.Async</span><br><span style="color: hsl(120, 100%, 40%);">+ functionality: USART</span><br><span style="color: hsl(120, 100%, 40%);">+ api: HAL:Driver:USART_Async</span><br><span style="color: hsl(120, 100%, 40%);">+ configuration:</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_advanced: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_clock_mode: USART with internal clock</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_cloden: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_dbgstop: Keep running</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_dord: LSB is transmitted first</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_ibon: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_runstdby: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_sfde: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_baud_rate: 9600</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_character_size: 8 bits</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_dsnack: The successive receive NACK is disable.</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_gtime: 2-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_inack: NACK is transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_inverse_enabled: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_iso7816_type: T=0</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_maxiter: 7</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_parity: Even parity</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_rx_enable: true</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_stop_bit: One stop bit</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_tx_enable: true</span><br><span style="color: hsl(120, 100%, 40%);">+ optional_signals: []</span><br><span style="color: hsl(120, 100%, 40%);">+ variant:</span><br><span style="color: hsl(120, 100%, 40%);">+ specification: TXPO=2, RXPO=0</span><br><span style="color: hsl(120, 100%, 40%);">+ required_signals:</span><br><span style="color: hsl(120, 100%, 40%);">+ - name: SERCOM1/PAD/0</span><br><span style="color: hsl(120, 100%, 40%);">+ pad: PA16</span><br><span style="color: hsl(120, 100%, 40%);">+ label: RX/TX</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks:</span><br><span style="color: hsl(120, 100%, 40%);">+ domain_group:</span><br><span style="color: hsl(120, 100%, 40%);">+ nodes:</span><br><span style="color: hsl(120, 100%, 40%);">+ - name: Core</span><br><span style="color: hsl(120, 100%, 40%);">+ input: Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+ - name: Slow</span><br><span style="color: hsl(120, 100%, 40%);">+ input: Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+ configuration:</span><br><span style="color: hsl(120, 100%, 40%);">+ core_gclk_selection: Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+ slow_gclk_selection: Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM2:</span><br><span style="color: hsl(120, 100%, 40%);">+ user_label: SIM2</span><br><span style="color: hsl(120, 100%, 40%);">+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM2::driver_config_definition::USART.with.ISO7816::HAL:Driver:USART.Async</span><br><span style="color: hsl(120, 100%, 40%);">+ functionality: USART</span><br><span style="color: hsl(120, 100%, 40%);">+ api: HAL:Driver:USART_Async</span><br><span style="color: hsl(120, 100%, 40%);">+ configuration:</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_advanced: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_clock_mode: USART with internal clock</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_cloden: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_dbgstop: Keep running</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_dord: LSB is transmitted first</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_ibon: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_runstdby: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_sfde: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_baud_rate: 9600</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_character_size: 8 bits</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_dsnack: The successive receive NACK is disable.</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_gtime: 2-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_inack: NACK is transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_inverse_enabled: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_iso7816_type: T=0</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_maxiter: 7</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_parity: Even parity</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_rx_enable: true</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_stop_bit: One stop bit</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_tx_enable: true</span><br><span style="color: hsl(120, 100%, 40%);">+ optional_signals: []</span><br><span style="color: hsl(120, 100%, 40%);">+ variant:</span><br><span style="color: hsl(120, 100%, 40%);">+ specification: TXPO=2, RXPO=0</span><br><span style="color: hsl(120, 100%, 40%);">+ required_signals:</span><br><span style="color: hsl(120, 100%, 40%);">+ - name: SERCOM2/PAD/0</span><br><span style="color: hsl(120, 100%, 40%);">+ pad: PA09</span><br><span style="color: hsl(120, 100%, 40%);">+ label: RX/TX</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks:</span><br><span style="color: hsl(120, 100%, 40%);">+ domain_group:</span><br><span style="color: hsl(120, 100%, 40%);">+ nodes:</span><br><span style="color: hsl(120, 100%, 40%);">+ - name: Core</span><br><span style="color: hsl(120, 100%, 40%);">+ input: Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+ - name: Slow</span><br><span style="color: hsl(120, 100%, 40%);">+ input: Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+ configuration:</span><br><span style="color: hsl(120, 100%, 40%);">+ core_gclk_selection: Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+ slow_gclk_selection: Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM3:</span><br><span style="color: hsl(120, 100%, 40%);">+ user_label: SIM3</span><br><span style="color: hsl(120, 100%, 40%);">+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM3::driver_config_definition::USART.with.ISO7816::HAL:Driver:USART.Async</span><br><span style="color: hsl(120, 100%, 40%);">+ functionality: USART</span><br><span style="color: hsl(120, 100%, 40%);">+ api: HAL:Driver:USART_Async</span><br><span style="color: hsl(120, 100%, 40%);">+ configuration:</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_advanced: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_clock_mode: USART with internal clock</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_cloden: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_dbgstop: Keep running</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_dord: LSB is transmitted first</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_ibon: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_runstdby: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_sfde: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_baud_rate: 9600</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_character_size: 8 bits</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_dsnack: The successive receive NACK is disable.</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_gtime: 2-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_inack: NACK is transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_inverse_enabled: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_iso7816_type: T=0</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_maxiter: 7</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_parity: Even parity</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_rx_enable: true</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_stop_bit: One stop bit</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_tx_enable: true</span><br><span style="color: hsl(120, 100%, 40%);">+ optional_signals: []</span><br><span style="color: hsl(120, 100%, 40%);">+ variant:</span><br><span style="color: hsl(120, 100%, 40%);">+ specification: TXPO=2, RXPO=0</span><br><span style="color: hsl(120, 100%, 40%);">+ required_signals:</span><br><span style="color: hsl(120, 100%, 40%);">+ - name: SERCOM3/PAD/0</span><br><span style="color: hsl(120, 100%, 40%);">+ pad: PB20</span><br><span style="color: hsl(120, 100%, 40%);">+ label: RX/TX</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks:</span><br><span style="color: hsl(120, 100%, 40%);">+ domain_group:</span><br><span style="color: hsl(120, 100%, 40%);">+ nodes:</span><br><span style="color: hsl(120, 100%, 40%);">+ - name: Core</span><br><span style="color: hsl(120, 100%, 40%);">+ input: Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+ - name: Slow</span><br><span style="color: hsl(120, 100%, 40%);">+ input: Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+ configuration:</span><br><span style="color: hsl(120, 100%, 40%);">+ core_gclk_selection: Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+ slow_gclk_selection: Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM4:</span><br><span style="color: hsl(120, 100%, 40%);">+ user_label: SIM4</span><br><span style="color: hsl(120, 100%, 40%);">+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM4::driver_config_definition::USART.with.ISO7816::HAL:Driver:USART.Async</span><br><span style="color: hsl(120, 100%, 40%);">+ functionality: USART</span><br><span style="color: hsl(120, 100%, 40%);">+ api: HAL:Driver:USART_Async</span><br><span style="color: hsl(120, 100%, 40%);">+ configuration:</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_advanced: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_clock_mode: USART with internal clock</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_cloden: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_dbgstop: Keep running</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_dord: LSB is transmitted first</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_ibon: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_runstdby: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_sfde: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_baud_rate: 9600</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_character_size: 8 bits</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_dsnack: The successive receive NACK is disable.</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_gtime: 2-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_inack: NACK is transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_inverse_enabled: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_iso7816_type: T=0</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_maxiter: 7</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_parity: Even parity</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_rx_enable: true</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_stop_bit: One stop bit</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_tx_enable: true</span><br><span style="color: hsl(120, 100%, 40%);">+ optional_signals: []</span><br><span style="color: hsl(120, 100%, 40%);">+ variant:</span><br><span style="color: hsl(120, 100%, 40%);">+ specification: TXPO=2, RXPO=0</span><br><span style="color: hsl(120, 100%, 40%);">+ required_signals:</span><br><span style="color: hsl(120, 100%, 40%);">+ - name: SERCOM4/PAD/0</span><br><span style="color: hsl(120, 100%, 40%);">+ pad: PB08</span><br><span style="color: hsl(120, 100%, 40%);">+ label: RX/TX</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks:</span><br><span style="color: hsl(120, 100%, 40%);">+ domain_group:</span><br><span style="color: hsl(120, 100%, 40%);">+ nodes:</span><br><span style="color: hsl(120, 100%, 40%);">+ - name: Core</span><br><span style="color: hsl(120, 100%, 40%);">+ input: Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+ - name: Slow</span><br><span style="color: hsl(120, 100%, 40%);">+ input: Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+ configuration:</span><br><span style="color: hsl(120, 100%, 40%);">+ core_gclk_selection: Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+ slow_gclk_selection: Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM5:</span><br><span style="color: hsl(120, 100%, 40%);">+ user_label: SIM5</span><br><span style="color: hsl(120, 100%, 40%);">+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM5::driver_config_definition::USART.with.ISO7816::HAL:Driver:USART.Async</span><br><span style="color: hsl(120, 100%, 40%);">+ functionality: USART</span><br><span style="color: hsl(120, 100%, 40%);">+ api: HAL:Driver:USART_Async</span><br><span style="color: hsl(120, 100%, 40%);">+ configuration:</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_advanced: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_clock_mode: USART with internal clock</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_cloden: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_dbgstop: Keep running</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_dord: LSB is transmitted first</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_ibon: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_runstdby: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_sfde: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_baud_rate: 9600</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_character_size: 8 bits</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_dsnack: The successive receive NACK is disable.</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_gtime: 2-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_inack: NACK is transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_inverse_enabled: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_iso7816_type: T=0</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_maxiter: 7</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_parity: Even parity</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_rx_enable: true</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_stop_bit: One stop bit</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_tx_enable: true</span><br><span style="color: hsl(120, 100%, 40%);">+ optional_signals: []</span><br><span style="color: hsl(120, 100%, 40%);">+ variant:</span><br><span style="color: hsl(120, 100%, 40%);">+ specification: TXPO=2, RXPO=0</span><br><span style="color: hsl(120, 100%, 40%);">+ required_signals:</span><br><span style="color: hsl(120, 100%, 40%);">+ - name: SERCOM5/PAD/0</span><br><span style="color: hsl(120, 100%, 40%);">+ pad: PB16</span><br><span style="color: hsl(120, 100%, 40%);">+ label: RX/TX</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks:</span><br><span style="color: hsl(120, 100%, 40%);">+ domain_group:</span><br><span style="color: hsl(120, 100%, 40%);">+ nodes:</span><br><span style="color: hsl(120, 100%, 40%);">+ - name: Core</span><br><span style="color: hsl(120, 100%, 40%);">+ input: Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+ - name: Slow</span><br><span style="color: hsl(120, 100%, 40%);">+ input: Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+ configuration:</span><br><span style="color: hsl(120, 100%, 40%);">+ core_gclk_selection: Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+ slow_gclk_selection: Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM6:</span><br><span style="color: hsl(120, 100%, 40%);">+ user_label: SIM6</span><br><span style="color: hsl(120, 100%, 40%);">+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM6::driver_config_definition::USART.with.ISO7816::HAL:Driver:USART.Async</span><br><span style="color: hsl(120, 100%, 40%);">+ functionality: USART</span><br><span style="color: hsl(120, 100%, 40%);">+ api: HAL:Driver:USART_Async</span><br><span style="color: hsl(120, 100%, 40%);">+ configuration:</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_advanced: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_clock_mode: USART with internal clock</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_cloden: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_dbgstop: Keep running</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_dord: LSB is transmitted first</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_ibon: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_runstdby: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_arch_sfde: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_baud_rate: 9600</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_character_size: 8 bits</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_dsnack: The successive receive NACK is disable.</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_gtime: 2-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_inack: NACK is transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_inverse_enabled: false</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_iso7816_type: T=0</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_maxiter: 7</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_parity: Even parity</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_rx_enable: true</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_stop_bit: One stop bit</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_tx_enable: true</span><br><span style="color: hsl(120, 100%, 40%);">+ optional_signals: []</span><br><span style="color: hsl(120, 100%, 40%);">+ variant:</span><br><span style="color: hsl(120, 100%, 40%);">+ specification: TXPO=2, RXPO=0</span><br><span style="color: hsl(120, 100%, 40%);">+ required_signals:</span><br><span style="color: hsl(120, 100%, 40%);">+ - name: SERCOM6/PAD/0</span><br><span style="color: hsl(120, 100%, 40%);">+ pad: PC16</span><br><span style="color: hsl(120, 100%, 40%);">+ label: RX/TX</span><br><span style="color: hsl(120, 100%, 40%);">+ clocks:</span><br><span style="color: hsl(120, 100%, 40%);">+ domain_group:</span><br><span style="color: hsl(120, 100%, 40%);">+ nodes:</span><br><span style="color: hsl(120, 100%, 40%);">+ - name: Core</span><br><span style="color: hsl(120, 100%, 40%);">+ input: Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+ - name: Slow</span><br><span style="color: hsl(120, 100%, 40%);">+ input: Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+ configuration:</span><br><span style="color: hsl(120, 100%, 40%);">+ core_gclk_selection: Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+ slow_gclk_selection: Generic clock generator 3</span><br><span> UART_debug:</span><br><span> user_label: UART_debug</span><br><span> definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM7::driver_config_definition::UART::HAL:Driver:USART.Async</span><br><span>@@ -1030,6 +1331,24 @@</span><br><span> configuration:</span><br><span> usb_gclk_selection: Generic clock generator 1</span><br><span> pads:</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM4_IO:</span><br><span style="color: hsl(120, 100%, 40%);">+ name: PB08</span><br><span style="color: hsl(120, 100%, 40%);">+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PB08</span><br><span style="color: hsl(120, 100%, 40%);">+ mode: Peripheral IO</span><br><span style="color: hsl(120, 100%, 40%);">+ user_label: SIM4_IO</span><br><span style="color: hsl(120, 100%, 40%);">+ configuration: null</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM0_IO:</span><br><span style="color: hsl(120, 100%, 40%);">+ name: PA04</span><br><span style="color: hsl(120, 100%, 40%);">+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA04</span><br><span style="color: hsl(120, 100%, 40%);">+ mode: Peripheral IO</span><br><span style="color: hsl(120, 100%, 40%);">+ user_label: SIM0_IO</span><br><span style="color: hsl(120, 100%, 40%);">+ configuration: null</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM2_IO:</span><br><span style="color: hsl(120, 100%, 40%);">+ name: PA09</span><br><span style="color: hsl(120, 100%, 40%);">+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA09</span><br><span style="color: hsl(120, 100%, 40%);">+ mode: Peripheral IO</span><br><span style="color: hsl(120, 100%, 40%);">+ user_label: SIM2_IO</span><br><span style="color: hsl(120, 100%, 40%);">+ configuration: null</span><br><span> SIMCLK_20MHZ:</span><br><span> name: PA11</span><br><span> definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA11</span><br><span>@@ -1046,6 +1365,30 @@</span><br><span> mode: Digital input</span><br><span> user_label: SWITCH</span><br><span> configuration: null</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM1_IO:</span><br><span style="color: hsl(120, 100%, 40%);">+ name: PA16</span><br><span style="color: hsl(120, 100%, 40%);">+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA16</span><br><span style="color: hsl(120, 100%, 40%);">+ mode: Peripheral IO</span><br><span style="color: hsl(120, 100%, 40%);">+ user_label: SIM1_IO</span><br><span style="color: hsl(120, 100%, 40%);">+ configuration: null</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM6_IO:</span><br><span style="color: hsl(120, 100%, 40%);">+ name: PC16</span><br><span style="color: hsl(120, 100%, 40%);">+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PC16</span><br><span style="color: hsl(120, 100%, 40%);">+ mode: Peripheral IO</span><br><span style="color: hsl(120, 100%, 40%);">+ user_label: SIM6_IO</span><br><span style="color: hsl(120, 100%, 40%);">+ configuration: null</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM5_IO:</span><br><span style="color: hsl(120, 100%, 40%);">+ name: PB16</span><br><span style="color: hsl(120, 100%, 40%);">+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PB16</span><br><span style="color: hsl(120, 100%, 40%);">+ mode: Peripheral IO</span><br><span style="color: hsl(120, 100%, 40%);">+ user_label: SIM5_IO</span><br><span style="color: hsl(120, 100%, 40%);">+ configuration: null</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM3_IO:</span><br><span style="color: hsl(120, 100%, 40%);">+ name: PB20</span><br><span style="color: hsl(120, 100%, 40%);">+ definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PB20</span><br><span style="color: hsl(120, 100%, 40%);">+ mode: Peripheral IO</span><br><span style="color: hsl(120, 100%, 40%);">+ user_label: SIM3_IO</span><br><span style="color: hsl(120, 100%, 40%);">+ configuration: null</span><br><span> VB0:</span><br><span> name: PA20</span><br><span> definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA20</span><br><span>diff --git a/sysmoOCTSIM/atmel_start_pins.h b/sysmoOCTSIM/atmel_start_pins.h</span><br><span>index fea4388..ad5f27b 100644</span><br><span>--- a/sysmoOCTSIM/atmel_start_pins.h</span><br><span>+++ b/sysmoOCTSIM/atmel_start_pins.h</span><br><span>@@ -27,16 +27,23 @@</span><br><span> #define GPIO_PIN_FUNCTION_M 12</span><br><span> #define GPIO_PIN_FUNCTION_N 13</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#define SIM0_IO GPIO(GPIO_PORTA, 4)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SIM2_IO GPIO(GPIO_PORTA, 9)</span><br><span> #define SIMCLK_20MHZ GPIO(GPIO_PORTA, 11)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SIM1_IO GPIO(GPIO_PORTA, 16)</span><br><span> #define VB0 GPIO(GPIO_PORTA, 20)</span><br><span> #define VB1 GPIO(GPIO_PORTA, 21)</span><br><span> #define VB2 GPIO(GPIO_PORTA, 22)</span><br><span> #define VB3 GPIO(GPIO_PORTA, 23)</span><br><span> #define USBUP_D_N GPIO(GPIO_PORTA, 24)</span><br><span> #define USBUP_D_P GPIO(GPIO_PORTA, 25)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SIM4_IO GPIO(GPIO_PORTB, 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SIM5_IO GPIO(GPIO_PORTB, 16)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SIM3_IO GPIO(GPIO_PORTB, 20)</span><br><span> #define UART_TX GPIO(GPIO_PORTB, 30)</span><br><span> #define UART_RX GPIO(GPIO_PORTB, 31)</span><br><span> #define SWITCH GPIO(GPIO_PORTC, 14)</span><br><span style="color: hsl(120, 100%, 40%);">+#define SIM6_IO GPIO(GPIO_PORTC, 16)</span><br><span> #define USER_LED GPIO(GPIO_PORTC, 26)</span><br><span> </span><br><span> #endif // ATMEL_START_PINS_H_INCLUDED</span><br><span>diff --git a/sysmoOCTSIM/config/hpl_sercom_config.h b/sysmoOCTSIM/config/hpl_sercom_config.h</span><br><span>index 2a8c023..735fdc2 100644</span><br><span>--- a/sysmoOCTSIM/config/hpl_sercom_config.h</span><br><span>+++ b/sysmoOCTSIM/config/hpl_sercom_config.h</span><br><span>@@ -6,6 +6,1910 @@</span><br><span> </span><br><span> #include <peripheral_clk_config.h></span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_ENABLE 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <h> Basic Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Receive buffer enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Enable input buffer in SERCOM module</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_rx_enable</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_RXEN</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_RXEN 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Transmitt buffer enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Enable output buffer in SERCOM module</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_tx_enable</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_TXEN</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_TXEN 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Frame parity</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=>Even parity</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Parity bit mode for USART frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_parity</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_PARITY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_PARITY 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Character Size</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=>8 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=>9 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x5=>5 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x6=>6 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x7=>7 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Data character size in USART frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_character_size</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_CHSIZE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_CHSIZE 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Stop Bit</span><br><span style="color: hsl(120, 100%, 40%);">+// <0=>One stop bit</span><br><span style="color: hsl(120, 100%, 40%);">+// <1=>Two stop bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Number of stop bits in USART frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_stop_bit</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_SBMODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_SBMODE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Baud rate <1-3000000></span><br><span style="color: hsl(120, 100%, 40%);">+// <i> USART baud rate setting</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_baud_rate</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_BAUD</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_BAUD 9600</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+// </h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <h> ISO7816 configuration</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Protocol Type</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=> T=0</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=> T=1</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define ISO7816 protocol type as 0.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_iso7816_type</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_ISO7816_PROTOCOL_T</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_ISO7816_PROTOCOL_T 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Inhibit Not Acknowledge</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=> NACK is transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=> NACK is not transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define whether a NACK is transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_inack</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_INACK</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_INACK 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Disable Successive Not Acknowledge</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=> The successive receive NACK is disable.</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=> The successive receive NACK is enable.</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define whether NACK will be sent on parity error reception.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_dsnack</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_DSNACK</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_DSNACK 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Maximum Iterations<0-7></span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define the maximum number of retransmit iterations.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_maxiter</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_MAXITER</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_MAXITER 0x7</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Guard Time</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x2=> 2-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x3=> 3-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x4=> 4-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x5=> 5-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x6=> 6-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x7=> 7-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define the guard time.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_gtime</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_GTIME</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_GTIME 0x2</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Inverse transmission and reception enabled</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define inverse transmission and reception enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_inverse_enabled</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_INVERSE_ENABLED</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_INVERSE_ENABLED 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if (CONF_SERCOM_0_USART_INVERSE_ENABLED == 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_RXINV 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_TXINV 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_RXINV 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_TXINV 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// </h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <e> Advanced configuration</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_advanced</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_ADVANCED_CONFIG</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_ADVANCED_CONFIG 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Run in stand-by</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Keep the module running in standby sleep mode</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_runstdby</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_RUNSTDBY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_RUNSTDBY 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Immediate Buffer Overflow Notification</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Controls when the BUFOVF status bit is asserted</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_ibon</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_IBON</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_IBON 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Start of Frame Detection Enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_sfde</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_SFDE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_SFDE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Collision Detection Enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Collision detection enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_cloden</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_CLODEN</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_CLODEN 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Operating Mode</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=>USART with internal clock</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Drive the shift register by an internal clock generated by the baud rate generator.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_clock_mode</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_MODE 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Data Order</span><br><span style="color: hsl(120, 100%, 40%);">+// <0=>MSB is transmitted first</span><br><span style="color: hsl(120, 100%, 40%);">+// <1=>LSB is transmitted first</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Data order of the data bits in the frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_dord</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_DORD</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_DORD 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Debug Stop Mode</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.</span><br><span style="color: hsl(120, 100%, 40%);">+// <0=>Keep running</span><br><span style="color: hsl(120, 100%, 40%);">+// <1=>Halt</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_dbgstop</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_DEBUG_STOP_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_DEBUG_STOP_MODE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Does not do anything in USRT mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_SAMPR 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_SAMPA 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_FRACTIONAL 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Does not do anything in UART mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_CPOL 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Does not do anything in USRT mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_ENC 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// </e></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_CMODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_CMODE CONF_SERCOM_0_USART_ISO7816_PROTOCOL_T</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* RX is on PIN_PA04 */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_RXPO</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_RXPO 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* TX uses the same pin with RX */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_TXPO</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_TXPO 2</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Set iso7816 mode */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_PMODE (CONF_SERCOM_0_USART_PARITY - 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_FORM 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if CONF_SERCOM_0_USART_CMODE == 0</span><br><span style="color: hsl(120, 100%, 40%);">+// Calculate BAUD register value in UART mode</span><br><span style="color: hsl(120, 100%, 40%);">+#if CONF_SERCOM_0_USART_SAMPR == 0</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ 65536 - ((65536 * 16.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_0_USART_SAMPR == 1</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ ((CONF_GCLK_SERCOM0_CORE_FREQUENCY) / (CONF_SERCOM_0_USART_BAUD * 16)) - (CONF_SERCOM_0_USART_FRACTIONAL / 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_0_USART_SAMPR == 2</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ 65536 - ((65536 * 8.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_0_USART_SAMPR == 3</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ ((CONF_GCLK_SERCOM0_CORE_FREQUENCY) / (CONF_SERCOM_0_USART_BAUD * 8)) - (CONF_SERCOM_0_USART_FRACTIONAL / 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_0_USART_SAMPR == 4</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ 65536 - ((65536 * 3.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_0_USART_CMODE == 1</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+// Calculate BAUD register value in USRT mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_BAUD_RATE (CONF_GCLK_SERCOM0_CORE_FREQUENCY) / (2 * CONF_SERCOM_0_USART_BAUD) - 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+#error CMODE value for SERCOM 0 in USART mode not known</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <peripheral_clk_config.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_ENABLE 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <h> Basic Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Receive buffer enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Enable input buffer in SERCOM module</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_rx_enable</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_RXEN</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_RXEN 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Transmitt buffer enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Enable output buffer in SERCOM module</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_tx_enable</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_TXEN</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_TXEN 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Frame parity</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=>Even parity</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Parity bit mode for USART frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_parity</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_PARITY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_PARITY 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Character Size</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=>8 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=>9 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x5=>5 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x6=>6 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x7=>7 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Data character size in USART frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_character_size</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_CHSIZE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_CHSIZE 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Stop Bit</span><br><span style="color: hsl(120, 100%, 40%);">+// <0=>One stop bit</span><br><span style="color: hsl(120, 100%, 40%);">+// <1=>Two stop bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Number of stop bits in USART frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_stop_bit</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_SBMODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_SBMODE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Baud rate <1-3000000></span><br><span style="color: hsl(120, 100%, 40%);">+// <i> USART baud rate setting</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_baud_rate</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_BAUD</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_BAUD 9600</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+// </h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <h> ISO7816 configuration</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Protocol Type</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=> T=0</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=> T=1</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define ISO7816 protocol type as 0.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_iso7816_type</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_ISO7816_PROTOCOL_T</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_ISO7816_PROTOCOL_T 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Inhibit Not Acknowledge</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=> NACK is transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=> NACK is not transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define whether a NACK is transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_inack</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_INACK</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_INACK 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Disable Successive Not Acknowledge</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=> The successive receive NACK is disable.</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=> The successive receive NACK is enable.</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define whether NACK will be sent on parity error reception.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_dsnack</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_DSNACK</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_DSNACK 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Maximum Iterations<0-7></span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define the maximum number of retransmit iterations.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_maxiter</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_MAXITER</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_MAXITER 0x7</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Guard Time</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x2=> 2-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x3=> 3-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x4=> 4-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x5=> 5-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x6=> 6-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x7=> 7-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define the guard time.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_gtime</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_GTIME</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_GTIME 0x2</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Inverse transmission and reception enabled</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define inverse transmission and reception enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_inverse_enabled</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_INVERSE_ENABLED</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_INVERSE_ENABLED 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if (CONF_SERCOM_1_USART_INVERSE_ENABLED == 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_RXINV 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_TXINV 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_RXINV 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_TXINV 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// </h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <e> Advanced configuration</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_advanced</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_ADVANCED_CONFIG</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_ADVANCED_CONFIG 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Run in stand-by</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Keep the module running in standby sleep mode</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_runstdby</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_RUNSTDBY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_RUNSTDBY 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Immediate Buffer Overflow Notification</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Controls when the BUFOVF status bit is asserted</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_ibon</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_IBON</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_IBON 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Start of Frame Detection Enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_sfde</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_SFDE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_SFDE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Collision Detection Enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Collision detection enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_cloden</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_CLODEN</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_CLODEN 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Operating Mode</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=>USART with internal clock</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Drive the shift register by an internal clock generated by the baud rate generator.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_clock_mode</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_MODE 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Data Order</span><br><span style="color: hsl(120, 100%, 40%);">+// <0=>MSB is transmitted first</span><br><span style="color: hsl(120, 100%, 40%);">+// <1=>LSB is transmitted first</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Data order of the data bits in the frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_dord</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_DORD</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_DORD 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Debug Stop Mode</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.</span><br><span style="color: hsl(120, 100%, 40%);">+// <0=>Keep running</span><br><span style="color: hsl(120, 100%, 40%);">+// <1=>Halt</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_dbgstop</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_DEBUG_STOP_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_DEBUG_STOP_MODE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Does not do anything in USRT mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_SAMPR 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_SAMPA 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_FRACTIONAL 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Does not do anything in UART mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_CPOL 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Does not do anything in USRT mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_ENC 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// </e></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_CMODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_CMODE CONF_SERCOM_1_USART_ISO7816_PROTOCOL_T</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* RX is on PIN_PA16 */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_RXPO</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_RXPO 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* TX uses the same pin with RX */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_TXPO</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_TXPO 2</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Set iso7816 mode */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_PMODE (CONF_SERCOM_1_USART_PARITY - 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_FORM 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if CONF_SERCOM_1_USART_CMODE == 0</span><br><span style="color: hsl(120, 100%, 40%);">+// Calculate BAUD register value in UART mode</span><br><span style="color: hsl(120, 100%, 40%);">+#if CONF_SERCOM_1_USART_SAMPR == 0</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ 65536 - ((65536 * 16.0f * CONF_SERCOM_1_USART_BAUD) / CONF_GCLK_SERCOM1_CORE_FREQUENCY)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_1_USART_SAMPR == 1</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ ((CONF_GCLK_SERCOM1_CORE_FREQUENCY) / (CONF_SERCOM_1_USART_BAUD * 16)) - (CONF_SERCOM_1_USART_FRACTIONAL / 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_1_USART_SAMPR == 2</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ 65536 - ((65536 * 8.0f * CONF_SERCOM_1_USART_BAUD) / CONF_GCLK_SERCOM1_CORE_FREQUENCY)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_1_USART_SAMPR == 3</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ ((CONF_GCLK_SERCOM1_CORE_FREQUENCY) / (CONF_SERCOM_1_USART_BAUD * 8)) - (CONF_SERCOM_1_USART_FRACTIONAL / 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_1_USART_SAMPR == 4</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ 65536 - ((65536 * 3.0f * CONF_SERCOM_1_USART_BAUD) / CONF_GCLK_SERCOM1_CORE_FREQUENCY)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_1_USART_CMODE == 1</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+// Calculate BAUD register value in USRT mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_BAUD_RATE (CONF_GCLK_SERCOM1_CORE_FREQUENCY) / (2 * CONF_SERCOM_1_USART_BAUD) - 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_1_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+#error CMODE value for SERCOM 1 in USART mode not known</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <peripheral_clk_config.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_ENABLE 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <h> Basic Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Receive buffer enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Enable input buffer in SERCOM module</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_rx_enable</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_RXEN</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_RXEN 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Transmitt buffer enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Enable output buffer in SERCOM module</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_tx_enable</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_TXEN</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_TXEN 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Frame parity</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=>Even parity</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Parity bit mode for USART frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_parity</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_PARITY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_PARITY 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Character Size</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=>8 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=>9 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x5=>5 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x6=>6 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x7=>7 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Data character size in USART frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_character_size</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_CHSIZE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_CHSIZE 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Stop Bit</span><br><span style="color: hsl(120, 100%, 40%);">+// <0=>One stop bit</span><br><span style="color: hsl(120, 100%, 40%);">+// <1=>Two stop bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Number of stop bits in USART frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_stop_bit</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_SBMODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_SBMODE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Baud rate <1-3000000></span><br><span style="color: hsl(120, 100%, 40%);">+// <i> USART baud rate setting</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_baud_rate</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_BAUD</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_BAUD 9600</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+// </h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <h> ISO7816 configuration</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Protocol Type</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=> T=0</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=> T=1</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define ISO7816 protocol type as 0.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_iso7816_type</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_ISO7816_PROTOCOL_T</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_ISO7816_PROTOCOL_T 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Inhibit Not Acknowledge</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=> NACK is transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=> NACK is not transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define whether a NACK is transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_inack</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_INACK</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_INACK 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Disable Successive Not Acknowledge</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=> The successive receive NACK is disable.</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=> The successive receive NACK is enable.</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define whether NACK will be sent on parity error reception.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_dsnack</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_DSNACK</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_DSNACK 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Maximum Iterations<0-7></span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define the maximum number of retransmit iterations.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_maxiter</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_MAXITER</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_MAXITER 0x7</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Guard Time</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x2=> 2-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x3=> 3-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x4=> 4-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x5=> 5-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x6=> 6-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x7=> 7-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define the guard time.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_gtime</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_GTIME</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_GTIME 0x2</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Inverse transmission and reception enabled</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define inverse transmission and reception enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_inverse_enabled</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_INVERSE_ENABLED</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_INVERSE_ENABLED 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if (CONF_SERCOM_2_USART_INVERSE_ENABLED == 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_RXINV 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_TXINV 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_RXINV 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_TXINV 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// </h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <e> Advanced configuration</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_advanced</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Run in stand-by</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Keep the module running in standby sleep mode</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_runstdby</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_RUNSTDBY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_RUNSTDBY 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Immediate Buffer Overflow Notification</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Controls when the BUFOVF status bit is asserted</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_ibon</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_IBON</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_IBON 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Start of Frame Detection Enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_sfde</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_SFDE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_SFDE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Collision Detection Enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Collision detection enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_cloden</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_CLODEN</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_CLODEN 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Operating Mode</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=>USART with internal clock</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Drive the shift register by an internal clock generated by the baud rate generator.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_clock_mode</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_MODE 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Data Order</span><br><span style="color: hsl(120, 100%, 40%);">+// <0=>MSB is transmitted first</span><br><span style="color: hsl(120, 100%, 40%);">+// <1=>LSB is transmitted first</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Data order of the data bits in the frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_dord</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_DORD</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_DORD 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Debug Stop Mode</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.</span><br><span style="color: hsl(120, 100%, 40%);">+// <0=>Keep running</span><br><span style="color: hsl(120, 100%, 40%);">+// <1=>Halt</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_dbgstop</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Does not do anything in USRT mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_SAMPR 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_SAMPA 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_FRACTIONAL 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Does not do anything in UART mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_CPOL 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Does not do anything in USRT mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_ENC 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// </e></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_CMODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_CMODE CONF_SERCOM_2_USART_ISO7816_PROTOCOL_T</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* RX is on PIN_PA09 */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_RXPO</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_RXPO 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* TX uses the same pin with RX */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_TXPO</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_TXPO 2</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Set iso7816 mode */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_PMODE (CONF_SERCOM_2_USART_PARITY - 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_FORM 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if CONF_SERCOM_2_USART_CMODE == 0</span><br><span style="color: hsl(120, 100%, 40%);">+// Calculate BAUD register value in UART mode</span><br><span style="color: hsl(120, 100%, 40%);">+#if CONF_SERCOM_2_USART_SAMPR == 0</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_2_USART_SAMPR == 1</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_2_USART_SAMPR == 2</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_2_USART_SAMPR == 3</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_2_USART_SAMPR == 4</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_2_USART_CMODE == 1</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+// Calculate BAUD register value in USRT mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_BAUD_RATE (CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (2 * CONF_SERCOM_2_USART_BAUD) - 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+#error CMODE value for SERCOM 2 in USART mode not known</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <peripheral_clk_config.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_ENABLE 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <h> Basic Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Receive buffer enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Enable input buffer in SERCOM module</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_rx_enable</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_RXEN</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_RXEN 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Transmitt buffer enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Enable output buffer in SERCOM module</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_tx_enable</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_TXEN</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_TXEN 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Frame parity</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=>Even parity</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Parity bit mode for USART frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_parity</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_PARITY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_PARITY 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Character Size</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=>8 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=>9 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x5=>5 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x6=>6 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x7=>7 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Data character size in USART frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_character_size</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_CHSIZE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_CHSIZE 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Stop Bit</span><br><span style="color: hsl(120, 100%, 40%);">+// <0=>One stop bit</span><br><span style="color: hsl(120, 100%, 40%);">+// <1=>Two stop bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Number of stop bits in USART frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_stop_bit</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_SBMODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_SBMODE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Baud rate <1-3000000></span><br><span style="color: hsl(120, 100%, 40%);">+// <i> USART baud rate setting</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_baud_rate</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_BAUD</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_BAUD 9600</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+// </h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <h> ISO7816 configuration</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Protocol Type</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=> T=0</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=> T=1</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define ISO7816 protocol type as 0.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_iso7816_type</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_ISO7816_PROTOCOL_T</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_ISO7816_PROTOCOL_T 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Inhibit Not Acknowledge</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=> NACK is transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=> NACK is not transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define whether a NACK is transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_inack</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_INACK</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_INACK 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Disable Successive Not Acknowledge</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=> The successive receive NACK is disable.</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=> The successive receive NACK is enable.</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define whether NACK will be sent on parity error reception.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_dsnack</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_DSNACK</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_DSNACK 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Maximum Iterations<0-7></span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define the maximum number of retransmit iterations.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_maxiter</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_MAXITER</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_MAXITER 0x7</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Guard Time</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x2=> 2-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x3=> 3-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x4=> 4-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x5=> 5-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x6=> 6-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x7=> 7-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define the guard time.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_gtime</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_GTIME</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_GTIME 0x2</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Inverse transmission and reception enabled</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define inverse transmission and reception enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_inverse_enabled</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_INVERSE_ENABLED</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_INVERSE_ENABLED 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if (CONF_SERCOM_3_USART_INVERSE_ENABLED == 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_RXINV 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_TXINV 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_RXINV 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_TXINV 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// </h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <e> Advanced configuration</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_advanced</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_ADVANCED_CONFIG</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_ADVANCED_CONFIG 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Run in stand-by</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Keep the module running in standby sleep mode</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_runstdby</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_RUNSTDBY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_RUNSTDBY 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Immediate Buffer Overflow Notification</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Controls when the BUFOVF status bit is asserted</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_ibon</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_IBON</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_IBON 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Start of Frame Detection Enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_sfde</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_SFDE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_SFDE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Collision Detection Enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Collision detection enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_cloden</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_CLODEN</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_CLODEN 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Operating Mode</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=>USART with internal clock</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Drive the shift register by an internal clock generated by the baud rate generator.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_clock_mode</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_MODE 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Data Order</span><br><span style="color: hsl(120, 100%, 40%);">+// <0=>MSB is transmitted first</span><br><span style="color: hsl(120, 100%, 40%);">+// <1=>LSB is transmitted first</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Data order of the data bits in the frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_dord</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_DORD</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_DORD 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Debug Stop Mode</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.</span><br><span style="color: hsl(120, 100%, 40%);">+// <0=>Keep running</span><br><span style="color: hsl(120, 100%, 40%);">+// <1=>Halt</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_dbgstop</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_DEBUG_STOP_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_DEBUG_STOP_MODE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Does not do anything in USRT mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_SAMPR 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_SAMPA 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_FRACTIONAL 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Does not do anything in UART mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_CPOL 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Does not do anything in USRT mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_ENC 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// </e></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_CMODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_CMODE CONF_SERCOM_3_USART_ISO7816_PROTOCOL_T</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* RX is on PIN_PB20 */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_RXPO</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_RXPO 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* TX uses the same pin with RX */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_TXPO</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_TXPO 2</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Set iso7816 mode */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_PMODE (CONF_SERCOM_3_USART_PARITY - 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_FORM 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if CONF_SERCOM_3_USART_CMODE == 0</span><br><span style="color: hsl(120, 100%, 40%);">+// Calculate BAUD register value in UART mode</span><br><span style="color: hsl(120, 100%, 40%);">+#if CONF_SERCOM_3_USART_SAMPR == 0</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ 65536 - ((65536 * 16.0f * CONF_SERCOM_3_USART_BAUD) / CONF_GCLK_SERCOM3_CORE_FREQUENCY)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_3_USART_SAMPR == 1</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ ((CONF_GCLK_SERCOM3_CORE_FREQUENCY) / (CONF_SERCOM_3_USART_BAUD * 16)) - (CONF_SERCOM_3_USART_FRACTIONAL / 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_3_USART_SAMPR == 2</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ 65536 - ((65536 * 8.0f * CONF_SERCOM_3_USART_BAUD) / CONF_GCLK_SERCOM3_CORE_FREQUENCY)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_3_USART_SAMPR == 3</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ ((CONF_GCLK_SERCOM3_CORE_FREQUENCY) / (CONF_SERCOM_3_USART_BAUD * 8)) - (CONF_SERCOM_3_USART_FRACTIONAL / 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_3_USART_SAMPR == 4</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ 65536 - ((65536 * 3.0f * CONF_SERCOM_3_USART_BAUD) / CONF_GCLK_SERCOM3_CORE_FREQUENCY)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_3_USART_CMODE == 1</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+// Calculate BAUD register value in USRT mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_BAUD_RATE (CONF_GCLK_SERCOM3_CORE_FREQUENCY) / (2 * CONF_SERCOM_3_USART_BAUD) - 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_3_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+#error CMODE value for SERCOM 3 in USART mode not known</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <peripheral_clk_config.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_ENABLE 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <h> Basic Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Receive buffer enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Enable input buffer in SERCOM module</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_rx_enable</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_RXEN</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_RXEN 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Transmitt buffer enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Enable output buffer in SERCOM module</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_tx_enable</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_TXEN</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_TXEN 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Frame parity</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=>Even parity</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Parity bit mode for USART frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_parity</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_PARITY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_PARITY 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Character Size</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=>8 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=>9 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x5=>5 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x6=>6 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x7=>7 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Data character size in USART frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_character_size</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_CHSIZE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_CHSIZE 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Stop Bit</span><br><span style="color: hsl(120, 100%, 40%);">+// <0=>One stop bit</span><br><span style="color: hsl(120, 100%, 40%);">+// <1=>Two stop bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Number of stop bits in USART frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_stop_bit</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_SBMODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_SBMODE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Baud rate <1-3000000></span><br><span style="color: hsl(120, 100%, 40%);">+// <i> USART baud rate setting</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_baud_rate</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_BAUD</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_BAUD 9600</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+// </h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <h> ISO7816 configuration</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Protocol Type</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=> T=0</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=> T=1</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define ISO7816 protocol type as 0.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_iso7816_type</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_ISO7816_PROTOCOL_T</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_ISO7816_PROTOCOL_T 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Inhibit Not Acknowledge</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=> NACK is transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=> NACK is not transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define whether a NACK is transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_inack</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_INACK</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_INACK 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Disable Successive Not Acknowledge</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=> The successive receive NACK is disable.</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=> The successive receive NACK is enable.</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define whether NACK will be sent on parity error reception.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_dsnack</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_DSNACK</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_DSNACK 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Maximum Iterations<0-7></span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define the maximum number of retransmit iterations.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_maxiter</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_MAXITER</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_MAXITER 0x7</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Guard Time</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x2=> 2-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x3=> 3-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x4=> 4-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x5=> 5-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x6=> 6-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x7=> 7-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define the guard time.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_gtime</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_GTIME</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_GTIME 0x2</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Inverse transmission and reception enabled</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define inverse transmission and reception enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_inverse_enabled</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_INVERSE_ENABLED</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_INVERSE_ENABLED 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if (CONF_SERCOM_4_USART_INVERSE_ENABLED == 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_RXINV 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_TXINV 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_RXINV 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_TXINV 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// </h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <e> Advanced configuration</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_advanced</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_ADVANCED_CONFIG</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_ADVANCED_CONFIG 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Run in stand-by</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Keep the module running in standby sleep mode</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_runstdby</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_RUNSTDBY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_RUNSTDBY 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Immediate Buffer Overflow Notification</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Controls when the BUFOVF status bit is asserted</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_ibon</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_IBON</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_IBON 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Start of Frame Detection Enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_sfde</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_SFDE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_SFDE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Collision Detection Enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Collision detection enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_cloden</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_CLODEN</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_CLODEN 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Operating Mode</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=>USART with internal clock</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Drive the shift register by an internal clock generated by the baud rate generator.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_clock_mode</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_MODE 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Data Order</span><br><span style="color: hsl(120, 100%, 40%);">+// <0=>MSB is transmitted first</span><br><span style="color: hsl(120, 100%, 40%);">+// <1=>LSB is transmitted first</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Data order of the data bits in the frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_dord</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_DORD</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_DORD 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Debug Stop Mode</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.</span><br><span style="color: hsl(120, 100%, 40%);">+// <0=>Keep running</span><br><span style="color: hsl(120, 100%, 40%);">+// <1=>Halt</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_dbgstop</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_DEBUG_STOP_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_DEBUG_STOP_MODE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Does not do anything in USRT mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_SAMPR 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_SAMPA 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_FRACTIONAL 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Does not do anything in UART mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_CPOL 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Does not do anything in USRT mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_ENC 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// </e></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_CMODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_CMODE CONF_SERCOM_4_USART_ISO7816_PROTOCOL_T</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* RX is on PIN_PB08 */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_RXPO</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_RXPO 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* TX uses the same pin with RX */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_TXPO</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_TXPO 2</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Set iso7816 mode */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_PMODE (CONF_SERCOM_4_USART_PARITY - 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_FORM 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if CONF_SERCOM_4_USART_CMODE == 0</span><br><span style="color: hsl(120, 100%, 40%);">+// Calculate BAUD register value in UART mode</span><br><span style="color: hsl(120, 100%, 40%);">+#if CONF_SERCOM_4_USART_SAMPR == 0</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ 65536 - ((65536 * 16.0f * CONF_SERCOM_4_USART_BAUD) / CONF_GCLK_SERCOM4_CORE_FREQUENCY)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_4_USART_SAMPR == 1</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ ((CONF_GCLK_SERCOM4_CORE_FREQUENCY) / (CONF_SERCOM_4_USART_BAUD * 16)) - (CONF_SERCOM_4_USART_FRACTIONAL / 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_4_USART_SAMPR == 2</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ 65536 - ((65536 * 8.0f * CONF_SERCOM_4_USART_BAUD) / CONF_GCLK_SERCOM4_CORE_FREQUENCY)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_4_USART_SAMPR == 3</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ ((CONF_GCLK_SERCOM4_CORE_FREQUENCY) / (CONF_SERCOM_4_USART_BAUD * 8)) - (CONF_SERCOM_4_USART_FRACTIONAL / 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_4_USART_SAMPR == 4</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ 65536 - ((65536 * 3.0f * CONF_SERCOM_4_USART_BAUD) / CONF_GCLK_SERCOM4_CORE_FREQUENCY)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_4_USART_CMODE == 1</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+// Calculate BAUD register value in USRT mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_BAUD_RATE (CONF_GCLK_SERCOM4_CORE_FREQUENCY) / (2 * CONF_SERCOM_4_USART_BAUD) - 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_4_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+#error CMODE value for SERCOM 4 in USART mode not known</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <peripheral_clk_config.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_ENABLE 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <h> Basic Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Receive buffer enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Enable input buffer in SERCOM module</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_rx_enable</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_RXEN</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_RXEN 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Transmitt buffer enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Enable output buffer in SERCOM module</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_tx_enable</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_TXEN</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_TXEN 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Frame parity</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=>Even parity</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Parity bit mode for USART frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_parity</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_PARITY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_PARITY 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Character Size</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=>8 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=>9 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x5=>5 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x6=>6 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x7=>7 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Data character size in USART frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_character_size</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_CHSIZE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_CHSIZE 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Stop Bit</span><br><span style="color: hsl(120, 100%, 40%);">+// <0=>One stop bit</span><br><span style="color: hsl(120, 100%, 40%);">+// <1=>Two stop bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Number of stop bits in USART frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_stop_bit</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_SBMODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_SBMODE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Baud rate <1-3000000></span><br><span style="color: hsl(120, 100%, 40%);">+// <i> USART baud rate setting</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_baud_rate</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_BAUD</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_BAUD 9600</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+// </h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <h> ISO7816 configuration</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Protocol Type</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=> T=0</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=> T=1</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define ISO7816 protocol type as 0.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_iso7816_type</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_ISO7816_PROTOCOL_T</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_ISO7816_PROTOCOL_T 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Inhibit Not Acknowledge</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=> NACK is transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=> NACK is not transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define whether a NACK is transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_inack</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_INACK</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_INACK 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Disable Successive Not Acknowledge</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=> The successive receive NACK is disable.</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=> The successive receive NACK is enable.</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define whether NACK will be sent on parity error reception.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_dsnack</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_DSNACK</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_DSNACK 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Maximum Iterations<0-7></span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define the maximum number of retransmit iterations.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_maxiter</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_MAXITER</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_MAXITER 0x7</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Guard Time</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x2=> 2-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x3=> 3-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x4=> 4-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x5=> 5-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x6=> 6-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x7=> 7-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define the guard time.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_gtime</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_GTIME</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_GTIME 0x2</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Inverse transmission and reception enabled</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define inverse transmission and reception enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_inverse_enabled</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_INVERSE_ENABLED</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_INVERSE_ENABLED 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if (CONF_SERCOM_5_USART_INVERSE_ENABLED == 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_RXINV 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_TXINV 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_RXINV 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_TXINV 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// </h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <e> Advanced configuration</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_advanced</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_ADVANCED_CONFIG</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_ADVANCED_CONFIG 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Run in stand-by</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Keep the module running in standby sleep mode</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_runstdby</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_RUNSTDBY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_RUNSTDBY 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Immediate Buffer Overflow Notification</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Controls when the BUFOVF status bit is asserted</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_ibon</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_IBON</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_IBON 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Start of Frame Detection Enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_sfde</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_SFDE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_SFDE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Collision Detection Enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Collision detection enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_cloden</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_CLODEN</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_CLODEN 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Operating Mode</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=>USART with internal clock</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Drive the shift register by an internal clock generated by the baud rate generator.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_clock_mode</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_MODE 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Data Order</span><br><span style="color: hsl(120, 100%, 40%);">+// <0=>MSB is transmitted first</span><br><span style="color: hsl(120, 100%, 40%);">+// <1=>LSB is transmitted first</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Data order of the data bits in the frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_dord</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_DORD</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_DORD 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Debug Stop Mode</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.</span><br><span style="color: hsl(120, 100%, 40%);">+// <0=>Keep running</span><br><span style="color: hsl(120, 100%, 40%);">+// <1=>Halt</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_dbgstop</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_DEBUG_STOP_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_DEBUG_STOP_MODE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Does not do anything in USRT mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_SAMPR 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_SAMPA 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_FRACTIONAL 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Does not do anything in UART mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_CPOL 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Does not do anything in USRT mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_ENC 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// </e></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_CMODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_CMODE CONF_SERCOM_5_USART_ISO7816_PROTOCOL_T</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* RX is on PIN_PB16 */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_RXPO</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_RXPO 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* TX uses the same pin with RX */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_TXPO</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_TXPO 2</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Set iso7816 mode */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_PMODE (CONF_SERCOM_5_USART_PARITY - 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_FORM 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if CONF_SERCOM_5_USART_CMODE == 0</span><br><span style="color: hsl(120, 100%, 40%);">+// Calculate BAUD register value in UART mode</span><br><span style="color: hsl(120, 100%, 40%);">+#if CONF_SERCOM_5_USART_SAMPR == 0</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ 65536 - ((65536 * 16.0f * CONF_SERCOM_5_USART_BAUD) / CONF_GCLK_SERCOM5_CORE_FREQUENCY)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_5_USART_SAMPR == 1</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ ((CONF_GCLK_SERCOM5_CORE_FREQUENCY) / (CONF_SERCOM_5_USART_BAUD * 16)) - (CONF_SERCOM_5_USART_FRACTIONAL / 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_5_USART_SAMPR == 2</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ 65536 - ((65536 * 8.0f * CONF_SERCOM_5_USART_BAUD) / CONF_GCLK_SERCOM5_CORE_FREQUENCY)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_5_USART_SAMPR == 3</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ ((CONF_GCLK_SERCOM5_CORE_FREQUENCY) / (CONF_SERCOM_5_USART_BAUD * 8)) - (CONF_SERCOM_5_USART_FRACTIONAL / 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_5_USART_SAMPR == 4</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ 65536 - ((65536 * 3.0f * CONF_SERCOM_5_USART_BAUD) / CONF_GCLK_SERCOM5_CORE_FREQUENCY)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_5_USART_CMODE == 1</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+// Calculate BAUD register value in USRT mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_BAUD_RATE (CONF_GCLK_SERCOM5_CORE_FREQUENCY) / (2 * CONF_SERCOM_5_USART_BAUD) - 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_5_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+#error CMODE value for SERCOM 5 in USART mode not known</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <peripheral_clk_config.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_ENABLE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_ENABLE 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <h> Basic Configuration</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Receive buffer enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Enable input buffer in SERCOM module</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_rx_enable</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_RXEN</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_RXEN 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Transmitt buffer enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Enable output buffer in SERCOM module</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_tx_enable</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_TXEN</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_TXEN 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Frame parity</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=>Even parity</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Parity bit mode for USART frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_parity</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_PARITY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_PARITY 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Character Size</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=>8 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=>9 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x5=>5 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x6=>6 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x7=>7 bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Data character size in USART frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_character_size</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_CHSIZE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_CHSIZE 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Stop Bit</span><br><span style="color: hsl(120, 100%, 40%);">+// <0=>One stop bit</span><br><span style="color: hsl(120, 100%, 40%);">+// <1=>Two stop bits</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Number of stop bits in USART frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_stop_bit</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_SBMODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_SBMODE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Baud rate <1-3000000></span><br><span style="color: hsl(120, 100%, 40%);">+// <i> USART baud rate setting</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_baud_rate</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_BAUD</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_BAUD 9600</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+// </h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <h> ISO7816 configuration</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Protocol Type</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=> T=0</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=> T=1</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define ISO7816 protocol type as 0.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_iso7816_type</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_ISO7816_PROTOCOL_T</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_ISO7816_PROTOCOL_T 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Inhibit Not Acknowledge</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=> NACK is transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=> NACK is not transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define whether a NACK is transmitted when a parity error is received.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_inack</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_INACK</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_INACK 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Disable Successive Not Acknowledge</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x0=> The successive receive NACK is disable.</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=> The successive receive NACK is enable.</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define whether NACK will be sent on parity error reception.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_dsnack</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_DSNACK</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_DSNACK 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Maximum Iterations<0-7></span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define the maximum number of retransmit iterations.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_maxiter</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_MAXITER</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_MAXITER 0x7</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> ISO7816 Guard Time</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x2=> 2-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x3=> 3-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x4=> 4-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x5=> 5-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x6=> 6-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x7=> 7-bit times</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define the guard time.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_gtime</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_GTIME</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_GTIME 0x2</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Inverse transmission and reception enabled</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Define inverse transmission and reception enabled.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_inverse_enabled</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_INVERSE_ENABLED</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_INVERSE_ENABLED 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if (CONF_SERCOM_6_USART_INVERSE_ENABLED == 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_RXINV 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_TXINV 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_RXINV 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_TXINV 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// </h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <e> Advanced configuration</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_advanced</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_ADVANCED_CONFIG</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_ADVANCED_CONFIG 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Run in stand-by</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Keep the module running in standby sleep mode</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_runstdby</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_RUNSTDBY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_RUNSTDBY 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Immediate Buffer Overflow Notification</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Controls when the BUFOVF status bit is asserted</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_ibon</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_IBON</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_IBON 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Start of Frame Detection Enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled)</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_sfde</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_SFDE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_SFDE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <q> Collision Detection Enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Collision detection enable</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_cloden</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_CLODEN</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_CLODEN 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Operating Mode</span><br><span style="color: hsl(120, 100%, 40%);">+// <0x1=>USART with internal clock</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Drive the shift register by an internal clock generated by the baud rate generator.</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_clock_mode</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_MODE 0x1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Data Order</span><br><span style="color: hsl(120, 100%, 40%);">+// <0=>MSB is transmitted first</span><br><span style="color: hsl(120, 100%, 40%);">+// <1=>LSB is transmitted first</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Data order of the data bits in the frame</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_dord</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_DORD</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_DORD 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <o> Debug Stop Mode</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.</span><br><span style="color: hsl(120, 100%, 40%);">+// <0=>Keep running</span><br><span style="color: hsl(120, 100%, 40%);">+// <1=>Halt</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> usart_arch_dbgstop</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_DEBUG_STOP_MODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_DEBUG_STOP_MODE 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Does not do anything in USRT mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_SAMPR 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_SAMPA 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_FRACTIONAL 0x0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Does not do anything in UART mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_CPOL 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// Does not do anything in USRT mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_ENC 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// </e></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_CMODE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_CMODE CONF_SERCOM_6_USART_ISO7816_PROTOCOL_T</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* RX is on PIN_PC16 */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_RXPO</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_RXPO 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* TX uses the same pin with RX */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_TXPO</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_TXPO 2</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/* Set iso7816 mode */</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_PMODE (CONF_SERCOM_6_USART_PARITY - 1)</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_FORM 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#if CONF_SERCOM_6_USART_CMODE == 0</span><br><span style="color: hsl(120, 100%, 40%);">+// Calculate BAUD register value in UART mode</span><br><span style="color: hsl(120, 100%, 40%);">+#if CONF_SERCOM_6_USART_SAMPR == 0</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ 65536 - ((65536 * 16.0f * CONF_SERCOM_6_USART_BAUD) / CONF_GCLK_SERCOM6_CORE_FREQUENCY)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_6_USART_SAMPR == 1</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ ((CONF_GCLK_SERCOM6_CORE_FREQUENCY) / (CONF_SERCOM_6_USART_BAUD * 16)) - (CONF_SERCOM_6_USART_FRACTIONAL / 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_6_USART_SAMPR == 2</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ 65536 - ((65536 * 8.0f * CONF_SERCOM_6_USART_BAUD) / CONF_GCLK_SERCOM6_CORE_FREQUENCY)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_6_USART_SAMPR == 3</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ ((CONF_GCLK_SERCOM6_CORE_FREQUENCY) / (CONF_SERCOM_6_USART_BAUD * 8)) - (CONF_SERCOM_6_USART_FRACTIONAL / 8)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_6_USART_SAMPR == 4</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_BAUD_RATE \</span><br><span style="color: hsl(120, 100%, 40%);">+ 65536 - ((65536 * 3.0f * CONF_SERCOM_6_USART_BAUD) / CONF_GCLK_SERCOM6_CORE_FREQUENCY)</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#elif CONF_SERCOM_6_USART_CMODE == 1</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_BAUD_RATE</span><br><span style="color: hsl(120, 100%, 40%);">+// Calculate BAUD register value in USRT mode</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_BAUD_RATE (CONF_GCLK_SERCOM6_CORE_FREQUENCY) / (2 * CONF_SERCOM_6_USART_BAUD) - 1</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_SERCOM_6_USART_RECEIVE_PULSE_LENGTH 0</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+#else</span><br><span style="color: hsl(120, 100%, 40%);">+#error CMODE value for SERCOM 6 in USART mode not known</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+#include <peripheral_clk_config.h></span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> #ifndef CONF_SERCOM_7_USART_ENABLE</span><br><span> #define CONF_SERCOM_7_USART_ENABLE 1</span><br><span> #endif</span><br><span>diff --git a/sysmoOCTSIM/config/peripheral_clk_config.h b/sysmoOCTSIM/config/peripheral_clk_config.h</span><br><span>index ce68abd..91c5c86 100644</span><br><span>--- a/sysmoOCTSIM/config/peripheral_clk_config.h</span><br><span>+++ b/sysmoOCTSIM/config/peripheral_clk_config.h</span><br><span>@@ -40,6 +40,566 @@</span><br><span> // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11</span><br><span> </span><br><span> // <i> Select the clock source for CORE.</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM0_CORE_SRC</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <y> Slow Clock Source</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> slow_gclk_selection</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Select the slow clock source.</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM0_SLOW_SRC</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief SERCOM0's Core Clock frequency</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 100000000</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief SERCOM0's Slow Clock frequency</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <y> Core Clock Source</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> core_gclk_selection</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Select the clock source for CORE.</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM1_CORE_SRC</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <y> Slow Clock Source</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> slow_gclk_selection</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Select the slow clock source.</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM1_SLOW_SRC</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief SERCOM1's Core Clock frequency</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 100000000</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief SERCOM1's Slow Clock frequency</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <y> Core Clock Source</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> core_gclk_selection</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Select the clock source for CORE.</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM2_CORE_SRC</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <y> Slow Clock Source</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> slow_gclk_selection</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Select the slow clock source.</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM2_SLOW_SRC</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief SERCOM2's Core Clock frequency</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 100000000</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief SERCOM2's Slow Clock frequency</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <y> Core Clock Source</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> core_gclk_selection</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Select the clock source for CORE.</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM3_CORE_SRC</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <y> Slow Clock Source</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> slow_gclk_selection</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Select the slow clock source.</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM3_SLOW_SRC</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \def CONF_GCLK_SERCOM3_CORE_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief SERCOM3's Core Clock frequency</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 100000000</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief SERCOM3's Slow Clock frequency</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <y> Core Clock Source</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> core_gclk_selection</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Select the clock source for CORE.</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM4_CORE_SRC</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM4_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <y> Slow Clock Source</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> slow_gclk_selection</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Select the slow clock source.</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM4_SLOW_SRC</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM4_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \def CONF_GCLK_SERCOM4_CORE_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief SERCOM4's Core Clock frequency</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM4_CORE_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 100000000</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \def CONF_GCLK_SERCOM4_SLOW_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief SERCOM4's Slow Clock frequency</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM4_SLOW_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM4_SLOW_FREQUENCY 32768</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <y> Core Clock Source</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> core_gclk_selection</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Select the clock source for CORE.</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM5_CORE_SRC</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM5_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <y> Slow Clock Source</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> slow_gclk_selection</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Select the slow clock source.</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM5_SLOW_SRC</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM5_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \def CONF_GCLK_SERCOM5_CORE_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief SERCOM5's Core Clock frequency</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM5_CORE_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 100000000</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \def CONF_GCLK_SERCOM5_SLOW_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief SERCOM5's Slow Clock frequency</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM5_SLOW_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM5_SLOW_FREQUENCY 32768</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <y> Core Clock Source</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> core_gclk_selection</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Select the clock source for CORE.</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM6_CORE_SRC</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM6_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <y> Slow Clock Source</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> slow_gclk_selection</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Select the slow clock source.</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM6_SLOW_SRC</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM6_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \def CONF_GCLK_SERCOM6_CORE_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief SERCOM6's Core Clock frequency</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM6_CORE_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM6_CORE_FREQUENCY 100000000</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \def CONF_GCLK_SERCOM6_SLOW_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief SERCOM6's Slow Clock frequency</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+#ifndef CONF_GCLK_SERCOM6_SLOW_FREQUENCY</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM6_SLOW_FREQUENCY 32768</span><br><span style="color: hsl(120, 100%, 40%);">+#endif</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <y> Core Clock Source</span><br><span style="color: hsl(120, 100%, 40%);">+// <id> core_gclk_selection</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+// <i> Select the clock source for CORE.</span><br><span> #ifndef CONF_GCLK_SERCOM7_CORE_SRC</span><br><span> #define CONF_GCLK_SERCOM7_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val</span><br><span> #endif</span><br><span>diff --git a/sysmoOCTSIM/driver_init.c b/sysmoOCTSIM/driver_init.c</span><br><span>index 4ab622f..a196791 100644</span><br><span>--- a/sysmoOCTSIM/driver_init.c</span><br><span>+++ b/sysmoOCTSIM/driver_init.c</span><br><span>@@ -12,10 +12,45 @@</span><br><span> #include <hal_init.h></span><br><span> </span><br><span> /*! The buffer size for USART */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SIM0_BUFFER_SIZE 16</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*! The buffer size for USART */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SIM1_BUFFER_SIZE 16</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*! The buffer size for USART */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SIM2_BUFFER_SIZE 16</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*! The buffer size for USART */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SIM3_BUFFER_SIZE 16</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*! The buffer size for USART */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SIM4_BUFFER_SIZE 16</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*! The buffer size for USART */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SIM5_BUFFER_SIZE 16</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*! The buffer size for USART */</span><br><span style="color: hsl(120, 100%, 40%);">+#define SIM6_BUFFER_SIZE 16</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/*! The buffer size for USART */</span><br><span> #define UART_DEBUG_BUFFER_SIZE 16</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+struct usart_async_descriptor SIM0;</span><br><span style="color: hsl(120, 100%, 40%);">+struct usart_async_descriptor SIM1;</span><br><span style="color: hsl(120, 100%, 40%);">+struct usart_async_descriptor SIM2;</span><br><span style="color: hsl(120, 100%, 40%);">+struct usart_async_descriptor SIM3;</span><br><span style="color: hsl(120, 100%, 40%);">+struct usart_async_descriptor SIM4;</span><br><span style="color: hsl(120, 100%, 40%);">+struct usart_async_descriptor SIM5;</span><br><span style="color: hsl(120, 100%, 40%);">+struct usart_async_descriptor SIM6;</span><br><span> struct usart_async_descriptor UART_debug;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static uint8_t SIM0_buffer[SIM0_BUFFER_SIZE];</span><br><span style="color: hsl(120, 100%, 40%);">+static uint8_t SIM1_buffer[SIM1_BUFFER_SIZE];</span><br><span style="color: hsl(120, 100%, 40%);">+static uint8_t SIM2_buffer[SIM2_BUFFER_SIZE];</span><br><span style="color: hsl(120, 100%, 40%);">+static uint8_t SIM3_buffer[SIM3_BUFFER_SIZE];</span><br><span style="color: hsl(120, 100%, 40%);">+static uint8_t SIM4_buffer[SIM4_BUFFER_SIZE];</span><br><span style="color: hsl(120, 100%, 40%);">+static uint8_t SIM5_buffer[SIM5_BUFFER_SIZE];</span><br><span style="color: hsl(120, 100%, 40%);">+static uint8_t SIM6_buffer[SIM6_BUFFER_SIZE];</span><br><span> static uint8_t UART_debug_buffer[UART_DEBUG_BUFFER_SIZE];</span><br><span> </span><br><span> /**</span><br><span>@@ -23,6 +58,265 @@</span><br><span> *</span><br><span> * Enables register interface and peripheral clock</span><br><span> */</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM0_CLOCK_init()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));</span><br><span style="color: hsl(120, 100%, 40%);">+ hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ hri_mclk_set_APBAMASK_SERCOM0_bit(MCLK);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief USART pinmux initialization function</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set each required pin to USART functionality</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM0_PORT_init()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_pin_function(SIM0_IO, PINMUX_PA04D_SERCOM0_PAD0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief USART initialization function</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enables USART peripheral, clocks and initializes USART driver</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM0_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM0_CLOCK_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_init(&SIM0, SERCOM0, SIM0_buffer, SIM0_BUFFER_SIZE, (void *)NULL);</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM0_PORT_init();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief USART Clock initialization function</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enables register interface and peripheral clock</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM1_CLOCK_init()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_CORE, CONF_GCLK_SERCOM1_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));</span><br><span style="color: hsl(120, 100%, 40%);">+ hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_SLOW, CONF_GCLK_SERCOM1_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ hri_mclk_set_APBAMASK_SERCOM1_bit(MCLK);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief USART pinmux initialization function</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set each required pin to USART functionality</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM1_PORT_init()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_pin_function(SIM1_IO, PINMUX_PA16C_SERCOM1_PAD0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief USART initialization function</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enables USART peripheral, clocks and initializes USART driver</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM1_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM1_CLOCK_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_init(&SIM1, SERCOM1, SIM1_buffer, SIM1_BUFFER_SIZE, (void *)NULL);</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM1_PORT_init();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief USART Clock initialization function</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enables register interface and peripheral clock</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM2_CLOCK_init()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));</span><br><span style="color: hsl(120, 100%, 40%);">+ hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief USART pinmux initialization function</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set each required pin to USART functionality</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM2_PORT_init()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_pin_function(SIM2_IO, PINMUX_PA09D_SERCOM2_PAD0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief USART initialization function</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enables USART peripheral, clocks and initializes USART driver</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM2_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM2_CLOCK_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_init(&SIM2, SERCOM2, SIM2_buffer, SIM2_BUFFER_SIZE, (void *)NULL);</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM2_PORT_init();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief USART Clock initialization function</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enables register interface and peripheral clock</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM3_CLOCK_init()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_CORE, CONF_GCLK_SERCOM3_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));</span><br><span style="color: hsl(120, 100%, 40%);">+ hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_SLOW, CONF_GCLK_SERCOM3_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ hri_mclk_set_APBBMASK_SERCOM3_bit(MCLK);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief USART pinmux initialization function</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set each required pin to USART functionality</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM3_PORT_init()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_pin_function(SIM3_IO, PINMUX_PB20C_SERCOM3_PAD0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief USART initialization function</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enables USART peripheral, clocks and initializes USART driver</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM3_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM3_CLOCK_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_init(&SIM3, SERCOM3, SIM3_buffer, SIM3_BUFFER_SIZE, (void *)NULL);</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM3_PORT_init();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief USART Clock initialization function</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enables register interface and peripheral clock</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM4_CLOCK_init()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_CORE, CONF_GCLK_SERCOM4_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));</span><br><span style="color: hsl(120, 100%, 40%);">+ hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_SLOW, CONF_GCLK_SERCOM4_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ hri_mclk_set_APBDMASK_SERCOM4_bit(MCLK);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief USART pinmux initialization function</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set each required pin to USART functionality</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM4_PORT_init()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_pin_function(SIM4_IO, PINMUX_PB08D_SERCOM4_PAD0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief USART initialization function</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enables USART peripheral, clocks and initializes USART driver</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM4_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM4_CLOCK_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_init(&SIM4, SERCOM4, SIM4_buffer, SIM4_BUFFER_SIZE, (void *)NULL);</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM4_PORT_init();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief USART Clock initialization function</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enables register interface and peripheral clock</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM5_CLOCK_init()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM5_GCLK_ID_CORE, CONF_GCLK_SERCOM5_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));</span><br><span style="color: hsl(120, 100%, 40%);">+ hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM5_GCLK_ID_SLOW, CONF_GCLK_SERCOM5_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ hri_mclk_set_APBDMASK_SERCOM5_bit(MCLK);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief USART pinmux initialization function</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set each required pin to USART functionality</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM5_PORT_init()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_pin_function(SIM5_IO, PINMUX_PB16C_SERCOM5_PAD0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief USART initialization function</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enables USART peripheral, clocks and initializes USART driver</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM5_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM5_CLOCK_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_init(&SIM5, SERCOM5, SIM5_buffer, SIM5_BUFFER_SIZE, (void *)NULL);</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM5_PORT_init();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief USART Clock initialization function</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enables register interface and peripheral clock</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM6_CLOCK_init()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM6_GCLK_ID_CORE, CONF_GCLK_SERCOM6_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));</span><br><span style="color: hsl(120, 100%, 40%);">+ hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM6_GCLK_ID_SLOW, CONF_GCLK_SERCOM6_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ hri_mclk_set_APBDMASK_SERCOM6_bit(MCLK);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief USART pinmux initialization function</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Set each required pin to USART functionality</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM6_PORT_init()</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ gpio_set_pin_function(SIM6_IO, PINMUX_PC16C_SERCOM6_PAD0);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief USART initialization function</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enables USART peripheral, clocks and initializes USART driver</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM6_init(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM6_CLOCK_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_init(&SIM6, SERCOM6, SIM6_buffer, SIM6_BUFFER_SIZE, (void *)NULL);</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM6_PORT_init();</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \brief USART Clock initialization function</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Enables register interface and peripheral clock</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> void UART_debug_CLOCK_init()</span><br><span> {</span><br><span> </span><br><span>@@ -312,6 +606,13 @@</span><br><span> </span><br><span> gpio_set_pin_function(USER_LED, GPIO_PIN_FUNCTION_OFF);</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ SIM0_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM1_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM2_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM3_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM4_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM5_init();</span><br><span style="color: hsl(120, 100%, 40%);">+ SIM6_init();</span><br><span> UART_debug_init();</span><br><span> </span><br><span> USB_DEVICE_INSTANCE_init();</span><br><span>diff --git a/sysmoOCTSIM/driver_init.h b/sysmoOCTSIM/driver_init.h</span><br><span>index 25e6370..a0fbb88 100644</span><br><span>--- a/sysmoOCTSIM/driver_init.h</span><br><span>+++ b/sysmoOCTSIM/driver_init.h</span><br><span>@@ -22,11 +22,53 @@</span><br><span> #include <hal_sleep.h></span><br><span> </span><br><span> #include <hal_usart_async.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <hal_usart_async.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <hal_usart_async.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <hal_usart_async.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <hal_usart_async.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <hal_usart_async.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <hal_usart_async.h></span><br><span style="color: hsl(120, 100%, 40%);">+#include <hal_usart_async.h></span><br><span> </span><br><span> #include "hal_usb_device.h"</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+extern struct usart_async_descriptor SIM0;</span><br><span style="color: hsl(120, 100%, 40%);">+extern struct usart_async_descriptor SIM1;</span><br><span style="color: hsl(120, 100%, 40%);">+extern struct usart_async_descriptor SIM2;</span><br><span style="color: hsl(120, 100%, 40%);">+extern struct usart_async_descriptor SIM3;</span><br><span style="color: hsl(120, 100%, 40%);">+extern struct usart_async_descriptor SIM4;</span><br><span style="color: hsl(120, 100%, 40%);">+extern struct usart_async_descriptor SIM5;</span><br><span style="color: hsl(120, 100%, 40%);">+extern struct usart_async_descriptor SIM6;</span><br><span> extern struct usart_async_descriptor UART_debug;</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+void SIM0_PORT_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM0_CLOCK_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM0_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM1_PORT_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM1_CLOCK_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM1_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM2_PORT_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM2_CLOCK_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM2_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM3_PORT_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM3_CLOCK_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM3_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM4_PORT_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM4_CLOCK_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM4_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM5_PORT_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM5_CLOCK_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM5_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM6_PORT_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM6_CLOCK_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM6_init(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void UART_debug_PORT_init(void);</span><br><span> void UART_debug_CLOCK_init(void);</span><br><span> void UART_debug_init(void);</span><br><span>diff --git a/sysmoOCTSIM/examples/driver_examples.c b/sysmoOCTSIM/examples/driver_examples.c</span><br><span>index 8384c87..14f1ae5 100644</span><br><span>--- a/sysmoOCTSIM/examples/driver_examples.c</span><br><span>+++ b/sysmoOCTSIM/examples/driver_examples.c</span><br><span>@@ -11,6 +11,209 @@</span><br><span> #include "utils.h"</span><br><span> </span><br><span> /**</span><br><span style="color: hsl(120, 100%, 40%);">+ * Example of using SIM0 to write "Hello World" using the IO abstraction.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Since the driver is asynchronous we need to use statically allocated memory for string</span><br><span style="color: hsl(120, 100%, 40%);">+ * because driver initiates transfer and then returns before the transmission is completed.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Once transfer has been completed the tx_cb function will be called.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static uint8_t example_SIM0[12] = "Hello World!";</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void tx_cb_SIM0(const struct usart_async_descriptor *const io_descr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Transfer completed */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM0_example(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct io_descriptor *io;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_register_callback(&SIM0, USART_ASYNC_TXC_CB, tx_cb_SIM0);</span><br><span style="color: hsl(120, 100%, 40%);">+ /*usart_async_register_callback(&SIM0, USART_ASYNC_RXC_CB, rx_cb);</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_register_callback(&SIM0, USART_ASYNC_ERROR_CB, err_cb);*/</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_get_io_descriptor(&SIM0, &io);</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_enable(&SIM0);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ io_write(io, example_SIM0, 12);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * Example of using SIM1 to write "Hello World" using the IO abstraction.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Since the driver is asynchronous we need to use statically allocated memory for string</span><br><span style="color: hsl(120, 100%, 40%);">+ * because driver initiates transfer and then returns before the transmission is completed.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Once transfer has been completed the tx_cb function will be called.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static uint8_t example_SIM1[12] = "Hello World!";</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void tx_cb_SIM1(const struct usart_async_descriptor *const io_descr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Transfer completed */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM1_example(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct io_descriptor *io;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_register_callback(&SIM1, USART_ASYNC_TXC_CB, tx_cb_SIM1);</span><br><span style="color: hsl(120, 100%, 40%);">+ /*usart_async_register_callback(&SIM1, USART_ASYNC_RXC_CB, rx_cb);</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_register_callback(&SIM1, USART_ASYNC_ERROR_CB, err_cb);*/</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_get_io_descriptor(&SIM1, &io);</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_enable(&SIM1);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ io_write(io, example_SIM1, 12);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * Example of using SIM2 to write "Hello World" using the IO abstraction.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Since the driver is asynchronous we need to use statically allocated memory for string</span><br><span style="color: hsl(120, 100%, 40%);">+ * because driver initiates transfer and then returns before the transmission is completed.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Once transfer has been completed the tx_cb function will be called.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static uint8_t example_SIM2[12] = "Hello World!";</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void tx_cb_SIM2(const struct usart_async_descriptor *const io_descr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Transfer completed */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM2_example(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct io_descriptor *io;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_register_callback(&SIM2, USART_ASYNC_TXC_CB, tx_cb_SIM2);</span><br><span style="color: hsl(120, 100%, 40%);">+ /*usart_async_register_callback(&SIM2, USART_ASYNC_RXC_CB, rx_cb);</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_register_callback(&SIM2, USART_ASYNC_ERROR_CB, err_cb);*/</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_get_io_descriptor(&SIM2, &io);</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_enable(&SIM2);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ io_write(io, example_SIM2, 12);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * Example of using SIM3 to write "Hello World" using the IO abstraction.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Since the driver is asynchronous we need to use statically allocated memory for string</span><br><span style="color: hsl(120, 100%, 40%);">+ * because driver initiates transfer and then returns before the transmission is completed.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Once transfer has been completed the tx_cb function will be called.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static uint8_t example_SIM3[12] = "Hello World!";</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void tx_cb_SIM3(const struct usart_async_descriptor *const io_descr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Transfer completed */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM3_example(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct io_descriptor *io;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_register_callback(&SIM3, USART_ASYNC_TXC_CB, tx_cb_SIM3);</span><br><span style="color: hsl(120, 100%, 40%);">+ /*usart_async_register_callback(&SIM3, USART_ASYNC_RXC_CB, rx_cb);</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_register_callback(&SIM3, USART_ASYNC_ERROR_CB, err_cb);*/</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_get_io_descriptor(&SIM3, &io);</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_enable(&SIM3);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ io_write(io, example_SIM3, 12);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * Example of using SIM4 to write "Hello World" using the IO abstraction.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Since the driver is asynchronous we need to use statically allocated memory for string</span><br><span style="color: hsl(120, 100%, 40%);">+ * because driver initiates transfer and then returns before the transmission is completed.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Once transfer has been completed the tx_cb function will be called.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static uint8_t example_SIM4[12] = "Hello World!";</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void tx_cb_SIM4(const struct usart_async_descriptor *const io_descr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Transfer completed */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM4_example(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct io_descriptor *io;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_register_callback(&SIM4, USART_ASYNC_TXC_CB, tx_cb_SIM4);</span><br><span style="color: hsl(120, 100%, 40%);">+ /*usart_async_register_callback(&SIM4, USART_ASYNC_RXC_CB, rx_cb);</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_register_callback(&SIM4, USART_ASYNC_ERROR_CB, err_cb);*/</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_get_io_descriptor(&SIM4, &io);</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_enable(&SIM4);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ io_write(io, example_SIM4, 12);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * Example of using SIM5 to write "Hello World" using the IO abstraction.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Since the driver is asynchronous we need to use statically allocated memory for string</span><br><span style="color: hsl(120, 100%, 40%);">+ * because driver initiates transfer and then returns before the transmission is completed.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Once transfer has been completed the tx_cb function will be called.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static uint8_t example_SIM5[12] = "Hello World!";</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void tx_cb_SIM5(const struct usart_async_descriptor *const io_descr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Transfer completed */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM5_example(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct io_descriptor *io;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_register_callback(&SIM5, USART_ASYNC_TXC_CB, tx_cb_SIM5);</span><br><span style="color: hsl(120, 100%, 40%);">+ /*usart_async_register_callback(&SIM5, USART_ASYNC_RXC_CB, rx_cb);</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_register_callback(&SIM5, USART_ASYNC_ERROR_CB, err_cb);*/</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_get_io_descriptor(&SIM5, &io);</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_enable(&SIM5);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ io_write(io, example_SIM5, 12);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * Example of using SIM6 to write "Hello World" using the IO abstraction.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Since the driver is asynchronous we need to use statically allocated memory for string</span><br><span style="color: hsl(120, 100%, 40%);">+ * because driver initiates transfer and then returns before the transmission is completed.</span><br><span style="color: hsl(120, 100%, 40%);">+ *</span><br><span style="color: hsl(120, 100%, 40%);">+ * Once transfer has been completed the tx_cb function will be called.</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static uint8_t example_SIM6[12] = "Hello World!";</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static void tx_cb_SIM6(const struct usart_async_descriptor *const io_descr)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ /* Transfer completed */</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM6_example(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ struct io_descriptor *io;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_register_callback(&SIM6, USART_ASYNC_TXC_CB, tx_cb_SIM6);</span><br><span style="color: hsl(120, 100%, 40%);">+ /*usart_async_register_callback(&SIM6, USART_ASYNC_RXC_CB, rx_cb);</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_register_callback(&SIM6, USART_ASYNC_ERROR_CB, err_cb);*/</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_get_io_descriptor(&SIM6, &io);</span><br><span style="color: hsl(120, 100%, 40%);">+ usart_async_enable(&SIM6);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ io_write(io, example_SIM6, 12);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span> * Example of using UART_debug to write "Hello World" using the IO abstraction.</span><br><span> *</span><br><span> * Since the driver is asynchronous we need to use statically allocated memory for string</span><br><span>diff --git a/sysmoOCTSIM/examples/driver_examples.h b/sysmoOCTSIM/examples/driver_examples.h</span><br><span>index 7bb60eb..4f2ce98 100644</span><br><span>--- a/sysmoOCTSIM/examples/driver_examples.h</span><br><span>+++ b/sysmoOCTSIM/examples/driver_examples.h</span><br><span>@@ -12,6 +12,20 @@</span><br><span> extern "C" {</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+void SIM0_example(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM1_example(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM2_example(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM3_example(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM4_example(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM5_example(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+void SIM6_example(void);</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> void UART_debug_example(void);</span><br><span> </span><br><span> #ifdef __cplusplus</span><br><span>diff --git a/sysmoOCTSIM/hpl/sercom/hpl_sercom.c b/sysmoOCTSIM/hpl/sercom/hpl_sercom.c</span><br><span>index 535ebc6..f235115 100644</span><br><span>--- a/sysmoOCTSIM/hpl/sercom/hpl_sercom.c</span><br><span>+++ b/sysmoOCTSIM/hpl/sercom/hpl_sercom.c</span><br><span>@@ -163,6 +163,20 @@</span><br><span> };</span><br><span> #endif</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static struct _usart_async_device *_sercom0_dev = NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct _usart_async_device *_sercom1_dev = NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct _usart_async_device *_sercom2_dev = NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct _usart_async_device *_sercom3_dev = NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct _usart_async_device *_sercom4_dev = NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct _usart_async_device *_sercom5_dev = NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+static struct _usart_async_device *_sercom6_dev = NULL;</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static struct _usart_async_device *_sercom7_dev = NULL;</span><br><span> </span><br><span> static uint8_t _get_sercom_index(const void *const hw);</span><br><span>@@ -626,6 +640,34 @@</span><br><span> static void _sercom_init_irq_param(const void *const hw, void *dev)</span><br><span> {</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+ if (hw == SERCOM0) {</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom0_dev = (struct _usart_async_device *)dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (hw == SERCOM1) {</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom1_dev = (struct _usart_async_device *)dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (hw == SERCOM2) {</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom2_dev = (struct _usart_async_device *)dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (hw == SERCOM3) {</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom3_dev = (struct _usart_async_device *)dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (hw == SERCOM4) {</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom4_dev = (struct _usart_async_device *)dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (hw == SERCOM5) {</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom5_dev = (struct _usart_async_device *)dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ if (hw == SERCOM6) {</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom6_dev = (struct _usart_async_device *)dev;</span><br><span style="color: hsl(120, 100%, 40%);">+ }</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> if (hw == SERCOM7) {</span><br><span> _sercom7_dev = (struct _usart_async_device *)dev;</span><br><span> }</span><br><span>@@ -2392,6 +2434,209 @@</span><br><span> /**</span><br><span> * \internal Sercom interrupt handler</span><br><span> */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM0_0_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom0_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM0_1_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom0_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM0_2_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom0_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM0_3_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom0_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM1_0_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom1_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM1_1_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom1_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM1_2_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom1_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM1_3_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom1_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM2_0_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom2_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM2_1_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom2_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM2_2_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom2_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM2_3_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom2_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM3_0_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom3_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM3_1_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom3_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM3_2_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom3_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM3_3_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom3_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM4_0_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom4_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM4_1_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom4_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM4_2_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom4_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM4_3_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom4_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM5_0_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom5_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM5_1_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom5_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM5_2_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom5_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM5_3_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom5_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM6_0_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom6_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM6_1_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom6_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM6_2_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom6_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span style="color: hsl(120, 100%, 40%);">+void SERCOM6_3_Handler(void)</span><br><span style="color: hsl(120, 100%, 40%);">+{</span><br><span style="color: hsl(120, 100%, 40%);">+ _sercom_usart_interrupt_handler(_sercom6_dev);</span><br><span style="color: hsl(120, 100%, 40%);">+}</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+/**</span><br><span style="color: hsl(120, 100%, 40%);">+ * \internal Sercom interrupt handler</span><br><span style="color: hsl(120, 100%, 40%);">+ */</span><br><span> void SERCOM7_0_Handler(void)</span><br><span> {</span><br><span> _sercom_usart_interrupt_handler(_sercom7_dev);</span><br><span></span><br></pre><p>To view, visit <a href="https://gerrit.osmocom.org/12811">change 12811</a>. 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<div style="display:none"> Gerrit-Project: osmo-ccid-firmware </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I3f1411ec5bc2ed7dfa714550d041f52be665132a </div>
<div style="display:none"> Gerrit-Change-Number: 12811 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Kévin Redon <kredon@sysmocom.de> </div>
<div style="display:none"> Gerrit-Reviewer: Harald Welte <laforge@gnumonks.org> </div>
<div style="display:none"> Gerrit-Reviewer: Jenkins Builder (1000002) </div>
<div style="display:none"> Gerrit-Reviewer: Kévin Redon <kredon@sysmocom.de> </div>