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Kévin Redon gerrit-no-reply at lists.osmocom.orgKévin Redon has submitted this change and it was merged. ( https://gerrit.osmocom.org/12806 ) Change subject: fix DPLL input clock division ...................................................................... fix DPLL input clock division Change-Id: I3df1356d36b54d0cc34fd827265b1e4b9d55509f --- M sysmoOCTSIM/config/hpl_oscctrl_config.h 1 file changed, 12 insertions(+), 4 deletions(-) Approvals: Jenkins Builder: Verified Harald Welte: Looks good to me, approved diff --git a/sysmoOCTSIM/config/hpl_oscctrl_config.h b/sysmoOCTSIM/config/hpl_oscctrl_config.h index 0676cb5..17bcfc2 100644 --- a/sysmoOCTSIM/config/hpl_oscctrl_config.h +++ b/sysmoOCTSIM/config/hpl_oscctrl_config.h @@ -404,6 +404,7 @@ // <i> Select the clock source. // <id> fdpll0_ref_clock #ifndef CONF_FDPLL0_GCLK +// directly use XOSC1 as clock input (no need to use an additional GCLK) #define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC1 #endif @@ -438,13 +439,15 @@ // <o> Loop Divider Ratio Integer Part <0x0-0x1FFF> // <id> fdpll0_ldr #ifndef CONF_FDPLL0_LDR -#define CONF_FDPLL0_LDR 0x3b +// 2 MHz input clock * ( <59> + 1 = 60 ) = 120 MHz output clock +#define CONF_FDPLL0_LDR 59 #endif // <o> Clock Divider <0x0-0x7FF> // <id> fdpll0_clock_div #ifndef CONF_FDPLL0_DIV -#define CONF_FDPLL0_DIV 0x6 +// XOSC1 = 12 MHz, divide by 2 * ( <2> + 1 ) = 6 to have a 2 MHz clock input (maximum is 3.4 MHz) +#define CONF_FDPLL0_DIV 2 #endif // <q> DCO Filter Enable @@ -485,6 +488,7 @@ // <0x3=>XOSC1 clock reference // <id> fdpll0_arch_refclk #ifndef CONF_FDPLL0_REFCLK +// XOSC1 is used as input signal, thus also use it as reference #define CONF_FDPLL0_REFCLK 0x3 #endif @@ -529,6 +533,7 @@ // <i> Select the clock source. // <id> fdpll1_ref_clock #ifndef CONF_FDPLL1_GCLK +// directly use XOSC1 as clock input (no need to use an additional GCLK) #define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC1 #endif @@ -563,13 +568,15 @@ // <o> Loop Divider Ratio Integer Part <0x0-0x1FFF> // <id> fdpll1_ldr #ifndef CONF_FDPLL1_LDR -#define CONF_FDPLL1_LDR 0x31 +// 2 MHz input clock * ( <49> + 1 = 50 ) = 100 MHz output clock +#define CONF_FDPLL1_LDR 49 #endif // <o> Clock Divider <0x0-0x7FF> // <id> fdpll1_clock_div #ifndef CONF_FDPLL1_DIV -#define CONF_FDPLL1_DIV 0x6 +// XOSC1 = 12 MHz, divide by 2 * ( <2> + 1 ) = 6 to have a 2 MHz clock input (maximum is 3.4 MHz) +#define CONF_FDPLL1_DIV 2 #endif // <q> DCO Filter Enable @@ -610,6 +617,7 @@ // <0x3=>XOSC1 clock reference // <id> fdpll1_arch_refclk #ifndef CONF_FDPLL1_REFCLK +// XOSC1 is used as input signal, thus also use it as reference #define CONF_FDPLL1_REFCLK 0x3 #endif -- To view, visit https://gerrit.osmocom.org/12806 To unsubscribe, or for help writing mail filters, visit https://gerrit.osmocom.org/settings Gerrit-Project: osmo-ccid-firmware Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I3df1356d36b54d0cc34fd827265b1e4b9d55509f Gerrit-Change-Number: 12806 Gerrit-PatchSet: 2 Gerrit-Owner: Kévin Redon <kredon at sysmocom.de> Gerrit-Reviewer: Harald Welte <laforge at gnumonks.org> Gerrit-Reviewer: Jenkins Builder (1000002) Gerrit-Reviewer: Kévin Redon <kredon at sysmocom.de> -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.osmocom.org/pipermail/gerrit-log/attachments/20190207/3afd4c24/attachment.htm>