Change in osmocom-bb[master]: trxcon/scheduler: add CCCH/SDCCH mframe layouts with CBCH

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Vadim Yanitskiy gerrit-no-reply at lists.osmocom.org
Mon Oct 1 19:33:44 UTC 2018 

Vadim Yanitskiy has uploaded this change for review. ( https://gerrit.osmocom.org/11182


Change subject: trxcon/scheduler: add CCCH/SDCCH mframe layouts with CBCH
......................................................................

trxcon/scheduler: add CCCH/SDCCH mframe layouts with CBCH

According to GSM TS 05.02, section 3.3.5, Cell Broadcast Channel
(CBCH) is a downlink only channel, which is used to carry the
short message service cell broadcast (SMSCB). CBCH is optional,
and uses the same physical channel as SDCCH. More precisely,
CBCH replaces sub-slot number 2 of SDCCH channels when enabled.

This change introduces the CBCH related multi-frame layouts,
and CBCH as a separate logical channel type itself. There is
no way to use these layouts for now.

Change-Id: Iad9905fc3a8a012ff1ada26ff95af384816f9873
---
M src/host/trxcon/sched_lchan_desc.c
M src/host/trxcon/sched_mframe.c
M src/host/trxcon/sched_trx.h
3 files changed, 231 insertions(+), 0 deletions(-)



  git pull ssh://gerrit.osmocom.org:29418/osmocom-bb refs/changes/82/11182/1

diff --git a/src/host/trxcon/sched_lchan_desc.c b/src/host/trxcon/sched_lchan_desc.c
index 05443f6..83fdc95 100644
--- a/src/host/trxcon/sched_lchan_desc.c
+++ b/src/host/trxcon/sched_lchan_desc.c
@@ -300,4 +300,10 @@
 		4 * GSM_BURST_PL_LEN,	TRX_CH_FLAG_PDCH,
 		rx_data_fn,		tx_data_fn,
 	},
+	[TRXC_CBCH] = {
+		TRXC_CBCH,		"CBCH",
+		0xc8,			TRX_CH_LID_DEDIC,
+		4 * GSM_BURST_PL_LEN,	TRX_CH_FLAG_AUTO,
+		rx_data_fn,		NULL,
+	},
 };
diff --git a/src/host/trxcon/sched_mframe.c b/src/host/trxcon/sched_mframe.c
index 25e7c29..f99b510 100644
--- a/src/host/trxcon/sched_mframe.c
+++ b/src/host/trxcon/sched_mframe.c
@@ -191,6 +191,113 @@
 	{ TRXC_IDLE,		0,	TRXC_SDCCH4_2,	3 },
 };
 
+static const struct trx_frame frame_bcch_sdcch4_cbch[102] = {
+	/* dl_chan		dl_bid	ul_chan		ul_bid */
+	{ TRXC_FCCH,		0,	TRXC_SDCCH4_3,	0 },
+	{ TRXC_SCH,		0,	TRXC_SDCCH4_3,	1 },
+	{ TRXC_BCCH,		0,	TRXC_SDCCH4_3,	2 },
+	{ TRXC_BCCH,		1,	TRXC_SDCCH4_3,	3 },
+	{ TRXC_BCCH,		2,	TRXC_RACH,	0 },
+	{ TRXC_BCCH,		3,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		0,	TRXC_IDLE,	0 },
+	{ TRXC_CCCH,		1,	TRXC_IDLE,	1 },
+	{ TRXC_CCCH,		2,	TRXC_IDLE,	2 },
+	{ TRXC_CCCH,		3,	TRXC_IDLE,	3 },
+	{ TRXC_FCCH,		0,	TRXC_SACCH4_3,	0 },
+	{ TRXC_SCH,		0,	TRXC_SACCH4_3,	1 },
+	{ TRXC_CCCH,		0,	TRXC_SACCH4_3,	2 },
+	{ TRXC_CCCH,		1,	TRXC_SACCH4_3,	3 },
+	{ TRXC_CCCH,		2,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		3,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		0,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		1,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		2,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		3,	TRXC_RACH,	0 },
+	{ TRXC_FCCH,		0,	TRXC_RACH,	0 },
+	{ TRXC_SCH,		0,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_0,	0,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_0,	1,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_0,	2,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_0,	3,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_1,	0,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_1,	1,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_1,	2,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_1,	3,	TRXC_RACH,	0 },
+	{ TRXC_FCCH,		0,	TRXC_RACH,	0 },
+	{ TRXC_SCH,		0,	TRXC_RACH,	0 },
+	{ TRXC_CBCH,		0,	TRXC_RACH,	0 },
+	{ TRXC_CBCH,		1,	TRXC_RACH,	0 },
+	{ TRXC_CBCH,		2,	TRXC_RACH,	0 },
+	{ TRXC_CBCH,		3,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_3,	0,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_3,	1,	TRXC_SDCCH4_0,	0 },
+	{ TRXC_SDCCH4_3,	2,	TRXC_SDCCH4_0,	1 },
+	{ TRXC_SDCCH4_3,	3,	TRXC_SDCCH4_0,	2 },
+	{ TRXC_FCCH,		0,	TRXC_SDCCH4_0,	3 },
+	{ TRXC_SCH,		0,	TRXC_SDCCH4_1,	0 },
+	{ TRXC_SACCH4_0,	0,	TRXC_SDCCH4_1,	1 },
+	{ TRXC_SACCH4_0,	1,	TRXC_SDCCH4_1,	2 },
+	{ TRXC_SACCH4_0,	2,	TRXC_SDCCH4_1,	3 },
+	{ TRXC_SACCH4_0,	3,	TRXC_RACH,	0 },
+	{ TRXC_SACCH4_1,	0,	TRXC_RACH,	0 },
+	{ TRXC_SACCH4_1,	1,	TRXC_IDLE,	0 },
+	{ TRXC_SACCH4_1,	2,	TRXC_IDLE,	1 },
+	{ TRXC_SACCH4_1,	3,	TRXC_IDLE,	2 },
+	{ TRXC_IDLE,		0,	TRXC_IDLE,	3 },
+
+	{ TRXC_FCCH,		0,	TRXC_SDCCH4_3,	0 },
+	{ TRXC_SCH,		0,	TRXC_SDCCH4_3,	1 },
+	{ TRXC_BCCH,		0,	TRXC_SDCCH4_3,	2 },
+	{ TRXC_BCCH,		1,	TRXC_SDCCH4_3,	3 },
+	{ TRXC_BCCH,		2,	TRXC_RACH,	0 },
+	{ TRXC_BCCH,		3,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		0,	TRXC_SACCH4_0,	0 },
+	{ TRXC_CCCH,		1,	TRXC_SACCH4_0,	1 },
+	{ TRXC_CCCH,		2,	TRXC_SACCH4_0,	2 },
+	{ TRXC_CCCH,		3,	TRXC_SACCH4_0,	3 },
+	{ TRXC_FCCH,		0,	TRXC_SACCH4_1,	0 },
+	{ TRXC_SCH,		0,	TRXC_SACCH4_1,	1 },
+	{ TRXC_CCCH,		0,	TRXC_SACCH4_1,	2 },
+	{ TRXC_CCCH,		1,	TRXC_SACCH4_1,	3 },
+	{ TRXC_CCCH,		2,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		3,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		0,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		1,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		2,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		3,	TRXC_RACH,	0 },
+	{ TRXC_FCCH,		0,	TRXC_RACH,	0 },
+	{ TRXC_SCH,		0,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_0,	0,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_0,	1,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_0,	2,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_0,	3,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_1,	0,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_1,	1,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_1,	2,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_1,	3,	TRXC_RACH,	0 },
+	{ TRXC_FCCH,		0,	TRXC_RACH,	0 },
+	{ TRXC_SCH,		0,	TRXC_RACH,	0 },
+	{ TRXC_CBCH,		0,	TRXC_RACH,	0 },
+	{ TRXC_CBCH,		1,	TRXC_RACH,	0 },
+	{ TRXC_CBCH,		2,	TRXC_RACH,	0 },
+	{ TRXC_CBCH,		3,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_3,	0,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_3,	1,	TRXC_SDCCH4_0,	0 },
+	{ TRXC_SDCCH4_3,	2,	TRXC_SDCCH4_0,	1 },
+	{ TRXC_SDCCH4_3,	3,	TRXC_SDCCH4_0,	2 },
+	{ TRXC_FCCH,		0,	TRXC_SDCCH4_0,	3 },
+	{ TRXC_SCH,		0,	TRXC_SDCCH4_1,	0 },
+	{ TRXC_IDLE,		0,	TRXC_SDCCH4_1,	1 },
+	{ TRXC_IDLE,		1,	TRXC_SDCCH4_1,	2 },
+	{ TRXC_IDLE,		2,	TRXC_SDCCH4_1,	3 },
+	{ TRXC_IDLE,		3,	TRXC_RACH,	0 },
+	{ TRXC_SACCH4_3,	0,	TRXC_RACH,	0 },
+	{ TRXC_SACCH4_3,	1,	TRXC_SDCCH4_2,	0 },
+	{ TRXC_SACCH4_3,	2,	TRXC_SDCCH4_2,	1 },
+	{ TRXC_SACCH4_3,	3,	TRXC_SDCCH4_2,	2 },
+	{ TRXC_IDLE,		0,	TRXC_SDCCH4_2,	3 },
+};
+
 static const struct trx_frame frame_sdcch8[102] = {
 	/* dl_chan		dl_bid	ul_chan		ul_bid */
 	{ TRXC_SDCCH8_0,	0,	TRXC_SACCH8_5,	0 },
@@ -298,6 +405,113 @@
 	{ TRXC_IDLE,		0,	TRXC_SACCH8_4,	3 },
 };
 
+static const struct trx_frame frame_sdcch8_cbch[102] = {
+	/* dl_chan		dl_bid	ul_chan		ul_bid */
+	{ TRXC_SDCCH8_0,	0,	TRXC_SACCH8_5,	0 },
+	{ TRXC_SDCCH8_0,	1,	TRXC_SACCH8_5,	1 },
+	{ TRXC_SDCCH8_0,	2,	TRXC_SACCH8_5,	2 },
+	{ TRXC_SDCCH8_0,	3,	TRXC_SACCH8_5,	3 },
+	{ TRXC_SDCCH8_1,	0,	TRXC_SACCH8_6,	0 },
+	{ TRXC_SDCCH8_1,	1,	TRXC_SACCH8_6,	1 },
+	{ TRXC_SDCCH8_1,	2,	TRXC_SACCH8_6,	2 },
+	{ TRXC_SDCCH8_1,	3,	TRXC_SACCH8_6,	3 },
+	{ TRXC_CBCH,		0,	TRXC_SACCH8_7,	0 },
+	{ TRXC_CBCH,		1,	TRXC_SACCH8_7,	1 },
+	{ TRXC_CBCH,		2,	TRXC_SACCH8_7,	2 },
+	{ TRXC_CBCH,		3,	TRXC_SACCH8_7,	3 },
+	{ TRXC_SDCCH8_3,	0,	TRXC_IDLE,	0 },
+	{ TRXC_SDCCH8_3,	1,	TRXC_IDLE,	0 },
+	{ TRXC_SDCCH8_3,	2,	TRXC_IDLE,	0 },
+	{ TRXC_SDCCH8_3,	3,	TRXC_SDCCH8_0,	0 },
+	{ TRXC_SDCCH8_4,	0,	TRXC_SDCCH8_0,	1 },
+	{ TRXC_SDCCH8_4,	1,	TRXC_SDCCH8_0,	2 },
+	{ TRXC_SDCCH8_4,	2,	TRXC_SDCCH8_0,	3 },
+	{ TRXC_SDCCH8_4,	3,	TRXC_SDCCH8_1,	0 },
+	{ TRXC_SDCCH8_5,	0,	TRXC_SDCCH8_1,	1 },
+	{ TRXC_SDCCH8_5,	1,	TRXC_SDCCH8_1,	2 },
+	{ TRXC_SDCCH8_5,	2,	TRXC_SDCCH8_1,	3 },
+	{ TRXC_SDCCH8_5,	3,	TRXC_IDLE,	0 },
+	{ TRXC_SDCCH8_6,	0,	TRXC_IDLE,	1 },
+	{ TRXC_SDCCH8_6,	1,	TRXC_IDLE,	2 },
+	{ TRXC_SDCCH8_6,	2,	TRXC_IDLE,	3 },
+	{ TRXC_SDCCH8_6,	3,	TRXC_SDCCH8_3,	0 },
+	{ TRXC_SDCCH8_7,	0,	TRXC_SDCCH8_3,	1 },
+	{ TRXC_SDCCH8_7,	1,	TRXC_SDCCH8_3,	2 },
+	{ TRXC_SDCCH8_7,	2,	TRXC_SDCCH8_3,	3 },
+	{ TRXC_SDCCH8_7,	3,	TRXC_SDCCH8_4,	0 },
+	{ TRXC_SACCH8_0,	0,	TRXC_SDCCH8_4,	1 },
+	{ TRXC_SACCH8_0,	1,	TRXC_SDCCH8_4,	2 },
+	{ TRXC_SACCH8_0,	2,	TRXC_SDCCH8_4,	3 },
+	{ TRXC_SACCH8_0,	3,	TRXC_SDCCH8_5,	0 },
+	{ TRXC_SACCH8_1,	0,	TRXC_SDCCH8_5,	1 },
+	{ TRXC_SACCH8_1,	1,	TRXC_SDCCH8_5,	2 },
+	{ TRXC_SACCH8_1,	2,	TRXC_SDCCH8_5,	3 },
+	{ TRXC_SACCH8_1,	3,	TRXC_SDCCH8_6,	0 },
+	{ TRXC_IDLE,		0,	TRXC_SDCCH8_6,	1 },
+	{ TRXC_IDLE,		1,	TRXC_SDCCH8_6,	2 },
+	{ TRXC_IDLE,		2,	TRXC_SDCCH8_6,	3 },
+	{ TRXC_IDLE,		3,	TRXC_SDCCH8_7,	0 },
+	{ TRXC_SACCH8_3,	0,	TRXC_SDCCH8_7,	1 },
+	{ TRXC_SACCH8_3,	1,	TRXC_SDCCH8_7,	2 },
+	{ TRXC_SACCH8_3,	2,	TRXC_SDCCH8_7,	3 },
+	{ TRXC_SACCH8_3,	3,	TRXC_SACCH8_0,	0 },
+	{ TRXC_IDLE,		0,	TRXC_SACCH8_0,	1 },
+	{ TRXC_IDLE,		0,	TRXC_SACCH8_0,	2 },
+	{ TRXC_IDLE,		0,	TRXC_SACCH8_0,	3 },
+
+	{ TRXC_SDCCH8_0,	0,	TRXC_SACCH8_1,	0 },
+	{ TRXC_SDCCH8_0,	1,	TRXC_SACCH8_1,	1 },
+	{ TRXC_SDCCH8_0,	2,	TRXC_SACCH8_1,	2 },
+	{ TRXC_SDCCH8_0,	3,	TRXC_SACCH8_1,	3 },
+	{ TRXC_SDCCH8_1,	0,	TRXC_IDLE,	0 },
+	{ TRXC_SDCCH8_1,	1,	TRXC_IDLE,	1 },
+	{ TRXC_SDCCH8_1,	2,	TRXC_IDLE,	2 },
+	{ TRXC_SDCCH8_1,	3,	TRXC_IDLE,	3 },
+	{ TRXC_CBCH,		0,	TRXC_SACCH8_3,	0 },
+	{ TRXC_CBCH,		1,	TRXC_SACCH8_3,	1 },
+	{ TRXC_CBCH,		2,	TRXC_SACCH8_3,	2 },
+	{ TRXC_CBCH,		3,	TRXC_SACCH8_3,	3 },
+	{ TRXC_SDCCH8_3,	0,	TRXC_IDLE,	0 },
+	{ TRXC_SDCCH8_3,	1,	TRXC_IDLE,	0 },
+	{ TRXC_SDCCH8_3,	2,	TRXC_IDLE,	0 },
+	{ TRXC_SDCCH8_3,	3,	TRXC_SDCCH8_0,	0 },
+	{ TRXC_SDCCH8_4,	0,	TRXC_SDCCH8_0,	1 },
+	{ TRXC_SDCCH8_4,	1,	TRXC_SDCCH8_0,	2 },
+	{ TRXC_SDCCH8_4,	2,	TRXC_SDCCH8_0,	3 },
+	{ TRXC_SDCCH8_4,	3,	TRXC_SDCCH8_1,	0 },
+	{ TRXC_SDCCH8_5,	0,	TRXC_SDCCH8_1,	1 },
+	{ TRXC_SDCCH8_5,	1,	TRXC_SDCCH8_1,	2 },
+	{ TRXC_SDCCH8_5,	2,	TRXC_SDCCH8_1,	3 },
+	{ TRXC_SDCCH8_5,	3,	TRXC_IDLE,	0 },
+	{ TRXC_SDCCH8_6,	0,	TRXC_IDLE,	1 },
+	{ TRXC_SDCCH8_6,	1,	TRXC_IDLE,	2 },
+	{ TRXC_SDCCH8_6,	2,	TRXC_IDLE,	3 },
+	{ TRXC_SDCCH8_6,	3,	TRXC_SDCCH8_3,	0 },
+	{ TRXC_SDCCH8_7,	0,	TRXC_SDCCH8_3,	1 },
+	{ TRXC_SDCCH8_7,	1,	TRXC_SDCCH8_3,	2 },
+	{ TRXC_SDCCH8_7,	2,	TRXC_SDCCH8_3,	3 },
+	{ TRXC_SDCCH8_7,	3,	TRXC_SDCCH8_4,	0 },
+	{ TRXC_SACCH8_4,	0,	TRXC_SDCCH8_4,	1 },
+	{ TRXC_SACCH8_4,	1,	TRXC_SDCCH8_4,	2 },
+	{ TRXC_SACCH8_4,	2,	TRXC_SDCCH8_4,	3 },
+	{ TRXC_SACCH8_4,	3,	TRXC_SDCCH8_5,	0 },
+	{ TRXC_SACCH8_5,	0,	TRXC_SDCCH8_5,	1 },
+	{ TRXC_SACCH8_5,	1,	TRXC_SDCCH8_5,	2 },
+	{ TRXC_SACCH8_5,	2,	TRXC_SDCCH8_5,	3 },
+	{ TRXC_SACCH8_5,	3,	TRXC_SDCCH8_6,	0 },
+	{ TRXC_SACCH8_6,	0,	TRXC_SDCCH8_6,	1 },
+	{ TRXC_SACCH8_6,	1,	TRXC_SDCCH8_6,	2 },
+	{ TRXC_SACCH8_6,	2,	TRXC_SDCCH8_6,	3 },
+	{ TRXC_SACCH8_6,	3,	TRXC_SDCCH8_7,	0 },
+	{ TRXC_SACCH8_7,	0,	TRXC_SDCCH8_7,	1 },
+	{ TRXC_SACCH8_7,	1,	TRXC_SDCCH8_7,	2 },
+	{ TRXC_SACCH8_7,	2,	TRXC_SDCCH8_7,	3 },
+	{ TRXC_SACCH8_7,	3,	TRXC_SACCH8_4,	0 },
+	{ TRXC_IDLE,		0,	TRXC_SACCH8_4,	1 },
+	{ TRXC_IDLE,		0,	TRXC_SACCH8_4,	2 },
+	{ TRXC_IDLE,		0,	TRXC_SACCH8_4,	3 },
+};
+
 static const struct trx_frame frame_tchf_ts0[104] = {
 	/* dl_chan	dl_bid	ul_chan		ul_bid */
 	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
@@ -1728,11 +1942,21 @@
 		frame_bcch_sdcch4
 	},
 	{
+		GSM_PCHAN_CCCH_SDCCH4_CBCH, "BCCH+CCCH+SDCCH/4+SACCH/4+CBCH",
+		102,	0xff,	(uint64_t) 0x400f001e3e,
+		frame_bcch_sdcch4_cbch
+	},
+	{
 		GSM_PCHAN_SDCCH8_SACCH8C, "SDCCH/8+SACCH/8",
 		102,	0xff,	(uint64_t) 0xff01fe000,
 		frame_sdcch8
 	},
 	{
+		GSM_PCHAN_SDCCH8_SACCH8C_CBCH, "SDCCH/8+SACCH/8+CBCH",
+		102,	0xff,	(uint64_t) 0x4ff01fe000,
+		frame_sdcch8_cbch
+	},
+	{
 		GSM_PCHAN_TCH_F, "TCH/F+SACCH",
 		104,	0x01,	(uint64_t) 0x200040,
 		frame_tchf_ts0
diff --git a/src/host/trxcon/sched_trx.h b/src/host/trxcon/sched_trx.h
index 10ae256..81d9ee6 100644
--- a/src/host/trxcon/sched_trx.h
+++ b/src/host/trxcon/sched_trx.h
@@ -83,6 +83,7 @@
 	TRXC_SACCH8_7,
 	TRXC_PDTCH,
 	TRXC_PTCCH,
+	TRXC_CBCH,
 	_TRX_CHAN_MAX
 };
 

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Gerrit-Branch: master
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Gerrit-Change-Id: Iad9905fc3a8a012ff1ada26ff95af384816f9873
Gerrit-Change-Number: 11182
Gerrit-PatchSet: 1
Gerrit-Owner: Vadim Yanitskiy <axilirator at gmail.com>
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