<p>Vadim Yanitskiy has uploaded this change for <strong>review</strong>.</p><p><a href="https://gerrit.osmocom.org/11182">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">trxcon/scheduler: add CCCH/SDCCH mframe layouts with CBCH<br><br>According to GSM TS 05.02, section 3.3.5, Cell Broadcast Channel<br>(CBCH) is a downlink only channel, which is used to carry the<br>short message service cell broadcast (SMSCB). CBCH is optional,<br>and uses the same physical channel as SDCCH. More precisely,<br>CBCH replaces sub-slot number 2 of SDCCH channels when enabled.<br><br>This change introduces the CBCH related multi-frame layouts,<br>and CBCH as a separate logical channel type itself. There is<br>no way to use these layouts for now.<br><br>Change-Id: Iad9905fc3a8a012ff1ada26ff95af384816f9873<br>---<br>M src/host/trxcon/sched_lchan_desc.c<br>M src/host/trxcon/sched_mframe.c<br>M src/host/trxcon/sched_trx.h<br>3 files changed, 231 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://gerrit.osmocom.org:29418/osmocom-bb refs/changes/82/11182/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/src/host/trxcon/sched_lchan_desc.c b/src/host/trxcon/sched_lchan_desc.c</span><br><span>index 05443f6..83fdc95 100644</span><br><span>--- a/src/host/trxcon/sched_lchan_desc.c</span><br><span>+++ b/src/host/trxcon/sched_lchan_desc.c</span><br><span>@@ -300,4 +300,10 @@</span><br><span> 4 * GSM_BURST_PL_LEN, TRX_CH_FLAG_PDCH,</span><br><span> rx_data_fn, tx_data_fn,</span><br><span> },</span><br><span style="color: hsl(120, 100%, 40%);">+ [TRXC_CBCH] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ TRXC_CBCH, "CBCH",</span><br><span style="color: hsl(120, 100%, 40%);">+ 0xc8, TRX_CH_LID_DEDIC,</span><br><span style="color: hsl(120, 100%, 40%);">+ 4 * GSM_BURST_PL_LEN, TRX_CH_FLAG_AUTO,</span><br><span style="color: hsl(120, 100%, 40%);">+ rx_data_fn, NULL,</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span> };</span><br><span>diff --git a/src/host/trxcon/sched_mframe.c b/src/host/trxcon/sched_mframe.c</span><br><span>index 25e7c29..f99b510 100644</span><br><span>--- a/src/host/trxcon/sched_mframe.c</span><br><span>+++ b/src/host/trxcon/sched_mframe.c</span><br><span>@@ -191,6 +191,113 @@</span><br><span> { TRXC_IDLE, 0, TRXC_SDCCH4_2, 3 },</span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static const struct trx_frame frame_bcch_sdcch4_cbch[102] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* dl_chan dl_bid ul_chan ul_bid */</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_FCCH, 0, TRXC_SDCCH4_3, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SCH, 0, TRXC_SDCCH4_3, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_BCCH, 0, TRXC_SDCCH4_3, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_BCCH, 1, TRXC_SDCCH4_3, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_BCCH, 2, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_BCCH, 3, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 0, TRXC_IDLE, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 1, TRXC_IDLE, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 2, TRXC_IDLE, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 3, TRXC_IDLE, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_FCCH, 0, TRXC_SACCH4_3, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SCH, 0, TRXC_SACCH4_3, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 0, TRXC_SACCH4_3, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 1, TRXC_SACCH4_3, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 2, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 3, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 0, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 1, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 2, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 3, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_FCCH, 0, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SCH, 0, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_0, 0, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_0, 1, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_0, 2, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_0, 3, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_1, 0, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_1, 1, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_1, 2, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_1, 3, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_FCCH, 0, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SCH, 0, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CBCH, 0, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CBCH, 1, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CBCH, 2, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CBCH, 3, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_3, 0, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_3, 1, TRXC_SDCCH4_0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_3, 2, TRXC_SDCCH4_0, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_3, 3, TRXC_SDCCH4_0, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_FCCH, 0, TRXC_SDCCH4_0, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SCH, 0, TRXC_SDCCH4_1, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH4_0, 0, TRXC_SDCCH4_1, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH4_0, 1, TRXC_SDCCH4_1, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH4_0, 2, TRXC_SDCCH4_1, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH4_0, 3, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH4_1, 0, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH4_1, 1, TRXC_IDLE, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH4_1, 2, TRXC_IDLE, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH4_1, 3, TRXC_IDLE, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_IDLE, 0, TRXC_IDLE, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_FCCH, 0, TRXC_SDCCH4_3, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SCH, 0, TRXC_SDCCH4_3, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_BCCH, 0, TRXC_SDCCH4_3, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_BCCH, 1, TRXC_SDCCH4_3, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_BCCH, 2, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_BCCH, 3, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 0, TRXC_SACCH4_0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 1, TRXC_SACCH4_0, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 2, TRXC_SACCH4_0, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 3, TRXC_SACCH4_0, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_FCCH, 0, TRXC_SACCH4_1, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SCH, 0, TRXC_SACCH4_1, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 0, TRXC_SACCH4_1, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 1, TRXC_SACCH4_1, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 2, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 3, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 0, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 1, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 2, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CCCH, 3, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_FCCH, 0, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SCH, 0, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_0, 0, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_0, 1, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_0, 2, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_0, 3, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_1, 0, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_1, 1, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_1, 2, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_1, 3, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_FCCH, 0, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SCH, 0, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CBCH, 0, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CBCH, 1, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CBCH, 2, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CBCH, 3, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_3, 0, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_3, 1, TRXC_SDCCH4_0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_3, 2, TRXC_SDCCH4_0, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH4_3, 3, TRXC_SDCCH4_0, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_FCCH, 0, TRXC_SDCCH4_0, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SCH, 0, TRXC_SDCCH4_1, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_IDLE, 0, TRXC_SDCCH4_1, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_IDLE, 1, TRXC_SDCCH4_1, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_IDLE, 2, TRXC_SDCCH4_1, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_IDLE, 3, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH4_3, 0, TRXC_RACH, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH4_3, 1, TRXC_SDCCH4_2, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH4_3, 2, TRXC_SDCCH4_2, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH4_3, 3, TRXC_SDCCH4_2, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_IDLE, 0, TRXC_SDCCH4_2, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static const struct trx_frame frame_sdcch8[102] = {</span><br><span> /* dl_chan dl_bid ul_chan ul_bid */</span><br><span> { TRXC_SDCCH8_0, 0, TRXC_SACCH8_5, 0 },</span><br><span>@@ -298,6 +405,113 @@</span><br><span> { TRXC_IDLE, 0, TRXC_SACCH8_4, 3 },</span><br><span> };</span><br><span> </span><br><span style="color: hsl(120, 100%, 40%);">+static const struct trx_frame frame_sdcch8_cbch[102] = {</span><br><span style="color: hsl(120, 100%, 40%);">+ /* dl_chan dl_bid ul_chan ul_bid */</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_0, 0, TRXC_SACCH8_5, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_0, 1, TRXC_SACCH8_5, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_0, 2, TRXC_SACCH8_5, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_0, 3, TRXC_SACCH8_5, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_1, 0, TRXC_SACCH8_6, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_1, 1, TRXC_SACCH8_6, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_1, 2, TRXC_SACCH8_6, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_1, 3, TRXC_SACCH8_6, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CBCH, 0, TRXC_SACCH8_7, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CBCH, 1, TRXC_SACCH8_7, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CBCH, 2, TRXC_SACCH8_7, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CBCH, 3, TRXC_SACCH8_7, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_3, 0, TRXC_IDLE, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_3, 1, TRXC_IDLE, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_3, 2, TRXC_IDLE, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_3, 3, TRXC_SDCCH8_0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_4, 0, TRXC_SDCCH8_0, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_4, 1, TRXC_SDCCH8_0, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_4, 2, TRXC_SDCCH8_0, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_4, 3, TRXC_SDCCH8_1, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_5, 0, TRXC_SDCCH8_1, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_5, 1, TRXC_SDCCH8_1, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_5, 2, TRXC_SDCCH8_1, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_5, 3, TRXC_IDLE, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_6, 0, TRXC_IDLE, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_6, 1, TRXC_IDLE, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_6, 2, TRXC_IDLE, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_6, 3, TRXC_SDCCH8_3, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_7, 0, TRXC_SDCCH8_3, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_7, 1, TRXC_SDCCH8_3, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_7, 2, TRXC_SDCCH8_3, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_7, 3, TRXC_SDCCH8_4, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_0, 0, TRXC_SDCCH8_4, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_0, 1, TRXC_SDCCH8_4, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_0, 2, TRXC_SDCCH8_4, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_0, 3, TRXC_SDCCH8_5, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_1, 0, TRXC_SDCCH8_5, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_1, 1, TRXC_SDCCH8_5, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_1, 2, TRXC_SDCCH8_5, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_1, 3, TRXC_SDCCH8_6, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_IDLE, 0, TRXC_SDCCH8_6, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_IDLE, 1, TRXC_SDCCH8_6, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_IDLE, 2, TRXC_SDCCH8_6, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_IDLE, 3, TRXC_SDCCH8_7, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_3, 0, TRXC_SDCCH8_7, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_3, 1, TRXC_SDCCH8_7, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_3, 2, TRXC_SDCCH8_7, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_3, 3, TRXC_SACCH8_0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_IDLE, 0, TRXC_SACCH8_0, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_IDLE, 0, TRXC_SACCH8_0, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_IDLE, 0, TRXC_SACCH8_0, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_0, 0, TRXC_SACCH8_1, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_0, 1, TRXC_SACCH8_1, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_0, 2, TRXC_SACCH8_1, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_0, 3, TRXC_SACCH8_1, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_1, 0, TRXC_IDLE, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_1, 1, TRXC_IDLE, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_1, 2, TRXC_IDLE, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_1, 3, TRXC_IDLE, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CBCH, 0, TRXC_SACCH8_3, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CBCH, 1, TRXC_SACCH8_3, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CBCH, 2, TRXC_SACCH8_3, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_CBCH, 3, TRXC_SACCH8_3, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_3, 0, TRXC_IDLE, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_3, 1, TRXC_IDLE, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_3, 2, TRXC_IDLE, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_3, 3, TRXC_SDCCH8_0, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_4, 0, TRXC_SDCCH8_0, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_4, 1, TRXC_SDCCH8_0, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_4, 2, TRXC_SDCCH8_0, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_4, 3, TRXC_SDCCH8_1, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_5, 0, TRXC_SDCCH8_1, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_5, 1, TRXC_SDCCH8_1, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_5, 2, TRXC_SDCCH8_1, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_5, 3, TRXC_IDLE, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_6, 0, TRXC_IDLE, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_6, 1, TRXC_IDLE, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_6, 2, TRXC_IDLE, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_6, 3, TRXC_SDCCH8_3, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_7, 0, TRXC_SDCCH8_3, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_7, 1, TRXC_SDCCH8_3, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_7, 2, TRXC_SDCCH8_3, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SDCCH8_7, 3, TRXC_SDCCH8_4, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_4, 0, TRXC_SDCCH8_4, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_4, 1, TRXC_SDCCH8_4, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_4, 2, TRXC_SDCCH8_4, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_4, 3, TRXC_SDCCH8_5, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_5, 0, TRXC_SDCCH8_5, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_5, 1, TRXC_SDCCH8_5, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_5, 2, TRXC_SDCCH8_5, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_5, 3, TRXC_SDCCH8_6, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_6, 0, TRXC_SDCCH8_6, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_6, 1, TRXC_SDCCH8_6, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_6, 2, TRXC_SDCCH8_6, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_6, 3, TRXC_SDCCH8_7, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_7, 0, TRXC_SDCCH8_7, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_7, 1, TRXC_SDCCH8_7, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_7, 2, TRXC_SDCCH8_7, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_SACCH8_7, 3, TRXC_SACCH8_4, 0 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_IDLE, 0, TRXC_SACCH8_4, 1 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_IDLE, 0, TRXC_SACCH8_4, 2 },</span><br><span style="color: hsl(120, 100%, 40%);">+ { TRXC_IDLE, 0, TRXC_SACCH8_4, 3 },</span><br><span style="color: hsl(120, 100%, 40%);">+};</span><br><span style="color: hsl(120, 100%, 40%);">+</span><br><span> static const struct trx_frame frame_tchf_ts0[104] = {</span><br><span> /* dl_chan dl_bid ul_chan ul_bid */</span><br><span> { TRXC_TCHF, 0, TRXC_TCHF, 0 },</span><br><span>@@ -1728,11 +1942,21 @@</span><br><span> frame_bcch_sdcch4</span><br><span> },</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ GSM_PCHAN_CCCH_SDCCH4_CBCH, "BCCH+CCCH+SDCCH/4+SACCH/4+CBCH",</span><br><span style="color: hsl(120, 100%, 40%);">+ 102, 0xff, (uint64_t) 0x400f001e3e,</span><br><span style="color: hsl(120, 100%, 40%);">+ frame_bcch_sdcch4_cbch</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span> GSM_PCHAN_SDCCH8_SACCH8C, "SDCCH/8+SACCH/8",</span><br><span> 102, 0xff, (uint64_t) 0xff01fe000,</span><br><span> frame_sdcch8</span><br><span> },</span><br><span> {</span><br><span style="color: hsl(120, 100%, 40%);">+ GSM_PCHAN_SDCCH8_SACCH8C_CBCH, "SDCCH/8+SACCH/8+CBCH",</span><br><span style="color: hsl(120, 100%, 40%);">+ 102, 0xff, (uint64_t) 0x4ff01fe000,</span><br><span style="color: hsl(120, 100%, 40%);">+ frame_sdcch8_cbch</span><br><span style="color: hsl(120, 100%, 40%);">+ },</span><br><span style="color: hsl(120, 100%, 40%);">+ {</span><br><span> GSM_PCHAN_TCH_F, "TCH/F+SACCH",</span><br><span> 104, 0x01, (uint64_t) 0x200040,</span><br><span> frame_tchf_ts0</span><br><span>diff --git a/src/host/trxcon/sched_trx.h b/src/host/trxcon/sched_trx.h</span><br><span>index 10ae256..81d9ee6 100644</span><br><span>--- a/src/host/trxcon/sched_trx.h</span><br><span>+++ b/src/host/trxcon/sched_trx.h</span><br><span>@@ -83,6 +83,7 @@</span><br><span> TRXC_SACCH8_7,</span><br><span> TRXC_PDTCH,</span><br><span> TRXC_PTCCH,</span><br><span style="color: hsl(120, 100%, 40%);">+ TRXC_CBCH,</span><br><span> _TRX_CHAN_MAX</span><br><span> };</span><br><span> </span><br><span></span><br></pre><p>To view, visit <a href="https://gerrit.osmocom.org/11182">change 11182</a>. To unsubscribe, or for help writing mail filters, visit <a href="https://gerrit.osmocom.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://gerrit.osmocom.org/11182"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: osmocom-bb </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Iad9905fc3a8a012ff1ada26ff95af384816f9873 </div>
<div style="display:none"> Gerrit-Change-Number: 11182 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Vadim Yanitskiy <axilirator@gmail.com> </div>