umtrx fpga internal clocking

Josh Blum josh at joshknows.com
Tue Apr 8 23:25:02 UTC 2014


>>
> No. If you look at dsp_core_rx.v. You'll see that strobe signal is forming
> at 104MHz (dsp_clk), not at adc_clk (13MHz).
> I added some additional code in purpose of moving strobe signal from 13MHz
> clock domain into 104MHz clock domain.
> If needed, I can point you to the appropriate commit in our git repository.
> 
> 

I see. I just got lost in the ifdefs. Those are the changes I was
looking for.

> 
> Yes, but global clock for LMS chip must be twice higher then samples rate.
> Therefore UmTRX have common 26MHz global clock source for FPGA and LMS
> chips instead of 13MHz.
> 

I see, the input clock is 26 MHz, ok makes sense.

Thanks!

So let me propose one more idea for thought. To avoid clock domain
crossing completely: We can use the existing usrp2 style design at 26
MHz. The rx/tx DSP, and vita framer/deframer all run at 26 MHz. The only
change needed is to pace the DSPs. For example, the rx input is only
good every other 26 MHz cycle, so add an input strobe to the RX DSP.
Similarly the TX DSP would have its input paced to take data every other
cycle. That way the 32-bit vita framers will have 2x clock cycles to do
the framing/deframing even when the DSP is running at full rate.

104MHz fifo bus in -> cross clock fifo to 26 MHz -> vita tx deframer ->
paced tx dsp -> out to dac

in from adc -> paced rx dsp -> vita rx deframer -> cross clock fifo to
104 MHz -> 104 MHz fifo bus out

Just a thought,
-josh




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