umtrx fpga internal clocking

Andrew Karpenkov plddesigner at gmail.com
Tue Apr 8 19:59:20 UTC 2014


Hi, Josh.

Please, see my comments below.

1) vita chain/dsp core
> Inside the u2plus_core.v, there is a 13MHz clock (lms_clk) that is used
> to clock the time core and the dsps. The vita chain is clocked at 104MHz
> (dsp_clk). So for example, when the dsp strobes out 1 sample, does the
> vita_rx_chain see 8 of the same sample?
>
No. If you look at dsp_core_rx.v. You'll see that strobe signal is forming
at 104MHz (dsp_clk), not at adc_clk (13MHz).
I added some additional code in purpose of moving strobe signal from 13MHz
clock domain into 104MHz clock domain.
If needed, I can point you to the appropriate commit in our git repository.


2) usrp3 style vita framing/deframing

Some time after umtrx was released, B200 came out. The FPGA architecture
> in B200 was changed from the earlier models to address dealing with
> these integrated frontend chips. Specifically, the ADC, DAC, DSP, and
> framing can all run on the same clock domain at full sample rate. This
> is accomplished because the vita framing happens on 64-bit wide bus to
> deal with the overhead of VITA headers. I suspect this architecture
> would be better fitting for the UmTRX.

I mostly agree with you, but I need some time to look at B200 fpga code
more deeply.

3) u2plus_umtrx_v2.v
> It looks like the ADC and DAC IQ signals are clocked in/out on the
> positive and negative edges of the 13MHz clock. This is accomplished
> using a 26 MHz clock. So technically, this is another clock domain
> crossing between the 13/26MHz for the ADC/DAC signals. So, you should be
> able to accomplish the same effect in with just the 13MHz clock using
> the ODDR2 and IDDR2 xilinx modules.

Yes, but global clock for LMS chip must be twice higher then samples rate.
Therefore UmTRX have common 26MHz global clock source for FPGA and LMS
chips instead of 13MHz.

4) digital loopback options?
> I was looking for a way to do a digital loopback inside the LMS. I wasnt
> sure if it was possible. Basically, if I set some value on the DAC pins,
> can I get the same value of the ADC pins? I saw registers for baseband
> loopback, but I think thats all analog. The idea is to self-test the bus
> timing by putting a test word into the IOs.

In this question I agree with Alexander.  There is no digital loopback in
the LMS, only analog loopback.

Regards,
Andrew Karpenkov

С уважением,
Андрей Карпенков


2014-04-08 22:45 GMT+03:00 Alexander Chemeris <
Alexander.Chemeris at fairwaves.co>:

> Hi Josh,
>
> On Tue, Apr 8, 2014 at 11:00 PM, Josh Blum <josh at joshknows.com> wrote:
> > Hey guys,
> >
> > Please CC whoever appropriate.
> >
> > I have been looking over the u2plus_core.v and u2plus_umtrx_v2.v files
> > with the intention of updating the vita rx/tx chains and dsp chains. I
> > noticed a few interesting things about the clocking and I just wanted to
> > confirm some of my assumptions, a few possible changes, and possibly
> > share some knowledge.
> >
> > 1) vita chain/dsp core
> > Inside the u2plus_core.v, there is a 13MHz clock (lms_clk) that is used
> > to clock the time core and the dsps. The vita chain is clocked at 104MHz
> > (dsp_clk). So for example, when the dsp strobes out 1 sample, does the
> > vita_rx_chain see 8 of the same sample?
> >
> > My immediate concern is updating the vita and dsp chains. So, I really
> > just need to understand the interaction between the dsp and the vita
> > chain since they are crossing this 104/13Mhz clock domain.
> >
> > 2) usrp3 style vita framing/deframing
> > Some time after umtrx was released, B200 came out. The FPGA architecture
> > in B200 was changed from the earlier models to address dealing with
> > these integrated frontend chips. Specifically, the ADC, DAC, DSP, and
> > framing can all run on the same clock domain at full sample rate. This
> > is accomplished because the vita framing happens on 64-bit wide bus to
> > deal with the overhead of VITA headers. I suspect this architecture
> > would be better fitting for the UmTRX.
>
> I think the B200 architecture is better for UmTRX, but I'll let Andrew
> and Sergey to decide, as they know the FPGA code much better.
>
> > 3) u2plus_umtrx_v2.v
> > It looks like the ADC and DAC IQ signals are clocked in/out on the
> > positive and negative edges of the 13MHz clock. This is accomplished
> > using a 26 MHz clock. So technically, this is another clock domain
> > crossing between the 13/26MHz for the ADC/DAC signals. So, you should be
> > able to accomplish the same effect in with just the 13MHz clock using
> > the ODDR2 and IDDR2 xilinx modules.
> >
> > 4) digital loopback options?
> > I was looking for a way to do a digital loopback inside the LMS. I wasnt
> > sure if it was possible. Basically, if I set some value on the DAC pins,
> > can I get the same value of the ADC pins? I saw registers for baseband
> > loopback, but I think thats all analog. The idea is to self-test the bus
> > timing by putting a test word into the IOs.
>
> Unfortunately, there is no digital loopback in the LMS.
> As you correctly note, the baseband loopback is actually analog.
>
> > ---
> > In any case, the most important issue is #1. I want to have a host build
> > and image that is fully functional with latest UHD, lets say next week.
> > And I would like to be able to first verify with your team that we
> > havent lost any functionality, before further changes like the timed
> > command core. Sounds OK to you?
>
> Ok with me.
>
> > Thanks,
> > -josh
> >
> >
> >
> >
>
>
>
> --
> Regards,
> Alexander Chemeris.
> CEO, Fairwaves, Inc. / ООО УмРадио
> https://fairwaves.co
>
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