SRAM Prpblem

Andrew Karpenkov andrew.karpenkov at
Sat May 11 19:30:04 UTC 2013

Hi Yaniv,

I'm not very familiar with Microblaze, but I'll try to help.

There are several possible reasons:

   - SDRAM cannot run at a higher frequency than Microblaze. So you need to
   reduce the SDRAM Clock to 52 MHz or speed up Microblaze core to 104Mhz.
   - Endianess. MicroBlaze is Big endian and SDRAM (IS61NLP25672) follow
   little Endian so need to assign Buses in inverted order. e.g:: address11 to
   address0 and adress10 to adress1 and so on ... also applying this for data,
   bank and DQM busses.
   - Issue of latching edge. SDRAM datasheet says to latch data at positive

Andrew Karpenkov

2013/5/10 Yaniv Shiber <yanivshiber at>

> Hi to All
> I am trying to implement Xilinx microblaze on the umtrx2 with EMC core
> that connect to the external SRAM.  I configured the EMC to Synchronous
> mode and I used the UCF that is published at the GITHUB. If I am trying to
> deluge the MCU without the EMC the MCU seem running, but when I connect the
> EMC, the MCU stuck and I cannot download the code through the JTAG.
> Please advise how to connect the EMC core to the external SRAM ?
> thanks in advance,
> Yaniv
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