This is merely a historical archive of years 2008-2021, before the migration to mailman3.
A maintained and still updated list archive can be found at https://lists.osmocom.org/hyperkitty/list/UmTRX@lists.osmocom.org/.
Alexander Chemeris alexander.chemeris at gmail.comOn Tue, Jul 17, 2012 at 12:14 AM, Andrew Karpenkov <plddesigner at gmail.com> wrote: > Hi All, > > I added one more RX and TX units and connected them to the second LMS chip. > You can find fpga sources with full supply (both, receive and transmit) of > dual channel at akarpenkov/dual-channel branch of github repository. > > Also, we need to make some changes in HOST code: > > SR_RX_FRONT0 (base adress of RX0 frontend) was changed from 24 to 20 (dec) > SR_RX_FRONT1 (base adress of RX1 frontend) was added with value = 25 (dec) > SR_TX_FRONT (base adress of TX0 frontend) was changed from 128 to 110 (dec) > SR_TX_CTRL (base adress of control logic of TX0 channel) was changed from > 144 to 126 (dec) > SR_TX_DSP (base adress of DSP TX0 unit) was changed from 160 to 135 (dec) > SR_TX1_FRONT (base adress of TX1 frontend) was added with value = 145 (dec) > SR_TX1_CTRL (base adress of control logic of TX1 channel) was added with > value = 161 (dec) > SR_TX1_DSP (base adress of TX1 channel) was added with value = 170 (dec) > Setting register to program the UDP TX DSP port (16 + 1 in dec) are now 32 > bit wide (udp dst0 port - lower 16 bits, udp dst1 port - higher 16 bits). > > I sent flash for FPGA to Alexander and he must publish files on the site > soon. Get them here: http://people.osmocom.org/ipse/umtrx/fpga_bitsream/2012-07-16/ -- Regards, Alexander Chemeris. CEO, Fairwaves LLC / ООО УмРадио http://fairwaves.ru