Change in ...osmo-ttcn3-hacks[master]: msc: use f_expect_clear() in check IMEI tests

osmith gerrit-no-reply at lists.osmocom.org
Tue Jul 23 11:55:15 UTC 2019


osmith has uploaded this change for review. ( https://gerrit.osmocom.org/c/osmo-ttcn3-hacks/+/14900


Change subject: msc: use f_expect_clear() in check IMEI tests
......................................................................

msc: use f_expect_clear() in check IMEI tests

Fix the broken pipe race condition caused by closing the RAN connection
too early. Properly wait for clear command and send clear complete.

TC_lu_imsi_auth_tmsi_check_imei_{nack,err} do not pass anymore, because
OsmoMSC is sending the LU reject twice. Patch [1] fixes it.

Update expected-results.xml, with latest from jenkins, and don't expect
errors for TC_lu_imsi_auth_tmsi_check_imei_{nack,err} anymore.

[1] I127b27937613ea0ff29d67991c0414fca6d441d9 (osmo-msc)
Fixes: 1d118ff753d963cfe5feb2450a31bc3a51aa5eb6 ("msc: add check IMEI tests")
Change-Id: I836f76242463789c4c003feec757714827f2a31b
---
M msc/MSC_Tests.ttcn
M msc/expected-results.xml
2 files changed, 106 insertions(+), 16 deletions(-)



  git pull ssh://gerrit.osmocom.org:29418/osmo-ttcn3-hacks refs/changes/00/14900/1

diff --git a/msc/MSC_Tests.ttcn b/msc/MSC_Tests.ttcn
index c7c96eb..15ff17c 100644
--- a/msc/MSC_Tests.ttcn
+++ b/msc/MSC_Tests.ttcn
@@ -5618,7 +5618,7 @@
 	f_msc_lu_hlr();
 	f_mm_imei();
 
-	/* Expect reject. As of writing, sometimes it passes, sometimes we get a broken pipe (race condition)! */
+	/* Expect reject */
 	alt {
 	[] BSSAP.receive(tr_PDU_DTAP_MT(tr_ML3_MT_LU_Rej)) {
 		setverdict(pass);
@@ -5628,6 +5628,7 @@
 		mtc.stop;
 		}
 	}
+	f_expect_clear();
 }
 testcase TC_lu_imsi_auth_tmsi_check_imei_nack() runs on MTC_CT {
 	var BSC_ConnHdlr vc_conn;
@@ -5658,7 +5659,7 @@
 	f_msc_lu_hlr();
 	f_mm_imei();
 
-	/* Expect reject. As of writing, sometimes it passes, sometimes we get a broken pipe (race condition)! */
+	/* Expect reject */
 	alt {
 	[] BSSAP.receive(tr_PDU_DTAP_MT(tr_ML3_MT_LU_Rej)) {
 		setverdict(pass);
@@ -5668,6 +5669,7 @@
 		mtc.stop;
 		}
 	}
+	f_expect_clear();
 }
 testcase TC_lu_imsi_auth_tmsi_check_imei_err() runs on MTC_CT {
 	var BSC_ConnHdlr vc_conn;
@@ -5769,6 +5771,7 @@
 		mtc.stop;
 		}
 	}
+	f_expect_clear();
 }
 testcase TC_lu_imsi_auth_tmsi_check_imei_early_nack() runs on MTC_CT {
 	var BSC_ConnHdlr vc_conn;
@@ -5807,6 +5810,7 @@
 		mtc.stop;
 		}
 	}
+	f_expect_clear();
 }
 testcase TC_lu_imsi_auth_tmsi_check_imei_early_err() runs on MTC_CT {
 	var BSC_ConnHdlr vc_conn;
diff --git a/msc/expected-results.xml b/msc/expected-results.xml
index ca8edd2..96af4a4 100644
--- a/msc/expected-results.xml
+++ b/msc/expected-results.xml
@@ -1,11 +1,12 @@
 <?xml version="1.0"?>
-<testsuite name='Titan' tests='96' failures='2' errors='3' skipped='0' inconc='0' time='MASKED'>
+<testsuite name='Titan' tests='154' failures='9' errors='0' skipped='0' inconc='0' time='MASKED'>
   <testcase classname='MSC_Tests' name='TC_cr_before_reset' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_tmsi' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_notmsi' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_imsi_reject' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_imsi_timeout_gsup' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi' time='MASKED'/>
+  <testcase classname='MSC_Tests' name='TC_lu_imsi_auth3g_tmsi' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_cmserv_imsi_unknown' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_and_mo_call' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_auth_sai_timeout' time='MASKED'/>
@@ -31,12 +32,7 @@
   <testcase classname='MSC_Tests' name='TC_mo_setup_and_nothing' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_mo_crcx_ran_timeout' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_mo_crcx_ran_reject' time='MASKED'/>
-  <testcase classname='MSC_Tests' name='TC_mt_crcx_ran_reject' time='MASKED'>
-    <failure type='fail-verdict'>Timeout waiting for channel release
-      MSC_Tests.ttcn:MASKED MSC_Tests control part
-      MSC_Tests.ttcn:MASKED TC_mt_crcx_ran_reject testcase
-    </failure>
-  </testcase>
+  <testcase classname='MSC_Tests' name='TC_mt_crcx_ran_reject' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_mo_setup_and_dtmf_dup' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_gsup_cancel' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_1_13' time='MASKED'/>
@@ -60,6 +56,7 @@
   <testcase classname='MSC_Tests' name='TC_gsup_mt_sms_err' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_gsup_mt_sms_rp_mr' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_gsup_mo_mt_sms_rp_mr' time='MASKED'/>
+  <testcase classname='MSC_Tests' name='TC_gsup_mt_multi_part_sms' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_and_mo_ussd_single_request' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_and_mt_ussd_notification' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_and_mo_ussd_during_mt_call' time='MASKED'/>
@@ -72,6 +69,10 @@
   <testcase classname='MSC_Tests' name='TC_proc_ss_paging_fail' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_proc_ss_abort' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_cipher_complete_with_invalid_cipher' time='MASKED'/>
+  <testcase classname='MSC_Tests' name='TC_cipher_complete_1_without_cipher' time='MASKED'/>
+  <testcase classname='MSC_Tests' name='TC_cipher_complete_3_without_cipher' time='MASKED'/>
+  <testcase classname='MSC_Tests' name='TC_cipher_complete_13_without_cipher' time='MASKED'/>
+  <testcase classname='MSC_Tests' name='TC_lu_with_invalid_mcc_mnc' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_sgsap_reset' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_sgsap_lu' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_sgsap_lu_imsi_reject' time='MASKED'/>
@@ -94,23 +95,108 @@
   <testcase classname='MSC_Tests' name='TC_bssap_lu_sgsap_lu_and_mt_call' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_sgsap_lu_and_mt_call' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_sgsap_vlr_failure' time='MASKED'/>
-  <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_3_1_log_msc_debug' time='MASKED'/>
-  <testcase classname='MSC_Tests' name='TC_gsup_mt_multi_part_sms' time='MASKED'/>
-  <testcase classname='MSC_Tests' name='TC_mo_cc_bssmap_clear' time='MASKED'/>
+  <testcase classname='MSC_Tests' name='TC_ho_inter_bsc_unknown_cell' time='MASKED'/>
+  <testcase classname='MSC_Tests' name='TC_ho_inter_bsc' time='MASKED'/>
+  <testcase classname='MSC_Tests' name='TC_ho_inter_msc_out' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_imsi_auth3g_tmsi_check_imei' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_tmsi_check_imei' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_notmsi_check_imei' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei_nack' time='MASKED'/>
-    <error type='DTE'></error>
-  </testcase>
   <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei_err' time='MASKED'/>
-    <error type='DTE'></error>
-  </testcase>
   <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei_early' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_imsi_auth3g_tmsi_check_imei_early' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_tmsi_check_imei_early' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_imsi_noauth_notmsi_check_imei_early' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei_early_nack' time='MASKED'/>
   <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_check_imei_early_err' time='MASKED'/>
+  <testcase classname='MSC_Tests' name='TC_lu_imsi_auth_tmsi_encr_3_1_log_msc_debug' time='MASKED'/>
+  <testcase classname='MSC_Tests' name='TC_mo_cc_bssmap_clear' time='MASKED'/>
+  <testcase classname='MSC_Tests' name='TC_lu_and_mt_call_osmux' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_imsi_reject' time='MASKED'>
+    <failure type='fail-verdict'>Tguard timeout
+      MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part
+      MSC_Tests_Iu.ttcn:MASKED TC_iu_lu_imsi_reject testcase
+    </failure>
+  </testcase>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_imsi_timeout_gsup' time='MASKED'>
+    <failure type='fail-verdict'>Tguard timeout
+      MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part
+      MSC_Tests_Iu.ttcn:MASKED TC_iu_lu_imsi_timeout_gsup testcase
+    </failure>
+  </testcase>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_imsi_auth3g_tmsi' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_cmserv_imsi_unknown' time='MASKED'>
+    <failure type='fail-verdict'>Tguard timeout
+      MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part
+      MSC_Tests_Iu.ttcn:MASKED TC_iu_cmserv_imsi_unknown testcase
+    </failure>
+  </testcase>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mo_call' time='MASKED'>
+    <failure type='fail-verdict'>Tguard timeout
+      MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part
+      MSC_Tests_Iu.ttcn:MASKED TC_iu_lu_and_mo_call testcase
+    </failure>
+  </testcase>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_auth_sai_timeout' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_auth_sai_err' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_release_request' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_disconnect' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_by_imei' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_imsi_detach_by_imsi' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_imsi_detach_by_tmsi' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_imsi_detach_by_imei' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_emerg_call_imei_reject' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_emerg_call_imsi' time='MASKED'>
+    <failure type='fail-verdict'>Tguard timeout
+      MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part
+      MSC_Tests_Iu.ttcn:MASKED TC_iu_emerg_call_imsi testcase
+    </failure>
+  </testcase>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_establish_and_nothing' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_mo_setup_and_nothing' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_mo_crcx_ran_timeout' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_mo_crcx_ran_reject' time='MASKED'>
+    <failure type='fail-verdict'>Timeout waiting for channel release
+      MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part
+      MSC_Tests_Iu.ttcn:MASKED TC_iu_mo_crcx_ran_reject testcase
+    </failure>
+  </testcase>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_mt_crcx_ran_reject' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_cancel' time='MASKED'>
+    <failure type='fail-verdict'>Tguard timeout
+      MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part
+      MSC_Tests_Iu.ttcn:MASKED TC_iu_gsup_cancel testcase
+    </failure>
+  </testcase>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_mo_release_timeout' time='MASKED'/>
+  <testcase classname='MSC_Tests' name='TC_reset_two_1iu' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mo_sms' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mt_sms' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mt_sms_paging_and_nothing' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_smpp_mo_sms' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mo_sms' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mo_smma' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mt_sms_ack' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mt_sms_err' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mt_sms_rp_mr' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_gsup_mo_mt_sms_rp_mr' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mo_ussd_single_request' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mt_ussd_notification' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mo_ussd_during_mt_call' time='MASKED'>
+    <failure type='fail-verdict'>Tguard timeout
+      MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part
+      MSC_Tests_Iu.ttcn:MASKED TC_iu_lu_and_mo_ussd_during_mt_call testcase
+    </failure>
+  </testcase>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mt_ussd_during_mt_call' time='MASKED'>
+    <failure type='fail-verdict'>Tguard timeout
+      MSC_Tests_Iu.ttcn:MASKED MSC_Tests_Iu control part
+      MSC_Tests_Iu.ttcn:MASKED TC_iu_lu_and_mt_ussd_during_mt_call testcase
+    </failure>
+  </testcase>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_mo_ussd_mo_release' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_and_ss_session_timeout' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_iu_lu_with_invalid_mcc_mnc' time='MASKED'/>
+  <testcase classname='MSC_Tests_Iu' name='TC_mo_cc_iu_release' time='MASKED'/>
 </testsuite>

-- 
To view, visit https://gerrit.osmocom.org/c/osmo-ttcn3-hacks/+/14900
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Gerrit-Project: osmo-ttcn3-hacks
Gerrit-Branch: master
Gerrit-Change-Id: I836f76242463789c4c003feec757714827f2a31b
Gerrit-Change-Number: 14900
Gerrit-PatchSet: 1
Gerrit-Owner: osmith <osmith at sysmocom.de>
Gerrit-MessageType: newchange
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