Change in osmo-ccid-firmware[master]: configure GCLK for ISO baud rates

Kévin Redon gerrit-no-reply at lists.osmocom.org
Thu Apr 25 14:08:31 UTC 2019


Kévin Redon has uploaded this change for review. ( https://gerrit.osmocom.org/13781


Change subject: configure GCLK for ISO baud rates
......................................................................

configure GCLK for ISO baud rates

the SERCOMM clock triplet 0.5 MHz (100 MHz / 200),
7.0588 MHz (120 MHz / 17), and 50 MHz (100 MHz / 2) allows to
generate all possible ISO 7816 baud rates (from
F = 2048 / D = 1 @ f = 2.5 MHz -> 1220 bps to
F = 372 / D = 64 @ f = 20 MHz -> 3.4 Mbps) with a maximum baud
rate error of 2.57 %, for available SIM clocks 2.5, 5, 10, 20 MHz.
2.57% means a bit more than quarter a bit might be wrong after the
11 bits ISO transmission (still less than half a bit).
This triplet is one of the optimum when 3 clocks are used.
An additional clock would be required for higher accuracy.

The 50 MHz clock is re-used from the RMII clock output.

Change-Id: I2c69848582e49031fa6453f535a2bf1408f8e22e
---
M sysmoOCTSIM/atmel_start_config.atstart
M sysmoOCTSIM/config/hpl_gclk_config.h
M sysmoOCTSIM/config/peripheral_clk_config.h
3 files changed, 17 insertions(+), 17 deletions(-)



  git pull ssh://gerrit.osmocom.org:29418/osmo-ccid-firmware refs/changes/81/13781/1

diff --git a/sysmoOCTSIM/atmel_start_config.atstart b/sysmoOCTSIM/atmel_start_config.atstart
index 6357a74..3854fb5 100644
--- a/sysmoOCTSIM/atmel_start_config.atstart
+++ b/sysmoOCTSIM/atmel_start_config.atstart
@@ -666,7 +666,7 @@
       enable_gclk_gen_3: true
       enable_gclk_gen_4: true
       enable_gclk_gen_5: true
-      enable_gclk_gen_6: false
+      enable_gclk_gen_6: true
       enable_gclk_gen_7: false
       enable_gclk_gen_8: false
       enable_gclk_gen_9: false
@@ -710,7 +710,7 @@
       gclk_arch_gen_5_oe: true
       gclk_arch_gen_5_oov: false
       gclk_arch_gen_5_runstdby: false
-      gclk_arch_gen_6_enable: false
+      gclk_arch_gen_6_enable: true
       gclk_arch_gen_6_idc: false
       gclk_arch_gen_6_oe: false
       gclk_arch_gen_6_oov: false
@@ -742,7 +742,7 @@
       gclk_gen_1_div: 1
       gclk_gen_1_div_sel: false
       gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M)
-      gclk_gen_2_div: 30
+      gclk_gen_2_div: 200
       gclk_gen_2_div_sel: false
       gclk_gen_2_oscillator: Digital Phase Locked Loop (DPLL1)
       gclk_gen_3_div: 1
@@ -754,9 +754,9 @@
       gclk_gen_5_div: 5
       gclk_gen_5_div_sel: false
       gclk_gen_5_oscillator: Digital Phase Locked Loop (DPLL1)
-      gclk_gen_6_div: 1
+      gclk_gen_6_div: 17
       gclk_gen_6_div_sel: false
-      gclk_gen_6_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
+      gclk_gen_6_oscillator: Digital Phase Locked Loop (DPLL0)
       gclk_gen_7_div: 1
       gclk_gen_7_div_sel: false
       gclk_gen_7_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)
diff --git a/sysmoOCTSIM/config/hpl_gclk_config.h b/sysmoOCTSIM/config/hpl_gclk_config.h
index 81a1f03..158fc93 100644
--- a/sysmoOCTSIM/config/hpl_gclk_config.h
+++ b/sysmoOCTSIM/config/hpl_gclk_config.h
@@ -226,7 +226,7 @@
 //<o> Generic clock generator 2 division <0x0000-0xFFFF>
 // <id> gclk_gen_2_div
 #ifndef CONF_GCLK_GEN_2_DIV
-#define CONF_GCLK_GEN_2_DIV 30
+#define CONF_GCLK_GEN_2_DIV 200
 #endif
 // </h>
 // </e>
@@ -463,7 +463,7 @@
 // <i> Indicates whether generic clock 6 configuration is enabled or not
 // <id> enable_gclk_gen_6
 #ifndef CONF_GCLK_GENERATOR_6_CONFIG
-#define CONF_GCLK_GENERATOR_6_CONFIG 0
+#define CONF_GCLK_GENERATOR_6_CONFIG 1
 #endif
 
 // <h> Generic Clock Generator Control
@@ -480,7 +480,7 @@
 // <i> This defines the clock source for generic clock generator 6
 // <id> gclk_gen_6_oscillator
 #ifndef CONF_GCLK_GEN_6_SOURCE
-#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_DPLL0
 #endif
 
 // <q> Run in Standby
@@ -522,7 +522,7 @@
 // <i> Indicates whether Generic Clock Generator Enable is enabled or not
 // <id> gclk_arch_gen_6_enable
 #ifndef CONF_GCLK_GEN_6_GENEN
-#define CONF_GCLK_GEN_6_GENEN 0
+#define CONF_GCLK_GEN_6_GENEN 1
 #endif
 // </h>
 
@@ -530,7 +530,7 @@
 //<o> Generic clock generator 6 division <0x0000-0xFFFF>
 // <id> gclk_gen_6_div
 #ifndef CONF_GCLK_GEN_6_DIV
-#define CONF_GCLK_GEN_6_DIV 1
+#define CONF_GCLK_GEN_6_DIV 17
 #endif
 // </h>
 // </e>
diff --git a/sysmoOCTSIM/config/peripheral_clk_config.h b/sysmoOCTSIM/config/peripheral_clk_config.h
index 2ae1f63..f794792 100644
--- a/sysmoOCTSIM/config/peripheral_clk_config.h
+++ b/sysmoOCTSIM/config/peripheral_clk_config.h
@@ -81,7 +81,7 @@
  * \brief SERCOM0's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 3333333
+#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 500000
 #endif
 
 /**
@@ -161,7 +161,7 @@
  * \brief SERCOM1's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 3333333
+#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 500000
 #endif
 
 /**
@@ -241,7 +241,7 @@
  * \brief SERCOM2's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 3333333
+#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 500000
 #endif
 
 /**
@@ -321,7 +321,7 @@
  * \brief SERCOM3's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 3333333
+#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 500000
 #endif
 
 /**
@@ -401,7 +401,7 @@
  * \brief SERCOM4's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM4_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 3333333
+#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 500000
 #endif
 
 /**
@@ -481,7 +481,7 @@
  * \brief SERCOM5's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM5_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 3333333
+#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 500000
 #endif
 
 /**
@@ -561,7 +561,7 @@
  * \brief SERCOM6's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM6_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM6_CORE_FREQUENCY 3333333
+#define CONF_GCLK_SERCOM6_CORE_FREQUENCY 500000
 #endif
 
 /**

-- 
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Gerrit-Project: osmo-ccid-firmware
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2c69848582e49031fa6453f535a2bf1408f8e22e
Gerrit-Change-Number: 13781
Gerrit-PatchSet: 1
Gerrit-Owner: Kévin Redon <kredon at sysmocom.de>
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