<p>Kévin Redon has uploaded this change for <strong>review</strong>.</p><p><a href="https://gerrit.osmocom.org/13781">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">configure GCLK for ISO baud rates<br><br>the SERCOMM clock triplet 0.5 MHz (100 MHz / 200),<br>7.0588 MHz (120 MHz / 17), and 50 MHz (100 MHz / 2) allows to<br>generate all possible ISO 7816 baud rates (from<br>F = 2048 / D = 1 @ f = 2.5 MHz -> 1220 bps to<br>F = 372 / D = 64 @ f = 20 MHz -> 3.4 Mbps) with a maximum baud<br>rate error of 2.57 %, for available SIM clocks 2.5, 5, 10, 20 MHz.<br>2.57% means a bit more than quarter a bit might be wrong after the<br>11 bits ISO transmission (still less than half a bit).<br>This triplet is one of the optimum when 3 clocks are used.<br>An additional clock would be required for higher accuracy.<br><br>The 50 MHz clock is re-used from the RMII clock output.<br><br>Change-Id: I2c69848582e49031fa6453f535a2bf1408f8e22e<br>---<br>M sysmoOCTSIM/atmel_start_config.atstart<br>M sysmoOCTSIM/config/hpl_gclk_config.h<br>M sysmoOCTSIM/config/peripheral_clk_config.h<br>3 files changed, 17 insertions(+), 17 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://gerrit.osmocom.org:29418/osmo-ccid-firmware refs/changes/81/13781/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;"><span>diff --git a/sysmoOCTSIM/atmel_start_config.atstart b/sysmoOCTSIM/atmel_start_config.atstart</span><br><span>index 6357a74..3854fb5 100644</span><br><span>--- a/sysmoOCTSIM/atmel_start_config.atstart</span><br><span>+++ b/sysmoOCTSIM/atmel_start_config.atstart</span><br><span>@@ -666,7 +666,7 @@</span><br><span> enable_gclk_gen_3: true</span><br><span> enable_gclk_gen_4: true</span><br><span> enable_gclk_gen_5: true</span><br><span style="color: hsl(0, 100%, 40%);">- enable_gclk_gen_6: false</span><br><span style="color: hsl(120, 100%, 40%);">+ enable_gclk_gen_6: true</span><br><span> enable_gclk_gen_7: false</span><br><span> enable_gclk_gen_8: false</span><br><span> enable_gclk_gen_9: false</span><br><span>@@ -710,7 +710,7 @@</span><br><span> gclk_arch_gen_5_oe: true</span><br><span> gclk_arch_gen_5_oov: false</span><br><span> gclk_arch_gen_5_runstdby: false</span><br><span style="color: hsl(0, 100%, 40%);">- gclk_arch_gen_6_enable: false</span><br><span style="color: hsl(120, 100%, 40%);">+ gclk_arch_gen_6_enable: true</span><br><span> gclk_arch_gen_6_idc: false</span><br><span> gclk_arch_gen_6_oe: false</span><br><span> gclk_arch_gen_6_oov: false</span><br><span>@@ -742,7 +742,7 @@</span><br><span> gclk_gen_1_div: 1</span><br><span> gclk_gen_1_div_sel: false</span><br><span> gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M)</span><br><span style="color: hsl(0, 100%, 40%);">- gclk_gen_2_div: 30</span><br><span style="color: hsl(120, 100%, 40%);">+ gclk_gen_2_div: 200</span><br><span> gclk_gen_2_div_sel: false</span><br><span> gclk_gen_2_oscillator: Digital Phase Locked Loop (DPLL1)</span><br><span> gclk_gen_3_div: 1</span><br><span>@@ -754,9 +754,9 @@</span><br><span> gclk_gen_5_div: 5</span><br><span> gclk_gen_5_div_sel: false</span><br><span> gclk_gen_5_oscillator: Digital Phase Locked Loop (DPLL1)</span><br><span style="color: hsl(0, 100%, 40%);">- gclk_gen_6_div: 1</span><br><span style="color: hsl(120, 100%, 40%);">+ gclk_gen_6_div: 17</span><br><span> gclk_gen_6_div_sel: false</span><br><span style="color: hsl(0, 100%, 40%);">- gclk_gen_6_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)</span><br><span style="color: hsl(120, 100%, 40%);">+ gclk_gen_6_oscillator: Digital Phase Locked Loop (DPLL0)</span><br><span> gclk_gen_7_div: 1</span><br><span> gclk_gen_7_div_sel: false</span><br><span> gclk_gen_7_oscillator: External Crystal Oscillator 8-48MHz (XOSC1)</span><br><span>diff --git a/sysmoOCTSIM/config/hpl_gclk_config.h b/sysmoOCTSIM/config/hpl_gclk_config.h</span><br><span>index 81a1f03..158fc93 100644</span><br><span>--- a/sysmoOCTSIM/config/hpl_gclk_config.h</span><br><span>+++ b/sysmoOCTSIM/config/hpl_gclk_config.h</span><br><span>@@ -226,7 +226,7 @@</span><br><span> //<o> Generic clock generator 2 division <0x0000-0xFFFF></span><br><span> // <id> gclk_gen_2_div</span><br><span> #ifndef CONF_GCLK_GEN_2_DIV</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_GEN_2_DIV 30</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_GEN_2_DIV 200</span><br><span> #endif</span><br><span> // </h></span><br><span> // </e></span><br><span>@@ -463,7 +463,7 @@</span><br><span> // <i> Indicates whether generic clock 6 configuration is enabled or not</span><br><span> // <id> enable_gclk_gen_6</span><br><span> #ifndef CONF_GCLK_GENERATOR_6_CONFIG</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_GENERATOR_6_CONFIG 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_GENERATOR_6_CONFIG 1</span><br><span> #endif</span><br><span> </span><br><span> // <h> Generic Clock Generator Control</span><br><span>@@ -480,7 +480,7 @@</span><br><span> // <i> This defines the clock source for generic clock generator 6</span><br><span> // <id> gclk_gen_6_oscillator</span><br><span> #ifndef CONF_GCLK_GEN_6_SOURCE</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC1</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_DPLL0</span><br><span> #endif</span><br><span> </span><br><span> // <q> Run in Standby</span><br><span>@@ -522,7 +522,7 @@</span><br><span> // <i> Indicates whether Generic Clock Generator Enable is enabled or not</span><br><span> // <id> gclk_arch_gen_6_enable</span><br><span> #ifndef CONF_GCLK_GEN_6_GENEN</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_GEN_6_GENEN 0</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_GEN_6_GENEN 1</span><br><span> #endif</span><br><span> // </h></span><br><span> </span><br><span>@@ -530,7 +530,7 @@</span><br><span> //<o> Generic clock generator 6 division <0x0000-0xFFFF></span><br><span> // <id> gclk_gen_6_div</span><br><span> #ifndef CONF_GCLK_GEN_6_DIV</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_GEN_6_DIV 1</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_GEN_6_DIV 17</span><br><span> #endif</span><br><span> // </h></span><br><span> // </e></span><br><span>diff --git a/sysmoOCTSIM/config/peripheral_clk_config.h b/sysmoOCTSIM/config/peripheral_clk_config.h</span><br><span>index 2ae1f63..f794792 100644</span><br><span>--- a/sysmoOCTSIM/config/peripheral_clk_config.h</span><br><span>+++ b/sysmoOCTSIM/config/peripheral_clk_config.h</span><br><span>@@ -81,7 +81,7 @@</span><br><span> * \brief SERCOM0's Core Clock frequency</span><br><span> */</span><br><span> #ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 3333333</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 500000</span><br><span> #endif</span><br><span> </span><br><span> /**</span><br><span>@@ -161,7 +161,7 @@</span><br><span> * \brief SERCOM1's Core Clock frequency</span><br><span> */</span><br><span> #ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 3333333</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 500000</span><br><span> #endif</span><br><span> </span><br><span> /**</span><br><span>@@ -241,7 +241,7 @@</span><br><span> * \brief SERCOM2's Core Clock frequency</span><br><span> */</span><br><span> #ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 3333333</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 500000</span><br><span> #endif</span><br><span> </span><br><span> /**</span><br><span>@@ -321,7 +321,7 @@</span><br><span> * \brief SERCOM3's Core Clock frequency</span><br><span> */</span><br><span> #ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 3333333</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 500000</span><br><span> #endif</span><br><span> </span><br><span> /**</span><br><span>@@ -401,7 +401,7 @@</span><br><span> * \brief SERCOM4's Core Clock frequency</span><br><span> */</span><br><span> #ifndef CONF_GCLK_SERCOM4_CORE_FREQUENCY</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 3333333</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 500000</span><br><span> #endif</span><br><span> </span><br><span> /**</span><br><span>@@ -481,7 +481,7 @@</span><br><span> * \brief SERCOM5's Core Clock frequency</span><br><span> */</span><br><span> #ifndef CONF_GCLK_SERCOM5_CORE_FREQUENCY</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 3333333</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 500000</span><br><span> #endif</span><br><span> </span><br><span> /**</span><br><span>@@ -561,7 +561,7 @@</span><br><span> * \brief SERCOM6's Core Clock frequency</span><br><span> */</span><br><span> #ifndef CONF_GCLK_SERCOM6_CORE_FREQUENCY</span><br><span style="color: hsl(0, 100%, 40%);">-#define CONF_GCLK_SERCOM6_CORE_FREQUENCY 3333333</span><br><span style="color: hsl(120, 100%, 40%);">+#define CONF_GCLK_SERCOM6_CORE_FREQUENCY 500000</span><br><span> #endif</span><br><span> </span><br><span> /**</span><br><span></span><br></pre><p>To view, visit <a href="https://gerrit.osmocom.org/13781">change 13781</a>. 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<div style="display:none"> Gerrit-Project: osmo-ccid-firmware </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I2c69848582e49031fa6453f535a2bf1408f8e22e </div>
<div style="display:none"> Gerrit-Change-Number: 13781 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Kévin Redon <kredon@sysmocom.de> </div>