Change in osmo-ccid-firmware[master]: change SERCOM clock to 3.3 MHz

Kévin Redon gerrit-no-reply at lists.osmocom.org
Tue Apr 16 23:29:22 UTC 2019


Kévin Redon has uploaded this change for review. ( https://gerrit.osmocom.org/13680


Change subject: change SERCOM clock to 3.3 MHz
......................................................................

change SERCOM clock to 3.3 MHz

we use the SERCOM peripheral for USART (in 7816 mode SIM card
communication) in synchronous mode (TX and RX clock are the same).
in this mode only the 8 least significant bits of the BAUD register
are used (see TRM 33.6.2.3 Clock Generation – Baud-Rate Generator).
When the SERCOM is clocked at 100 MHz the minimum resulting baud
rate would be 100E6 / (2 * 255 + 1) = 195694 bps.
clocking SERCOM at 3.33 MHz also to have a baud rate of 6720 bps
(~ 3.33E6 / (2 * 247 + 1)), used after reset to read the ATR.

Change-Id: Id60322e092a6652a89821fc737d5336d79a1420c
---
M sysmoOCTSIM/config/hpl_gclk_config.h
M sysmoOCTSIM/config/peripheral_clk_config.h
2 files changed, 12 insertions(+), 12 deletions(-)



  git pull ssh://gerrit.osmocom.org:29418/osmo-ccid-firmware refs/changes/80/13680/1

diff --git a/sysmoOCTSIM/config/hpl_gclk_config.h b/sysmoOCTSIM/config/hpl_gclk_config.h
index 6b7586c..71c26e1 100644
--- a/sysmoOCTSIM/config/hpl_gclk_config.h
+++ b/sysmoOCTSIM/config/hpl_gclk_config.h
@@ -226,7 +226,7 @@
 //<o> Generic clock generator 2 division <0x0000-0xFFFF>
 // <id> gclk_gen_2_div
 #ifndef CONF_GCLK_GEN_2_DIV
-#define CONF_GCLK_GEN_2_DIV 1
+#define CONF_GCLK_GEN_2_DIV 30
 #endif
 // </h>
 // </e>
@@ -311,7 +311,7 @@
 // <i> Indicates whether generic clock 4 configuration is enabled or not
 // <id> enable_gclk_gen_4
 #ifndef CONF_GCLK_GENERATOR_4_CONFIG
-#define CONF_GCLK_GENERATOR_4_CONFIG 0
+#define CONF_GCLK_GENERATOR_4_CONFIG 1
 #endif
 
 // <h> Generic Clock Generator Control
@@ -328,7 +328,7 @@
 // <i> This defines the clock source for generic clock generator 4
 // <id> gclk_gen_4_oscillator
 #ifndef CONF_GCLK_GEN_4_SOURCE
-#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC1
+#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_DPLL1
 #endif
 
 // <q> Run in Standby
@@ -370,7 +370,7 @@
 // <i> Indicates whether Generic Clock Generator Enable is enabled or not
 // <id> gclk_arch_gen_4_enable
 #ifndef CONF_GCLK_GEN_4_GENEN
-#define CONF_GCLK_GEN_4_GENEN 0
+#define CONF_GCLK_GEN_4_GENEN 1
 #endif
 // </h>
 
diff --git a/sysmoOCTSIM/config/peripheral_clk_config.h b/sysmoOCTSIM/config/peripheral_clk_config.h
index 91c5c86..4bff6ff 100644
--- a/sysmoOCTSIM/config/peripheral_clk_config.h
+++ b/sysmoOCTSIM/config/peripheral_clk_config.h
@@ -81,7 +81,7 @@
  * \brief SERCOM0's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 100000000
+#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 3333333
 #endif
 
 /**
@@ -161,7 +161,7 @@
  * \brief SERCOM1's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 100000000
+#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 3333333
 #endif
 
 /**
@@ -241,7 +241,7 @@
  * \brief SERCOM2's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 100000000
+#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 3333333
 #endif
 
 /**
@@ -321,7 +321,7 @@
  * \brief SERCOM3's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 100000000
+#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 3333333
 #endif
 
 /**
@@ -401,7 +401,7 @@
  * \brief SERCOM4's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM4_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 100000000
+#define CONF_GCLK_SERCOM4_CORE_FREQUENCY 3333333
 #endif
 
 /**
@@ -481,7 +481,7 @@
  * \brief SERCOM5's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM5_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 100000000
+#define CONF_GCLK_SERCOM5_CORE_FREQUENCY 3333333
 #endif
 
 /**
@@ -561,7 +561,7 @@
  * \brief SERCOM6's Core Clock frequency
  */
 #ifndef CONF_GCLK_SERCOM6_CORE_FREQUENCY
-#define CONF_GCLK_SERCOM6_CORE_FREQUENCY 100000000
+#define CONF_GCLK_SERCOM6_CORE_FREQUENCY 3333333
 #endif
 
 /**
@@ -601,7 +601,7 @@
 
 // <i> Select the clock source for CORE.
 #ifndef CONF_GCLK_SERCOM7_CORE_SRC
-#define CONF_GCLK_SERCOM7_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val
+#define CONF_GCLK_SERCOM7_CORE_SRC GCLK_PCHCTRL_GEN_GCLK4_Val
 #endif
 
 // <y> Slow Clock Source

-- 
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Gerrit-Project: osmo-ccid-firmware
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id60322e092a6652a89821fc737d5336d79a1420c
Gerrit-Change-Number: 13680
Gerrit-PatchSet: 1
Gerrit-Owner: Kévin Redon <kredon at sysmocom.de>
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