jtag trouble j100i

Mathias K. kesmtp at freenet.de
Mon May 7 18:37:30 UTC 2012


Hello,


i try to connect the j100i with the latest openocd (git) but there is always something wrong with
the embedded ice module. My configuration script is based on openocd_calypso.cfg and the
calypso_magic.svf. The main difference i can see is the idcode and the irlen. My changes in the
script looks like this:

set _CPUTAPID 0xf9001807

jtag newtap $_CHIPNAME dsp -expected-id 0x00000000 -irlen 5
jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID

This changes are based on some appended svf scripts that simple scan the jtag chain to get more
informations.
The jtag_idcodes.svf returns the shifted idcodes like this:

SDR 32 TDI(ffffffff);
length = 32
TDI = 0xFFFFFFFF
TDO read = 0xF200300E
SDR 32 TDI(ffffffff);
length = 32
TDI = 0xFFFFFFFF
TDO read = 0xFFFFFFFF

The jtag_devices.svf told me the device count and the possible ir register count/length:

SIR 32 TDI(ffffffff);
length = 32
TDI = 0xFFFFFFFF
TDO read = 0xFFFFFE25

TDO: 11...11000100101 Looks like 3 ir registers with 4,3 and 2 bit length

SDR 32 TDI(ffffffff);
length = 32
TDI = 0xFFFFFFFF
TDO read = 0xFFFFFFFC

TDO: 11...1100 Looks like 2 devices


But every access to the embedded ice registers (they are located in the internal scan chain 2)
result in random (most time zero) values for the comms ctrl register and a cpu halt state. Is there
anything wrong? Is there a different "magic" 0x0b jtag command or argument for this kind of cpu?


Thanks & Regards,

Mathias
-------------- next part --------------
! based on http://www.fpga4fun.com/JTAG3.html

STATE RESET;
! LOAD IDCODE istruction
RUNTEST IDLE 5 TCK;
ENDDR DRPAUSE;

SDR 32 TDI(ffffffff);
SDR 32 TDI(ffffffff);
SDR 32 TDI(ffffffff);
SDR 32 TDI(ffffffff);
SDR 32 TDI(ffffffff);
SDR 32 TDI(ffffffff);
SDR 32 TDI(ffffffff);
SDR 32 TDI(ffffffff);
-------------- next part --------------
! http://www.fpga4fun.com/JTAG3.html

STATE RESET;
! LOAD IDCODE istruction
RUNTEST IDLE 5 TCK;
ENDIR IRPAUSE;
ENDDR DRPAUSE;

! fill ir reg with ones
! set devices in bypass mode
SIR 32 TDI(ffffffff);
SIR 32 TDI(ffffffff);
SIR 32 TDI(ffffffff);
SIR 32 TDI(ffffffff);
SIR 32 TDI(ffffffff);
SIR 32 TDI(ffffffff);
SIR 32 TDI(ffffffff);
SIR 32 TDI(ffffffff);

! flush dr register
SDR 32 TDI(00000000);
SDR 32 TDI(00000000);
SDR 32 TDI(00000000);
SDR 32 TDI(00000000);
SDR 32 TDI(00000000);
SDR 32 TDI(00000000);

! send ones to dr
! at the first one received
! there are no more devices
SDR 32 TDI(ffffffff);
SDR 32 TDI(ffffffff);
SDR 32 TDI(ffffffff);
SDR 32 TDI(ffffffff);
SDR 32 TDI(ffffffff);
SDR 32 TDI(ffffffff);


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