spaar at mirider.augusta.de
Tue May 17 07:29:17 UTC 2011
On Tue, 17 May 2011 00:09:13 +0200, "l--putt" <ichgeh at l--putt.de> wrote:
> Saving power
> Having everything on and at maximum clock drains the battery _fast_!
> With the ULPD, we actually have the appropriate solution build into the
> Calypso. I guess other chipsets have something similar.
> It is neat to get the timing and power sequence right. But since the
> TDMA timing is affected, Layer 1 must be aware of those clock/power
> changes or at least tolerate to be turned on and off. Does anybody right
> away have ideas how to approach this?
A few notes, I don't remember the details: The basic idea is to only
receive in idle mode when its necessary. This means listening only for
the paging group of the IMSI and doing the neighbour cell measurements.
During the other time the processor can be stopped. There are different
levels to which extend the clock is stopped, for saving the most power
only the 32 kHz crystal remains active. However this requires some
calibration, otherwise the TDMA frames could be missed after sleeping.
Most of this calibration can be done with the help of the hardware,
its always done before switching to 32 kHz.
Dieter Spaar, Germany spaar at mirider.augusta.de
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