From alexander.chemeris at gmail.com  Sun Feb  3 12:54:43 2013
From: alexander.chemeris at gmail.com (Alexander Chemeris)
Date: Sun, 3 Feb 2013 16:54:43 +0400
Subject: Dual-channel support on UmTRX
In-Reply-To: <CABmJbFWkimMtmJQzz4+Wt6COc1ZyiBkz+6k0F+U9OqFCf6RVzg@mail.gmail.com>
References: <CABmJbFWkimMtmJQzz4+Wt6COc1ZyiBkz+6k0F+U9OqFCf6RVzg@mail.gmail.com>
Message-ID: <CABmJbFXdHYgkCuhYwbsh69pB80hqYLCMm=i6q1Wj6VUOO-hqYw@mail.gmail.com>

Hi all,

I've published the pre-compiled UmTRX firmware with dual-channel
support in our downloads area:
http://people.osmocom.org/ipse/umtrx-v2/fpga_bitsream/2013-02-03-394f48b7/
UmTRX LEDs new indicate Rx/Tx on both channels independently - LEDs
A/C indicate Tx1/Rx1 and LEDs E/B indicate Tx2/Rx2:
https://code.google.com/p/umtrx/wiki/FeaturesAndTechnicalSpecification#UmTRX_LEDs

Note, that you have to use the latest 'fairwaves/umtrx' branch of our
github repo on the host side for this firmware to work properly:
https://github.com/fairwaves/UHD-Fairwaves



From alexander.chemeris at gmail.com  Sun Feb  3 21:18:05 2013
From: alexander.chemeris at gmail.com (Alexander Chemeris)
Date: Mon, 4 Feb 2013 01:18:05 +0400
Subject: MAC address range for UmTRX has been assigned
Message-ID: <CABmJbFW7ogkTWusS3WRb1SU6pixfZtCHCC70Cu1sy89nuoB+oQ@mail.gmail.com>

Hi all,

A one more bit of good news - we've been assigned with a range of MAC
addresses we could use for UmTRX's. Many thanks for Openmoko Inc and
Harald Welte for generously offering this service to open-source
hardware projects for free!

Now we have to setup a procedure to make sure all UmTRX's get out of
the fab with unique MAC addresses.

---------- Forwarded message ----------
From: Harald Welte <laforge at gnumonks.org>
Date: Mon, Feb 4, 2013 at 1:04 AM
Subject: Re: Request for the OUI range for UmTRX board
To: Alexander Chemeris <alexander.chemeris at gmail.com>


Hi Alexander.

00-1F-11-02-19-00 to 00-1F-11-02-28-ff

see http://wiki.openmoko.org/wiki/OUI#MAC_addresses

Regards,
        Harald

On Mon, Feb 04, 2013 at 12:08:45AM +0400, Alexander Chemeris wrote:
> Hi,
>
> I'd like to request a range of 0xfff MAC addresses for the use with
> UmTRX boards.
>
> Project information
> ==============
>
> Name: UmTRX
> Short description: UmTRX is a dual-channel wide-band SDR transceiver
> with 1GbE connection.
> Software License: GPLv3
> Hardware License: CC BY-SA 3.0
> Link: https://code.google.com/p/umtrx/
> Number of MAC addresses: 0xfff
>
> --
> Regards,
> Alexander Chemeris.
> CEO, Fairwaves LLC / ??? ???????
> http://fairwaves.ru

--
- Harald Welte <laforge at gnumonks.org>           http://laforge.gnumonks.org/
============================================================================
"Privacy in residential applications is a desirable marketing option."
                                                  (ETSI EN 300 175-7 Ch. A6)


--
Regards,
Alexander Chemeris.
CEO, Fairwaves LLC / ??? ???????
http://fairwaves.ru



From 246tnt at gmail.com  Wed Feb  6 20:53:27 2013
From: 246tnt at gmail.com (Sylvain Munaut)
Date: Wed, 6 Feb 2013 21:53:27 +0100
Subject: LMS RX PLL questions
Message-ID: <CAHL+j090_=LogfW8+PZQdgzAqXuZ5rxszrReG0hLgmkUmE1SLw@mail.gmail.com>

Hi,

I have a couple questions about the RX PLL in the LMS chip:

 - What are the various LOBUF  for ? (1/2/3). Do they correspond the
the 3 input of the RX side ? I see they're controlled by the SELOUT
bits, but I have no idea how to choose. Should it be matched to
LNASEL_RXFE ?

 - What's the expected levels of the LO harmonics ?  In my tests I see
to measure around -10 dB for 3xLO and ~ -22 dB for 5x LO. Is there any
way to improve this ?

   The method I used to measure is to feed 400 MHz narrow bw signal to
the input. Tune LMS to 400 MHz and measure the received strength, then
change the signal generator to TX a signal at 1.2 GHz and measure
again, then at 2GHz, and so on ...


Cheers,

    Sylvain



From 246tnt at gmail.com  Thu Feb  7 21:59:13 2013
From: 246tnt at gmail.com (Sylvain Munaut)
Date: Thu, 7 Feb 2013 22:59:13 +0100
Subject: LMS RX PLL questions
In-Reply-To: <51141E83.6090708@limemicro.com>
References: <CAHL+j090_=LogfW8+PZQdgzAqXuZ5rxszrReG0hLgmkUmE1SLw@mail.gmail.com>
	<51141E83.6090708@limemicro.com>
Message-ID: <CAHL+j09EBwk9g35JVqhROiTrXtvZrF8v9qR-ep_A6Vzt-fgzFA@mail.gmail.com>

Hi Ricardas,


Thanks for the quick answer. A couple of followup questions :


> You should see 2xLO, 4xLO ... as well.

Oh really ? Mmm, I couldn't see those. I guess they're much lower than
the odd harmonics and were buried in the noise floor.


> On the TX side these can be
> reduced by RF filter/duplexer. RX LPF will filter them out on the RX side.

Yes, I know how to get rid of them. Unfortunately designing a front
end that can programmably filter those for the whole range of the LMS
(like in a broadband SDR), it's not easy :p

So I was wondering if you had any data on the typical / worst case
values for those so I can know exactly how good a pre-filtering I need
to have on the input.


Cheers,

    Sylvain



From joel at jointventure.com  Fri Feb 22 14:28:22 2013
From: joel at jointventure.com (joel yabut)
Date: Fri, 22 Feb 2013 22:28:22 +0800
Subject: Fwd: Re: UmTRX beta samples shipping address check
In-Reply-To: <A2CE449F-4773-488C-911B-0308F835B187@gmail.com>
References: <CABmJbFUYy039KGE0iEdoq93B=07qq=LO74p60usdA18NwTesxA@mail.gmail.com>
	<56296323-4C77-40F3-86F1-9EB047A1FD8D@gmail.com>
	<CABmJbFWv7bz=5PXBCeYtC+sdxOFUn5+CMTQuKzv98R0ALh5rFQ@mail.gmail.com>
	<CABYi+4i-w5ZL=hHazaMDqVOoWGfz9POjUQeMJ1gEt6+vcw60sg@mail.gmail.com>
	<CABYi+4gqi-cH5b+mr_s=2_3woteoR7YUJKhuSdnkXw-bV8BKtg@mail.gmail.com>
	<CABmJbFXRxaPDxw=tOF3LyXgMP0iUpM2DWDHXdrZ_hzt-wjnKjA@mail.gmail.com>
	<CABYi+4gd=AGC5oEMreawGpgY7o0xjRt1Hvq67rkm2heUEjxD9w@mail.gmail.com>
	<CABmJbFV6Gg1HoF12uWaX=VLVKUa5hOuximWsV7PnVxo3WTaZWQ@mail.gmail.com>
	<CABYi+4gdj=ZCu0wJiwTFVBrEJv0Z9N95Uxw9QCCDox9=7-xbcg@mail.gmail.com>
	<CABmJbFURNVePkBFB5yhEROqdifinYDhsWrm4-HeJg10Uaipoug@mail.gmail.com>
	<A2CE449F-4773-488C-911B-0308F835B187@gmail.com>
Message-ID: <CABYi+4jMkiXtjgjMawNyUv6Vvj3MmNt=_ARhzuLY3JU6Tt8tZg@mail.gmail.com>

---------- Forwarded message ----------
From: "Joel Yabut" <joel.yabut at gmail.com>
Date: Feb 18, 2013 9:25 AM
Subject: Re: UmTRX beta samples shipping address check
To: "Alexander Chemeris" <alexander.chemeris at gmail.com>
Cc:

May i know the following specs
1. What is the tx and rx isolation of umtrx?
2. What is the power output in dbm of your umtrx?
3. How is the lna on the rx input and is an external lna and bpf
recommended?
4. What is the main advantage of umtrx compared to usrp by ettus?

Thanks!
Joel

Sent from my Ipad

On Feb 15, 2013, at 7:23 PM, Alexander Chemeris <
alexander.chemeris at gmail.com> wrote:

> Ok, I'll ask to ship to this address.
>
> On Fri, Feb 15, 2013 at 11:41 AM, joel yabut <joel.yabut at gmail.com> wrote:
>> ok. thanks..
>> if you can set this value and follow shipping instruction below to avoid
any
>> transhipment.
>> cCan you just ship it straight to Manila, Philippines
>>
>> just declare it as PCB parts
>> Joint Venture Sound light entertainment concepts, Inc.
>> 2 scout rallos, quezon City
>> MM, Philippines
>> Attn: Louie Domingsil
>> tel. 3742969
>>
>>
>>
>> On Thu, Feb 14, 2013 at 11:17 PM, Alexander Chemeris
>> <alexander.chemeris at gmail.com> wrote:
>>>
>>> Thanks. I think we'll set this value for this package as well if you
>>> don't object.
>>>
>>> On Fri, Feb 15, 2013 at 11:05 AM, joel yabut <joel.yabut at gmail.com>
wrote:
>>>> ok. it seems fine.
>>>> in the future, a 150 usd for the future.
>>>>
>>>>
>>>> On Thu, Feb 14, 2013 at 10:59 PM, Alexander Chemeris
>>>> <alexander.chemeris at gmail.com> wrote:
>>>>>
>>>>> Here is a packing list:
>>>>>
>>>>> * UmTRXv2, flashed and ready to use.
>>>>> * Power supply, 12V/30W -
>>>>> http://www.phihong.com/assets/pdf/PSAC30U.pdf
>>>>> Note, that it comes without a 220V power cord. Make sure to prepare
>>>>> one before you receive the UmTRX to be able to power it on
>>>>> immediately.
>>>>> * Converter cable from a Molex power connector to a standard round DC
>>>>> connector.
>>>>> * U.FL-to-SMA-F pigtail cables
>>>>> * Two small antennas - one for Tx and one for Rx.
>>>>>
>>>>> Note, that for safe operation you'll need either a heatsink (external
>>>>> HDD enclosures work well) or a fan. Otherwise you could overheat your
>>>>> UmTRX during a long operation.
>>>>>
>>>>> On Fri, Feb 15, 2013 at 10:45 AM, joel yabut <joel.yabut at gmail.com>
>>>>> wrote:
>>>>>> What is included with the order?
>>>>>> Does it include the cables for antenna and psu?
>>>>>>
>>>>>>
>>>>>> On Thu, Feb 14, 2013 at 10:42 PM, joel yabut <joel.yabut at gmail.com>
>>>>>> wrote:
>>>>>>>
>>>>>>> thanks!!!
>>>>>>> in the future, can you declare lower value for shipping purposes?
>>>>>>>
>>>>>>>
>>>>>>> On Thu, Feb 14, 2013 at 10:26 PM, Alexander Chemeris
>>>>>>> <alexander.chemeris at gmail.com> wrote:
>>>>>>>>
>>>>>>>> Ok, corrected.
>>>>>>>>
>>>>>>>> On Fri, Feb 15, 2013 at 8:01 AM, Joel Yabut <joel.yabut at gmail.com>
>>>>>>>> wrote:
>>>>>>>>> Just correct to Amazing speed..
>>>>>>>>> Thank you
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Sent from my Ipad
>>>>>>>>>
>>>>>>>>> On Feb 15, 2013, at 4:18 AM, Alexander Chemeris
>>>>>>>>> <alexander.chemeris at gmail.com> wrote:
>>>>>>>>>
>>>>>>>>>> Hi Joel,
>>>>>>>>>>
>>>>>>>>>> We're ready to ship UmTRX beta samples to our first customers
>>>>>>>>>> and
>>>>>>>>>> we
>>>>>>>>>> want to check that your shipping address is correct:
>>>>>>>>>>
>>>>>>>>>> Jose Q. Yabut
>>>>>>>>>> AMAZIN SPEED INTL LTD
>>>>>>>>>> K1 4FL NORTH TWR KWAI SHUN IND CTR
>>>>>>>>>> 51-63 CONTAINER PORT ROAD
>>>>>>>>>> Hong Kong
>>>>>>>>>> 85293354413
>>>>>>>>>>
>>>>>>>>>> We  apologize for the delay with the production. We've made all
>>>>>>>>>> we
>>>>>>>>>> could to solve the issue quickly and ensure the quality of the
>>>>>>>>>> further
>>>>>>>>>> production at the same time. We appreciate your patience and
>>>>>>>>>> looking
>>>>>>>>>> forward to your feedback when you receive your UmTRX!
>>>>>>>>>>
>>>>>>>>>> PS T-shirts will be sent as a separate package from our
>>>>>>>>>> headquarter
>>>>>>>>>> in
>>>>>>>>>> Moscow, so expect two tracking numbers.
>>>>>>>>>>
>>>>>>>>>> --
>>>>>>>>>> Regards,
>>>>>>>>>> Alexander Chemeris.
>>>>>>>>>> CEO, Fairwaves LLC / ??? ???????
>>>>>>>>>> http://fairwaves.ru
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> --
>>>>>>>> Regards,
>>>>>>>> Alexander Chemeris.
>>>>>>>> CEO, Fairwaves LLC / ??? ???????
>>>>>>>> http://fairwaves.ru
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> --
>>>>>>> Mother Ignacia Avenue corner Scout Rallos St.
>>>>>>> Quezon City, Metro Manila, Philippines
>>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>> --
>>>>>> Mother Ignacia Avenue corner Scout Rallos St.
>>>>>> Quezon City, Metro Manila, Philippines
>>>>>>
>>>>>
>>>>>
>>>>>
>>>>> --
>>>>> Regards,
>>>>> Alexander Chemeris.
>>>>> CEO, Fairwaves LLC / ??? ???????
>>>>> http://fairwaves.ru
>>>>
>>>>
>>>>
>>>>
>>>> --
>>>> Mother Ignacia Avenue corner Scout Rallos St.
>>>> Quezon City, Metro Manila, Philippines
>>>>
>>>
>>>
>>>
>>> --
>>> Regards,
>>> Alexander Chemeris.
>>> CEO, Fairwaves LLC / ??? ???????
>>> http://fairwaves.ru
>>
>>
>>
>>
>> --
>> Mother Ignacia Avenue corner Scout Rallos St.
>> Quezon City, Metro Manila, Philippines
>>
>
>
>
> --
> Regards,
> Alexander Chemeris.
> CEO, Fairwaves LLC / ??? ???????
> http://fairwaves.ru
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From joel at jointventure.com  Fri Feb 22 14:31:28 2013
From: joel at jointventure.com (joel yabut)
Date: Fri, 22 Feb 2013 22:31:28 +0800
Subject: Dual channel
Message-ID: <CABYi+4i97UD5wdF0tJVrc=tk1rf1DEjLDUPrZsxdk8dpgFQp9Q@mail.gmail.com>

What does dual channel actually mean? Can you use 2 different frequencies
at the same time  like 900 and 1800 or is it same band  but different arfcn?
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From stephane at shimaore.net  Sat Feb 23 16:02:57 2013
From: stephane at shimaore.net (stephane at shimaore.net)
Date: Sat, 23 Feb 2013 17:02:57 +0100
Subject: transceiver won't start; fpga build error
Message-ID: <20130223160257.GB4895@shimaore.net>

Hi,

I went to pick up my UmTRX this morning. \o/

It appears to start fine, but I'm hitting a couple issues trying to
connect OpenBTS to it:

transceiver won't start
=======================

I get the following errors when starting OpenBTS or the transceiver:

  /home/stephane/Public/src/umtrx/openbts-p2.8/apps# ./transceiver
  linux; GNU C++ version 4.7.2; Boost_104900; UHD_003.004.000-a52936a

  ALERT 139976877029152 UHDDevice.cpp:434:open: No UHD devices found with address ''
  ALERT 139976877029152 runTransceiver.cpp:94:main: Transceiver exiting...

  /home/stephane/Public/src/umtrx/openbts-p2.8/apps# ./transceiver
  linux; GNU C++ version 4.7.2; Boost_104900; UHD_003.004.000-a52936a

  ALERT 139853627492128 UHDDevice.cpp:345:set_rates: Failed to set master clock rate
  ALERT 139853627492128 UHDDevice.cpp:346:set_rates: Actual clock rate 1.3e+07
  ALERT 139853627492128 runTransceiver.cpp:94:main: Transceiver exiting...

(This is with latest UHD from git://github.com/chemeris/UHD-Fairwaves.git
and latest openBTS from git://github.com/ttsou/openbts-p2.8.git )

I assume the first one ('No UHD devices...') is a transcient problem.

For the second issue I don't know whether this might be because the
firmware on the unit I received might not be the latest, or because I
really need to first upload the FPGA image (although I assumed ZPU wouldn't
start in that case); here's the console output in any case:

  USRP N210 UDP bootloader
  FPGA compatibility number: 8
  Firmware compatibility number: 11
  Production image = 0
  Checking for valid production FPGA image...
  No valid production FPGA image found.

  Valid production firmware found. Loading...
  Finished loading. Starting image.

  TxRx-UHD-ZPU
  FPGA compatibility number: 8
  Firmware compatibility number: 11
  LMS1 chip version = 0x22
  LMS2 chip version = 0x22
  00:1F:11:02:19:01
  192.168.10.2

FPGA compilation error
======================

Assuming this is because of a missing/out-of-date FPGA image, I tried to
compile the latest (git) FPGA firmware:

  cd UHD-Fairwaves/fpga/usrp2/top/N2x0/ ; make clean ; make UmTRXv2

but got the following error:

  ERROR:HDLCompiler:1654 - "/home/stephane/Public/src/umtrx/UHD-Fairwaves/fpga/usrp2/top/N2x0/u2plus_core.v" Line 734: Instantiating <rx_frontend_sw> from unknown module <frontend_sw>

A quick `git blame` points to some changes in January but I wouldn't
know where to start fixing this (or maybe this is an issue with my
environemnt and not the code). In case this is the environemnt, I'm using
ISE 14.4 on Linux/amd64.

S.



From alexander.chemeris at gmail.com  Sat Feb 23 16:46:52 2013
From: alexander.chemeris at gmail.com (Alexander Chemeris)
Date: Sat, 23 Feb 2013 20:46:52 +0400
Subject: transceiver won't start; fpga build error
In-Reply-To: <20130223160257.GB4895@shimaore.net>
References: <20130223160257.GB4895@shimaore.net>
Message-ID: <CABmJbFU6VDvpPG5ADqVSEeqaYDw3uXf=eTWdqsvu3KY4tqUx4g@mail.gmail.com>

Hi Stephane,

Glad to see first users starting to play with UmTRX. :)

Please use OpenBTS from our repository and use branch "umtrx" instead
of "master". UmTRX support is not merged into master yet.
git://github.com/fairwaves/openbts-2.8 umtrx

"Failed to set master clock rate" error is thrown because it thinks
you're using USRP N and tries to set frequency accordingly.

FPGA image should be the latest. You could download it here as well:
http://people.osmocom.org/ipse/umtrx-v2/fpga_bitsream/2013-02-03-394f48b7/

We'll look into the FPGA compilation issue - may be Andrew forgot to
check in that file. Thank you for reporting this.

On Sat, Feb 23, 2013 at 8:02 PM,  <stephane at shimaore.net> wrote:
> Hi,
>
> I went to pick up my UmTRX this morning. \o/
>
> It appears to start fine, but I'm hitting a couple issues trying to
> connect OpenBTS to it:
>
> transceiver won't start
> =======================
>
> I get the following errors when starting OpenBTS or the transceiver:
>
>   /home/stephane/Public/src/umtrx/openbts-p2.8/apps# ./transceiver
>   linux; GNU C++ version 4.7.2; Boost_104900; UHD_003.004.000-a52936a
>
>   ALERT 139976877029152 UHDDevice.cpp:434:open: No UHD devices found with address ''
>   ALERT 139976877029152 runTransceiver.cpp:94:main: Transceiver exiting...
>
>   /home/stephane/Public/src/umtrx/openbts-p2.8/apps# ./transceiver
>   linux; GNU C++ version 4.7.2; Boost_104900; UHD_003.004.000-a52936a
>
>   ALERT 139853627492128 UHDDevice.cpp:345:set_rates: Failed to set master clock rate
>   ALERT 139853627492128 UHDDevice.cpp:346:set_rates: Actual clock rate 1.3e+07
>   ALERT 139853627492128 runTransceiver.cpp:94:main: Transceiver exiting...
>
> (This is with latest UHD from git://github.com/chemeris/UHD-Fairwaves.git
> and latest openBTS from git://github.com/ttsou/openbts-p2.8.git )
>
> I assume the first one ('No UHD devices...') is a transcient problem.
>
> For the second issue I don't know whether this might be because the
> firmware on the unit I received might not be the latest, or because I
> really need to first upload the FPGA image (although I assumed ZPU wouldn't
> start in that case); here's the console output in any case:
>
>   USRP N210 UDP bootloader
>   FPGA compatibility number: 8
>   Firmware compatibility number: 11
>   Production image = 0
>   Checking for valid production FPGA image...
>   No valid production FPGA image found.
>
>   Valid production firmware found. Loading...
>   Finished loading. Starting image.
>
>   TxRx-UHD-ZPU
>   FPGA compatibility number: 8
>   Firmware compatibility number: 11
>   LMS1 chip version = 0x22
>   LMS2 chip version = 0x22
>   00:1F:11:02:19:01
>   192.168.10.2
>
> FPGA compilation error
> ======================
>
> Assuming this is because of a missing/out-of-date FPGA image, I tried to
> compile the latest (git) FPGA firmware:
>
>   cd UHD-Fairwaves/fpga/usrp2/top/N2x0/ ; make clean ; make UmTRXv2
>
> but got the following error:
>
>   ERROR:HDLCompiler:1654 - "/home/stephane/Public/src/umtrx/UHD-Fairwaves/fpga/usrp2/top/N2x0/u2plus_core.v" Line 734: Instantiating <rx_frontend_sw> from unknown module <frontend_sw>
>
> A quick `git blame` points to some changes in January but I wouldn't
> know where to start fixing this (or maybe this is an issue with my
> environemnt and not the code). In case this is the environemnt, I'm using
> ISE 14.4 on Linux/amd64.
>
> S.
>



--
Regards,
Alexander Chemeris.
CEO, Fairwaves LLC / ??? ???????
http://fairwaves.ru



From alexander.chemeris at gmail.com  Sat Feb 23 16:48:47 2013
From: alexander.chemeris at gmail.com (Alexander Chemeris)
Date: Sat, 23 Feb 2013 20:48:47 +0400
Subject: transceiver won't start; fpga build error
In-Reply-To: <CABmJbFU6VDvpPG5ADqVSEeqaYDw3uXf=eTWdqsvu3KY4tqUx4g@mail.gmail.com>
References: <20130223160257.GB4895@shimaore.net>
	<CABmJbFU6VDvpPG5ADqVSEeqaYDw3uXf=eTWdqsvu3KY4tqUx4g@mail.gmail.com>
Message-ID: <CABmJbFWr2BQzKRtEWuyboOL4ptEU3_bUH2z+2NSk4z=pi4hmNw@mail.gmail.com>

PS We're flying to the Mobile World Congress tonight and may be slow
to respond. I apologize for this - we'll catch up when we get back
after March 4.

On Sat, Feb 23, 2013 at 8:46 PM, Alexander Chemeris
<alexander.chemeris at gmail.com> wrote:
> Hi Stephane,
>
> Glad to see first users starting to play with UmTRX. :)
>
> Please use OpenBTS from our repository and use branch "umtrx" instead
> of "master". UmTRX support is not merged into master yet.
> git://github.com/fairwaves/openbts-2.8 umtrx
>
> "Failed to set master clock rate" error is thrown because it thinks
> you're using USRP N and tries to set frequency accordingly.
>
> FPGA image should be the latest. You could download it here as well:
> http://people.osmocom.org/ipse/umtrx-v2/fpga_bitsream/2013-02-03-394f48b7/
>
> We'll look into the FPGA compilation issue - may be Andrew forgot to
> check in that file. Thank you for reporting this.
>
> On Sat, Feb 23, 2013 at 8:02 PM,  <stephane at shimaore.net> wrote:
>> Hi,
>>
>> I went to pick up my UmTRX this morning. \o/
>>
>> It appears to start fine, but I'm hitting a couple issues trying to
>> connect OpenBTS to it:
>>
>> transceiver won't start
>> =======================
>>
>> I get the following errors when starting OpenBTS or the transceiver:
>>
>>   /home/stephane/Public/src/umtrx/openbts-p2.8/apps# ./transceiver
>>   linux; GNU C++ version 4.7.2; Boost_104900; UHD_003.004.000-a52936a
>>
>>   ALERT 139976877029152 UHDDevice.cpp:434:open: No UHD devices found with address ''
>>   ALERT 139976877029152 runTransceiver.cpp:94:main: Transceiver exiting...
>>
>>   /home/stephane/Public/src/umtrx/openbts-p2.8/apps# ./transceiver
>>   linux; GNU C++ version 4.7.2; Boost_104900; UHD_003.004.000-a52936a
>>
>>   ALERT 139853627492128 UHDDevice.cpp:345:set_rates: Failed to set master clock rate
>>   ALERT 139853627492128 UHDDevice.cpp:346:set_rates: Actual clock rate 1.3e+07
>>   ALERT 139853627492128 runTransceiver.cpp:94:main: Transceiver exiting...
>>
>> (This is with latest UHD from git://github.com/chemeris/UHD-Fairwaves.git
>> and latest openBTS from git://github.com/ttsou/openbts-p2.8.git )
>>
>> I assume the first one ('No UHD devices...') is a transcient problem.
>>
>> For the second issue I don't know whether this might be because the
>> firmware on the unit I received might not be the latest, or because I
>> really need to first upload the FPGA image (although I assumed ZPU wouldn't
>> start in that case); here's the console output in any case:
>>
>>   USRP N210 UDP bootloader
>>   FPGA compatibility number: 8
>>   Firmware compatibility number: 11
>>   Production image = 0
>>   Checking for valid production FPGA image...
>>   No valid production FPGA image found.
>>
>>   Valid production firmware found. Loading...
>>   Finished loading. Starting image.
>>
>>   TxRx-UHD-ZPU
>>   FPGA compatibility number: 8
>>   Firmware compatibility number: 11
>>   LMS1 chip version = 0x22
>>   LMS2 chip version = 0x22
>>   00:1F:11:02:19:01
>>   192.168.10.2
>>
>> FPGA compilation error
>> ======================
>>
>> Assuming this is because of a missing/out-of-date FPGA image, I tried to
>> compile the latest (git) FPGA firmware:
>>
>>   cd UHD-Fairwaves/fpga/usrp2/top/N2x0/ ; make clean ; make UmTRXv2
>>
>> but got the following error:
>>
>>   ERROR:HDLCompiler:1654 - "/home/stephane/Public/src/umtrx/UHD-Fairwaves/fpga/usrp2/top/N2x0/u2plus_core.v" Line 734: Instantiating <rx_frontend_sw> from unknown module <frontend_sw>
>>
>> A quick `git blame` points to some changes in January but I wouldn't
>> know where to start fixing this (or maybe this is an issue with my
>> environemnt and not the code). In case this is the environemnt, I'm using
>> ISE 14.4 on Linux/amd64.
>>
>> S.
>>
>
>
>
> --
> Regards,
> Alexander Chemeris.
> CEO, Fairwaves LLC / ??? ???????
> http://fairwaves.ru



--
Regards,
Alexander Chemeris.
CEO, Fairwaves LLC / ??? ???????
http://fairwaves.ru



From stephane at shimaore.net  Sat Feb 23 17:14:00 2013
From: stephane at shimaore.net (stephane at shimaore.net)
Date: Sat, 23 Feb 2013 18:14:00 +0100
Subject: transceiver won't start; fpga build error
In-Reply-To: <CABmJbFU6VDvpPG5ADqVSEeqaYDw3uXf=eTWdqsvu3KY4tqUx4g@mail.gmail.com>
References: <20130223160257.GB4895@shimaore.net>
	<CABmJbFU6VDvpPG5ADqVSEeqaYDw3uXf=eTWdqsvu3KY4tqUx4g@mail.gmail.com>
Message-ID: <20130223171359.GA6824@shimaore.net>

Hi Alexander,

> We'll look into the FPGA compilation issue - may be Andrew forgot to
> check in that file. Thank you for reporting this.

FWIW the issue appears with d7628bcd0b562f8a3be02eb52acc2f5e0a541c33 ;
commit 9d67877209fa5f92d0858ad041be198bd0262045 doesn't have the issue.

I'll go ahead and recompile openBTS using your version. Thank you!
S.



From alexander.chemeris at gmail.com  Sat Feb 23 17:23:14 2013
From: alexander.chemeris at gmail.com (Alexander Chemeris)
Date: Sat, 23 Feb 2013 21:23:14 +0400
Subject: transceiver won't start; fpga build error
In-Reply-To: <20130223171359.GA6824@shimaore.net>
References: <20130223160257.GB4895@shimaore.net>
	<CABmJbFU6VDvpPG5ADqVSEeqaYDw3uXf=eTWdqsvu3KY4tqUx4g@mail.gmail.com>
	<20130223171359.GA6824@shimaore.net>
Message-ID: <CABmJbFWBJZ319tQYhrL9WEgTWSVpLygxs9fL01NWLFBQ3kfrOQ@mail.gmail.com>

Hi Stephane,

On Sat, Feb 23, 2013 at 9:14 PM,  <stephane at shimaore.net> wrote:
>> We'll look into the FPGA compilation issue - may be Andrew forgot to
>> check in that file. Thank you for reporting this.
>
> FWIW the issue appears with d7628bcd0b562f8a3be02eb52acc2f5e0a541c33 ;
> commit 9d67877209fa5f92d0858ad041be198bd0262045 doesn't have the issue.

Btw, do you have experience with Xilinx FPGAs programming? We have an
issue with ICAP which prevents us to use a "production" FPGA bitstream
- right now we use only "safe" bistream. It's not a critical issue and
thus we haven't looked into it deeply, but it would be very convenient
to have it working. If you feel like you could do that, I'll explain
it in more details.

-- 
Regards,
Alexander Chemeris.
CEO, Fairwaves LLC / ??? ???????
http://fairwaves.ru



From stephane at shimaore.net  Sat Feb 23 20:22:58 2013
From: stephane at shimaore.net (stephane at shimaore.net)
Date: Sat, 23 Feb 2013 21:22:58 +0100
Subject: transceiver won't start; fpga build error
In-Reply-To: <20130223171359.GA6824@shimaore.net>
References: <20130223160257.GB4895@shimaore.net>
	<CABmJbFU6VDvpPG5ADqVSEeqaYDw3uXf=eTWdqsvu3KY4tqUx4g@mail.gmail.com>
	<20130223171359.GA6824@shimaore.net>
Message-ID: <20130223202258.GB6824@shimaore.net>

> I'll go ahead and recompile openBTS using your version. Thank you!

That worked out rather smoothly. I can see the '00101' GSM network on my
phone and OpenBTS attempts to SIP REGISTER when I choose it on the
phone.

Here are my notes, I'll be posting further updates there as well:
  http://blog.shimaore.net/2013/02/umtrx.html
Hope this helps.

Next steps for me are to setup FreeSwitch (and maybe OpenSIPS) so that I
can start testing calls.


Question: I used RX1 and TX1 on the board to connect the antennae, but
`transceiver` says "using transmit antenna RX1" and "using receive antenna
TX2", does that mean I should use RX1/TX2 instead, or is this a
configuration parameter I should modify in OpenBTS.db?

S.


PS: Congratulations to everyone involved in making this so painless!
Eight hours (lunch included) from unpacking to being able to see the MNC
show up on a phone is _very_ nice.



From plddesigner at gmail.com  Sat Feb 23 20:55:19 2013
From: plddesigner at gmail.com (Andrew Karpenkov)
Date: Sun, 24 Feb 2013 00:55:19 +0400
Subject: transceiver won't start; fpga build error
In-Reply-To: <20130223160257.GB4895@shimaore.net>
References: <20130223160257.GB4895@shimaore.net>
Message-ID: <CACy-4bnSiOwMkKQXNcN2KX7=tDvXZrW1qrT-aDDkSmhYmrGw-w@mail.gmail.com>

Hi Stephane,

Thank you very much for your comment. It's my fault. I forgot to add a line
to the fpga/usrp2/sdr_lib/Makefile.srcs. I fixed this error. To
successfully compile the FPGA project, you will need to update your local
repository from github.

2013/2/23 <stephane at shimaore.net>

> FPGA compilation error
> ======================
>
> Assuming this is because of a missing/out-of-date FPGA image, I tried to
> compile the latest (git) FPGA firmware:
>
>   cd UHD-Fairwaves/fpga/usrp2/top/N2x0/ ; make clean ; make UmTRXv2
>
> but got the following error:
>
>   ERROR:HDLCompiler:1654 -
> "/home/stephane/Public/src/umtrx/UHD-Fairwaves/fpga/usrp2/top/N2x0/u2plus_core.v"
> Line 734: Instantiating <rx_frontend_sw> from unknown module <frontend_sw>
>
> A quick `git blame` points to some changes in January but I wouldn't
> know where to start fixing this (or maybe this is an issue with my
> environemnt and not the code). In case this is the environemnt, I'm using
> ISE 14.4 on Linux/amd64
>



Regards,
Andrew Karpenkov
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From craig.reading1 at gmail.com  Sun Feb 24 20:47:09 2013
From: craig.reading1 at gmail.com (Craig Reading)
Date: Sun, 24 Feb 2013 20:47:09 +0000
Subject: Debug port configuration
Message-ID: <CACSK8pZ+p1iFaL7uLqGQAS+gYZO6rf-q+e_0Nii+sj-wqv8wTA@mail.gmail.com>

Hi,

Can anybody confirm the USB debug serial port settings. I have downloaded
the FTDI drivers and can connect. However I do not get any meaningful
output.

Based on the source code I assume the settings are:

?         baudrate = 115200

?         stop bits = 1

?         parity = none

?         flow-control = off


Regards
Craig
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From andreysviyaz at gmail.com  Sun Feb 24 22:58:31 2013
From: andreysviyaz at gmail.com (Andrey Sviyazov)
Date: Mon, 25 Feb 2013 02:58:31 +0400
Subject: Debug port configuration
In-Reply-To: <CACSK8pZ+p1iFaL7uLqGQAS+gYZO6rf-q+e_0Nii+sj-wqv8wTA@mail.gmail.com>
References: <CACSK8pZ+p1iFaL7uLqGQAS+gYZO6rf-q+e_0Nii+sj-wqv8wTA@mail.gmail.com>
Message-ID: <CAE9AREzMukbVmc6yBJ4QfTO6fv7vy0oZBc8yaCYL=_hS_TTCsw@mail.gmail.com>

Hi Craig.

Virtual com port should work at 230400.

Best regards,
Andrey Sviyazov.
(Sent from my mobile client)
25.02.2013 2:35 ???????????? "Craig Reading" <craig.reading1 at gmail.com>
???????:

> Hi,
>
> Can anybody confirm the USB debug serial port settings. I have downloaded
> the FTDI drivers and can connect. However I do not get any meaningful
> output.
>
> Based on the source code I assume the settings are:
>
> ?         baudrate = 115200
>
> ?         stop bits = 1
>
> ?         parity = none
>
> ?         flow-control = off
>
>
> Regards
> Craig
>
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