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Thomas Tsou thomastsou at gmail.comHi Andrey, Sorry I did answer sooner. The E4406A arrived so I have been setting that up. I have UmTRX hooked up right now, which I will be testing very shortly. Thomas On Fri, Jul 20, 2012 at 1:14 PM, Andrey Sviyazov <andrey.sviyazov at fairwaves.ru> wrote: > Hi Thomas. > > I couldn't wait your reply and start to implement 10kHz BW of PLL. > You can find here two pictures with results. > First of all I found that PLL tuning algorithm doesn't work properly at low > PLL BW. > VCOCAP register (r0x19) should contain higher value at least for +3 units > (to make CAP lower), otherwise freq's above 950MHz never locked. > Note, that you should read and change register 0x19 after autotuning. > Second, you can see some noise difference for the 925MHz because of used > DIV=8 of the VCO, instead of DIV=4 for 942 and 960MHz. > Third, you can see PLL noice dependance with the charge pump current > (r0x16). > > On the other two pictures you can find which components have to be changed. > Thomas, please make one more measure of LO noise and jitter at PLL BW=10kHz > by your instrument. > We need to know, is it real to reach modulation accuracy of 1.5 degrees RMS > or impossible, just because of LMS PLL have bigger jitter. > > Best regards, > Andrey Sviyazov. > > > > 2012/7/19 Andrey Sviyazov <andrey.sviyazov at fairwaves.ru> >> >> Thomas. >> I've calculate few PIF filters for PLL by the ADIsimPLL and found that RMS >> phase jitter in case of 5kHz and 50kHz only 0.33 and 0.46 degrees. >> It is very small difference, so are you sure that I should implement 10kHz >> bandwidth filter as in USRP? >> Actually it is absolutly not an problem for me to implement it, but I have >> to be sure. >> I've calculated it for 10kHz bandwidth, noise plot will be around >> 75-80dBc/Hz @ 10kHz and 105-110 dBc/Hz @ 100kHz offset. >> >> Best regards, >> Andrey Sviyazov. >> >> >> >> 2012/7/19 Andrey Sviyazov <andrey.sviyazov at fairwaves.ru> >>> >>> Alexander. >>> I think that few pulses of LMS hardware reset (LMS_NRST-1 and LMS_NRST-2 >>> pins) will be much easily than all registers checking. >>> BTW, are there reset pulses after power up or not? >>> >>> Best regards, >>> Andrey Sviyazov. >>> >>> >>> >>> 2012/7/19 Alexander Chemeris <alexander.chemeris at gmail.com> >>>> >>>> Guys, please keep track of all LMS configuration values which are not >>>> set to default during power on and we'll add them to our manual >>>> initialization script. >>>> >>>> On Thu, Jul 19, 2012 at 6:56 PM, Andrey Sviyazov >>>> <andrey.sviyazov at fairwaves.ru> wrote: >>>> > Sergey. >>>> > I'll play around GPS power and RTC supply, thank you for your help. >>>> > >>>> > Thomas. >>>> > About r0x16 please be sure that sometimes it isn't set to default >>>> > value >>>> > after power up (I saw it few times). >>>> > Also I think that possible those bad "power on reset" gave us unstable >>>> > result of LMS autocalibration. >>>> > >>>> > Best regards, >>>> > Andrey Sviyazov. >>>> > >>>> > >>>> > >>>> > 2012/7/19 sergey kostanbaev <sergey.kostanbaev at gmail.com> >>>> >> >>>> >> Which gives ~1.5khz cut-off, that's strange >>>> >> >>>> >> Also I'd check GPS VDD and AVDD nosies >>>> >> >>>> >> >>>> >> On Thu, Jul 19, 2012 at 6:41 PM, Andrey Sviyazov >>>> >> <andrey.sviyazov at fairwaves.ru> wrote: >>>> >>> >>>> >>> 1kOhm resistor and 0.1uF capacitor already exist between DAC and VC >>>> >>> input. >>>> >>> Of course I'll increase capacitance or resistance to be sure about >>>> >>> VC >>>> >>> pin. >>>> >>> >>>> >>> Best regards, >>>> >>> Andrey Sviyazov. >>>> >>> >>>> >>> >>>> >>> >>>> >>> 2012/7/19 sergey kostanbaev <sergey.kostanbaev at gmail.com> >>>> >>>> >>>> >>>> No :) But it may cause. >>>> >>>> >>>> >>>> I'd check all the line from FPGA to DAC to VCTXCO because VC pin is >>>> >>>> really sensible to any noise. >>>> >>>> - caused by power supply of DAC. >>>> >>>> - output noise of DAC. >>>> >>>> - algorithm of changing values >>>> >>>> >>>> >>>> At first I'd inspect VC pin at VCTXCO and try to filter it with >>>> >>>> cut-off >>>> >>>> frequency 1-0.1 Hz >>>> >>>> >>>> >>>> >>>> >>>> On Thu, Jul 19, 2012 at 6:29 PM, Andrey Sviyazov >>>> >>>> <andrey.sviyazov at fairwaves.ru> wrote: >>>> >>>>> >>>> >>>>> Sergey. >>>> >>>>> Is it really so frequently (32k/s updates at 1pps reference)? >>>> >>>>> >>>> >>>>> Best regards, >>>> >>>>> Andrey Sviyazov. >>>> >>>>> >>>> >>>>> >>>> >>>>> >>>> >>>>> 2012/7/19 sergey kostanbaev <sergey.kostanbaev at gmail.com> >>>> >>>>>> >>>> >>>>>> >>>> >>>>>> >>>> >>>>>> On Thu, Jul 19, 2012 at 6:10 PM, Andrey Sviyazov >>>> >>>>>> <andrey.sviyazov at fairwaves.ru> wrote: >>>> >>>>>>> >>>> >>>>>>> Hi all. >>>> >>>>>>> >>>> >>>>>>> I've found spurs on the LO noise plot at ~33kHz and ~66kHz >>>> >>>>>>> offset >>>> >>>>>>> when GPS antenna used and position locked. >>>> >>>>>>> This spurs begin grow up when GPS just near to lock position and >>>> >>>>>>> after locking spurs stopped to grow as you can see at picture. >>>> >>>>>>> If thereafter GPS disconnected then noise coming back to normal >>>> >>>>>>> plot. >>>> >>>>>>> I think that it is result of 32768Hz clock in the GPS module >>>> >>>>>>> EB-230, >>>> >>>>>>> but can't understant how it can impact to 26MHz clock or VCO. >>>> >>>>>> >>>> >>>>>> >>>> >>>>>> As another idea it can be caused by continues GPS correction lead >>>> >>>>>> to >>>> >>>>>> DAC changes to the VCTXCO. >>>> >>>>>> >>>> >>>>>>> >>>> >>>>>>> Please tell me something who know. >>>> >>>>>>> >>>> >>>>>>> Thomas. >>>> >>>>>>> Was GPS antenna connected when noise measured like on the >>>> >>>>>>> picture >>>> >>>>>>> which you sent us (also attached here)? >>>> >>>>>>> I would to know because of anomal peak near to 30kHz offset too. >>>> >>>>>>> >>>> >>>>>>> Best regards, >>>> >>>>>>> Andrey Sviyazov. >>>> >>>>>>> >>>> >>>>>>> >>>> >>>>>>> >>>> >>>>>>> 2012/7/19 Andrey Sviyazov <andrey.sviyazov at fairwaves.ru> >>>> >>>>>>>> >>>> >>>>>>>> Sorry, that was meant to be sent to the mailing list :) >>>> >>>>>>>> >>>> >>>>>>>> Best regards, >>>> >>>>>>>> Andrey Sviyazov. >>>> >>>>>>>> >>>> >>>>>>>> ---------- Forwarded message ---------- >>>> >>>>>>>> From: Andrey Sviyazov <andreysviyaz at gmail.com> >>>> >>>>>>>> Date: 2012/7/18 >>>> >>>>>>>> Subject: LMS TxLO noise >>>> >>>>>>>> >>>> >>>>>>>> Hi Thomas. >>>> >>>>>>>> >>>> >>>>>>>> Here forwarded my last e-mail with noise plots when I stopped >>>> >>>>>>>> work >>>> >>>>>>>> around it at first time, please see below. >>>> >>>>>>>> >>>> >>>>>>>> Please try to play around Tx PLL charge pump current (register >>>> >>>>>>>> 0x16) >>>> >>>>>>>> for better RMS phase stability. >>>> >>>>>>>> I think we should reach 1 degree or below. >>>> >>>>>>>> >>>> >>>>>>>> Alexander gave me the second UmTRX board and after checking and >>>> >>>>>>>> fixing all known hardware issues I've got roughly the same LO >>>> >>>>>>>> noise plot. >>>> >>>>>>>> Possible Robin had no time to fixing all of our issues, so >>>> >>>>>>>> check >>>> >>>>>>>> them all please. >>>> >>>>>>>> And also check please what type of TCXO installed on your >>>> >>>>>>>> board. >>>> >>>>>>>> >>>> >>>>>>>> Best regards, >>>> >>>>>>>> Andrey Sviyazov. >>>> >>>>>>>> >>>> >>>>>>>> ---------- Forwarded message ---------- >>>> >>>>>>>> From: Andrey Sviyazov <andreysviyaz at gmail.com> >>>> >>>>>>>> Date: 2012/4/13 >>>> >>>>>>>> Subject: Re: LMS TxLO noise >>>> >>>>>>>> >>>> >>>>>>>> Hi all. >>>> >>>>>>>> >>>> >>>>>>>> There is progress with LMS PLL :) >>>> >>>>>>>> Pictures are attached here. >>>> >>>>>>>> t was discovered that 80 kHz spurs come from Ethernet, or >>>> >>>>>>>> rather >>>> >>>>>>>> from the ET1011. >>>> >>>>>>>> I unknowingly put the choke between transistor of 1V regulator >>>> >>>>>>>> and >>>> >>>>>>>> analog power 1V. >>>> >>>>>>>> As a result, the regulator has become unstable and oscillated >>>> >>>>>>>> 80 kHz >>>> >>>>>>>> with amplitude of 200 mV, which climbed into the LMS PLL. >>>> >>>>>>>> To correct this problem L46 should be replaced by jumper on all >>>> >>>>>>>> alfa >>>> >>>>>>>> version PCB's. >>>> >>>>>>>> >>>> >>>>>>>> Also I just played with current in the PLL loop, shown on the >>>> >>>>>>>> picture for clarity. >>>> >>>>>>>> Proved to be the optimal current 1,9 mA (you should write 0x93 >>>> >>>>>>>> in >>>> >>>>>>>> the register of 0x16). >>>> >>>>>>>> But, I think, for the RxPLL will be better use of the current >>>> >>>>>>>> 2.4 >>>> >>>>>>>> mA, because the nearest noises more important for Rx (you >>>> >>>>>>>> should write 0x98 >>>> >>>>>>>> in the register 0x26). >>>> >>>>>>>> >>>> >>>>>>>> Best regards, >>>> >>>>>>>> Andrey Sviyazov. >>>> >>>>>>>> >>>> >>>>>>>> >>>> >>>>>>> >>>> >>>>>> >>>> >>>>> >>>> >>>> >>>> >>> >>>> >> >>>> > >>>> >>>> >>>> >>>> -- >>>> Regards, >>>> Alexander Chemeris. >>>> CEO, Fairwaves LLC / ООО УмРадио >>>> http://fairwaves.ru >>> >>> >> >