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Christian Vogel vogelchr at vogel.cxHi Harald,
I cannot say anything competent about the IDT82v2081, but I have a few
general remarks.
Is it on purpose that you can open the Tx-Line by removing R4/R5 (0 Ohm),
or is it planned to maybe add a RC-Filter there? (why?)
> The design has the following features:
> * the 4x3 and 2x3 jumpers like on the HFC-E1 eval board to set TE mode
> and NT mode as well as two possible configurations of the pairs
As you are trying to conserve space, have you thought about using
2x2 jumpers for TE/NT selection, such as:
jumpers jumpers
Rx+---- o o ----RJ4 Rx+---- o -- o ----RJ4
| |
RJ13--- o o ----Tx+ RJ13--- o -- o ----Tx+ ?
It might be useful to have pads for the RTIP/RRING TTIP/TRING signals + GND
accessible for debugging (maybe as unpopulated jumpers), those signals should
be cleaner than what's accessible on the jumpers/RJ45.
On Ethernet cards, the unused pairs are normally terminated in something ~100 Ohm,
and the central tap of the transformers and the unused pairs connected to system
ground via a few 100pF capacitor, I don't have any E1/T1 equipment here
to compare, but maybe one could consider doing this?
> * jumper to decide whether TCLK should be sourced from MCLK or if it is
> provided externally by the transmitter
> * 10pin header for SPI control interface
> * 10pin header for TDM interface
Is there an established standard for these interfaces, or a "most popular
eval board" in use? On the TDM-Interface TDN/TDP and RDN/RDP don't run
on adjacent pairs if a press-on flat-cable connector is used, if this
is a established standard, please ignore this comment, otherwise I'd propose
\RST 1 2 \LOS <- control signals
GND 3 4 TCLK <- gnd+tx clock
TDP 5 6 TDN <- transmit pair
GND 7 8 RCLK <- tnd+rx clock
RDP 9 10 RDN <- receive pair
When testing the chip on a bench, maybe with only a oscilloscope connected
to the TDM-pins, it might be useful if \RST is pulled high on the board.
For the SPI interface my suggestion would be to use something compatible
to the most prevalent JTAG pinout (SDO=TDO, \CS=TMS, SCLK=TCK), that way
one can easily talk to the 82V2081 from the PC using a common (dumb) USB
JTAG cable and custom software, and please include Vcc on SPI.
I don't know about the intended cable lengths, but maybe a few series resistors
for dampening the signal wouldn't hurt.
> * 5x5cm size for cheapest pcb prototyping ;)
For the board, can you please move all external connectors to the side
opposing the RJ45?
All but one diode have the same orientation, that's unnecessarily confusing
during population of the board. To conserve space, a quad diode array (first
google hit: BAV99DW has one pair with common cathode, one pair with common
anode) could be useful.
Include a LED for loss-of-signal and power?
Include pads for a 3.3V linear low-dropout regulator,
normally bridged by a 0 Ohm resistor?
The datasheets lists all I/O to be 5V compatible, and
someone might want to use the transceiver with a 5V-only
FPGA/Microcontroller board? Or someone might want to power
the FPGA/Microcontroller via the LDO on the transceiver board?
Hmm... ok, this has become more than I intended, but maybe
the comments are useful? ;-)
Happy Christmas,
Chris