Change in osmocom-bb[master]: trx_toolkit/clck_gen.py: fix TDMA clock counter wrapping

[fixeria]

fixeria has submitted this change. ( https://gerrit.osmocom.org/c/osmocom-bb/+/19225 )

Change subject: trx_toolkit/clck_gen.py: fix TDMA clock counter wrapping
......................................................................

trx_toolkit/clck_gen.py: fix TDMA clock counter wrapping

Change-Id: I157447c7610402f6d62d2b74c9f04fcaa0bc1724
---
M src/target/trx_toolkit/clck_gen.py
1 file changed, 2 insertions(+), 6 deletions(-)

Approvals:
  Jenkins Builder: Verified
  laforge: Looks good to me, approved



diff --git a/src/target/trx_toolkit/clck_gen.py b/src/target/trx_toolkit/clck_gen.py
index 92be8b0..9f39643 100755
--- a/src/target/trx_toolkit/clck_gen.py
+++ b/src/target/trx_toolkit/clck_gen.py
@@ -91,10 +91,6 @@
 			self.send_clck_ind()
 
 	def send_clck_ind(self):
-		# Keep clock cycle
-		if self.clck_src % GSM_HYPERFRAME >= 0:
-			self.clck_src %= GSM_HYPERFRAME
-
 		# We don't need to send so often
 		if self.clck_src % self.ind_period == 0:
 			# Create UDP payload
@@ -107,8 +103,8 @@
 			# Debug print
 			log.debug(payload.rstrip("\0"))
 
-		# Increase frame count
-		self.clck_src += 1
+		# Increase frame count (modular arithmetic)
+		self.clck_src = (self.clck_src + 1) % GSM_HYPERFRAME
 
 # Just a wrapper for independent usage
 class Application(ApplicationBase):

-- 
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Gerrit-Project: osmocom-bb
Gerrit-Branch: master
Gerrit-Change-Id: I157447c7610402f6d62d2b74c9f04fcaa0bc1724
Gerrit-Change-Number: 19225
Gerrit-PatchSet: 2
Gerrit-Owner: fixeria <vyanitskiy at sysmocom.de>
Gerrit-Reviewer: Jenkins Builder
Gerrit-Reviewer: fixeria <vyanitskiy at sysmocom.de>
Gerrit-Reviewer: laforge <laforge at osmocom.org>
Gerrit-Reviewer: pespin <pespin at sysmocom.de>
Gerrit-MessageType: merged
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