Change in simtrace2[master]: check RST/VCC/CLK line at every step of the activation

[laforge]

laforge has submitted this change. ( https://gerrit.osmocom.org/c/simtrace2/+/16078 )

Change subject: check RST/VCC/CLK line at every step of the activation
......................................................................

check RST/VCC/CLK line at every step of the activation

ISO-7816 specifies a card activation sequence: VCC on, CLK active, then RST
release.
we now check for the end state at every state of the activation in case the
reader does not strictly follows the sequence.

change has been tested on OWHW slot 1.

Change-Id: Ie55505ab3a70cbd64281af40af53d5e120313228
---
M firmware/libcommon/source/card_emu.c
1 file changed, 7 insertions(+), 0 deletions(-)

Approvals:
  Jenkins Builder: Verified
  laforge: Looks good to me, approved



diff --git a/firmware/libcommon/source/card_emu.c b/firmware/libcommon/source/card_emu.c
index 087867f..5298ffc 100644
--- a/firmware/libcommon/source/card_emu.c
+++ b/firmware/libcommon/source/card_emu.c
@@ -380,6 +380,13 @@
 	case ISO_S_WAIT_RST:
 		/* disable Rx and Tx of UART */
 		card_emu_uart_enable(ch->uart_chan, 0);
+		/* check end activation state (only necessary if the reader to not respect the activation sequence) */
+		if (ch->vcc_active && ch->clocked && !ch->in_reset) {
+			/* enable the TC/ETU counter once reset has been released */
+			tc_etu_enable(ch->tc_chan);
+			/* prepare to send the ATR */
+			card_set_state(ch, ISO_S_WAIT_ATR);
+		}
 		break;
 	case ISO_S_WAIT_ATR:
 		/* Reset to initial Fi / Di ratio */

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Gerrit-Project: simtrace2
Gerrit-Branch: master
Gerrit-Change-Id: Ie55505ab3a70cbd64281af40af53d5e120313228
Gerrit-Change-Number: 16078
Gerrit-PatchSet: 1
Gerrit-Owner: tsaitgaist <kredon at sysmocom.de>
Gerrit-Reviewer: Jenkins Builder
Gerrit-Reviewer: laforge <laforge at osmocom.org>
Gerrit-MessageType: merged
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