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Kévin Redon gerrit-no-reply at lists.osmocom.orgKévin Redon has uploaded this change for review. ( https://gerrit.osmocom.org/12808 Change subject: switch from dev board to prototype ...................................................................... switch from dev board to prototype the SAM E54 Xplained Pro development board uses a SAM E54P20N micro-controller. the sysmocom sysmoOCTSIM prototype uses a SAM E54N19A micro-controller. the system LED and UART debug GPIO are different, else the code is the same. the Atmel START definitions have been updated accordingly. Change-Id: Ifd15f6759c51b42a8d11b09f9f495d7e7a5b6afc --- M sysmoOCTSIM/AtmelStart.env_conf M sysmoOCTSIM/AtmelStart.gpdsc M sysmoOCTSIM/atmel_start_config.atstart M sysmoOCTSIM/atmel_start_pins.h M sysmoOCTSIM/config/hpl_gclk_config.h M sysmoOCTSIM/config/hpl_port_config.h M sysmoOCTSIM/config/hpl_sercom_config.h M sysmoOCTSIM/config/hpl_usb_config.h M sysmoOCTSIM/config/peripheral_clk_config.h M sysmoOCTSIM/driver_init.c M sysmoOCTSIM/gcc/Makefile A sysmoOCTSIM/gcc/gcc/same54n19a_flash.ld A sysmoOCTSIM/gcc/gcc/same54n19a_sram.ld M sysmoOCTSIM/hpl/port/hpl_gpio_base.h M sysmoOCTSIM/hpl/sercom/hpl_sercom.c M sysmoOCTSIM/hpl/usb/hpl_usb.c 16 files changed, 544 insertions(+), 355 deletions(-) git pull ssh://gerrit.osmocom.org:29418/osmo-ccid-firmware refs/changes/08/12808/1 diff --git a/sysmoOCTSIM/AtmelStart.env_conf b/sysmoOCTSIM/AtmelStart.env_conf index dfb4608..cad5b65 100644 --- a/sysmoOCTSIM/AtmelStart.env_conf +++ b/sysmoOCTSIM/AtmelStart.env_conf @@ -1,6 +1,6 @@ <environment> <configurations/> <device-packs> - <device-pack device="ATSAME54P20A" name="SAME54_DFP" vendor="Atmel" version="1.0.87"/> + <device-pack device="ATSAME54N19A" name="SAME54_DFP" vendor="Atmel" version="1.0.87"/> </device-packs> </environment> diff --git a/sysmoOCTSIM/AtmelStart.gpdsc b/sysmoOCTSIM/AtmelStart.gpdsc index ebb4d1e..51851db 100644 --- a/sysmoOCTSIM/AtmelStart.gpdsc +++ b/sysmoOCTSIM/AtmelStart.gpdsc @@ -12,7 +12,7 @@ <generators> <generator id="AtmelStart"> <description>Atmel Start</description> - <select Dname="ATSAME54P20A" Dvendor="Atmel:3"/> + <select Dname="ATSAME54N19A" Dvendor="Atmel:3"/> <command>http://start.atmel.com/</command> <files> <file category="generator" name="atmel_start_config.atstart"/> @@ -27,13 +27,13 @@ <require Cclass="Device" Cgroup="Startup" Cversion="1.0.0"/> </condition> <condition id="ARMCC, GCC, IAR"> - <require Dname="ATSAME54P20A"/> + <require Dname="ATSAME54N19A"/> <accept Tcompiler="ARMCC"/> <accept Tcompiler="GCC"/> <accept Tcompiler="IAR"/> </condition> <condition id="GCC"> - <require Dname="ATSAME54P20A"/> + <require Dname="ATSAME54N19A"/> <accept Tcompiler="GCC"/> </condition> </conditions> @@ -160,8 +160,7 @@ <file category="header" condition="ARMCC, GCC, IAR" name="usb/usb_includes.h"/> <file category="source" condition="ARMCC, GCC, IAR" name="usb/usb_protocol.c"/> <file category="header" condition="ARMCC, GCC, IAR" name="usb/usb_protocol.h"/> - <file category="source" condition="ARMCC, GCC, IAR" name="usb_cdc_echo_main.c"/> - <file category="doc" condition="ARMCC, GCC, IAR" name="documentation/usb_cdc_echo.rst"/> + <file category="source" condition="ARMCC, GCC, IAR" name="main.c"/> <file category="source" condition="ARMCC, GCC, IAR" name="driver_init.c"/> <file category="header" condition="ARMCC, GCC, IAR" name="driver_init.h"/> <file category="header" condition="ARMCC, GCC, IAR" name="atmel_start_pins.h"/> diff --git a/sysmoOCTSIM/atmel_start_config.atstart b/sysmoOCTSIM/atmel_start_config.atstart index 7492bf6..09c0b2d 100644 --- a/sysmoOCTSIM/atmel_start_config.atstart +++ b/sysmoOCTSIM/atmel_start_config.atstart @@ -9,12 +9,10 @@ format: '2' frontend: 1.4.1810 board: - identifier: SAME54XplainedPro - device: SAME54P20A-AU + identifier: CustomBoard + device: SAME54N19A-AF details: null -application: - definition: 'Atmel:Application_Examples:0.0.1::Application:USB_CDC_Echo:' - configuration: {} +application: null middlewares: USB_CHAPTER_9: user_label: USB_CHAPTER_9 @@ -31,8 +29,8 @@ api: USB:Protocol:CDC dependencies: USB Chapter 9: USB_CHAPTER_9 - USB_DEVICE_CORE: - user_label: USB_DEVICE_CORE + USB_DEVICE_STACK_CORE_INSTANCE: + user_label: USB_DEVICE_STACK_CORE_INSTANCE configuration: usbd_hs_sp: false definition: Atmel:USB:0.0.1::USB_Device_Core @@ -82,12 +80,12 @@ functionality: USB_Device_CDC_ACM api: USB:Device:CDC_ACM dependencies: - USB Device Stack Core Instance: USB_DEVICE_CORE + USB Device Stack Core Instance: USB_DEVICE_STACK_CORE_INSTANCE USB Class CDC: USB_CLASS_CDC drivers: CMCC: user_label: CMCC - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::CMCC::driver_config_definition::CMCC::HAL:HPL:CMCC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::CMCC::driver_config_definition::CMCC::HAL:HPL:CMCC functionality: System api: HAL:HPL:CMCC configuration: @@ -103,7 +101,7 @@ domain_group: null DMAC: user_label: DMAC - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC functionality: System api: HAL:HPL:DMAC configuration: @@ -639,7 +637,7 @@ domain_group: null GCLK: user_label: GCLK - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK functionality: System api: HAL:HPL:GCLK configuration: @@ -720,7 +718,7 @@ gclk_gen_0_oscillator: Digital Phase Locked Loop (DPLL0) gclk_gen_10_div: 1 gclk_gen_10_div_sel: false - gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC0) + gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) gclk_gen_11_div: 6 gclk_gen_11_div_sel: false gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) @@ -735,29 +733,29 @@ gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K) gclk_gen_4_div: 1 gclk_gen_4_div_sel: false - gclk_gen_4_oscillator: External Crystal Oscillator 8-48MHz (XOSC0) + gclk_gen_4_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) gclk_gen_5_div: 1 gclk_gen_5_div_sel: false - gclk_gen_5_oscillator: External Crystal Oscillator 8-48MHz (XOSC0) + gclk_gen_5_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) gclk_gen_6_div: 1 gclk_gen_6_div_sel: false - gclk_gen_6_oscillator: External Crystal Oscillator 8-48MHz (XOSC0) + gclk_gen_6_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) gclk_gen_7_div: 1 gclk_gen_7_div_sel: false - gclk_gen_7_oscillator: External Crystal Oscillator 8-48MHz (XOSC0) + gclk_gen_7_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) gclk_gen_8_div: 1 gclk_gen_8_div_sel: false - gclk_gen_8_oscillator: External Crystal Oscillator 8-48MHz (XOSC0) + gclk_gen_8_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) gclk_gen_9_div: 1 gclk_gen_9_div_sel: false - gclk_gen_9_oscillator: External Crystal Oscillator 8-48MHz (XOSC0) + gclk_gen_9_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) optional_signals: [] variant: null clocks: domain_group: null MCLK: user_label: MCLK - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK functionality: System api: HAL:HPL:MCLK configuration: @@ -778,7 +776,7 @@ configuration: {} OSC32KCTRL: user_label: OSC32KCTRL - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL functionality: System api: HAL:HPL:OSC32KCTRL configuration: @@ -806,7 +804,7 @@ domain_group: null OSCCTRL: user_label: OSCCTRL - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL functionality: System api: HAL:HPL:OSCCTRL configuration: @@ -843,7 +841,7 @@ fdpll0_arch_runstdby: false fdpll0_arch_wuf: false fdpll0_clock_dcofilter: 0 - fdpll0_clock_div: 6 + fdpll0_clock_div: 2 fdpll0_ldr: 59 fdpll0_ldrfrac: 0 fdpll0_ref_clock: Generic clock generator 11 @@ -857,7 +855,7 @@ fdpll1_arch_runstdby: false fdpll1_arch_wuf: false fdpll1_clock_dcofilter: 0 - fdpll1_clock_div: 6 + fdpll1_clock_div: 2 fdpll1_ldr: 49 fdpll1_ldrfrac: 0 fdpll1_ref_clock: Generic clock generator 11 @@ -887,7 +885,7 @@ domain_group: null PORT: user_label: PORT - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::PORT::driver_config_definition::PORT::HAL:HPL:PORT + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::PORT::driver_config_definition::PORT::HAL:HPL:PORT functionality: System api: HAL:HPL:PORT configuration: @@ -931,25 +929,13 @@ portc_input_event_enable_1: false portc_input_event_enable_2: false portc_input_event_enable_3: false - portd_event_action_0: Output register of pin will be set to level of event - portd_event_action_1: Output register of pin will be set to level of event - portd_event_action_2: Output register of pin will be set to level of event - portd_event_action_3: Output register of pin will be set to level of event - portd_event_pin_identifier_0: 0 - portd_event_pin_identifier_1: 0 - portd_event_pin_identifier_2: 0 - portd_event_pin_identifier_3: 0 - portd_input_event_enable_0: false - portd_input_event_enable_1: false - portd_input_event_enable_2: false - portd_input_event_enable_3: false optional_signals: [] variant: null clocks: domain_group: null RAMECC: user_label: RAMECC - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC functionality: System api: HAL:HPL:RAMECC configuration: {} @@ -959,7 +945,7 @@ domain_group: null UART_debug: user_label: UART_debug - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM2::driver_config_definition::UART::HAL:Driver:USART.Async + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM7::driver_config_definition::UART::HAL:Driver:USART.Async functionality: USART api: HAL:Driver:USART_Async configuration: @@ -986,11 +972,11 @@ variant: specification: TXPO=0, RXPO=1, CMODE=0 required_signals: - - name: SERCOM2/PAD/0 - pad: PB25 + - name: SERCOM7/PAD/0 + pad: PB30 label: TX - - name: SERCOM2/PAD/1 - pad: PB24 + - name: SERCOM7/PAD/1 + pad: PB31 label: RX clocks: domain_group: @@ -1004,7 +990,7 @@ slow_gclk_selection: Generic clock generator 3 USB_DEVICE_INSTANCE: user_label: USB_DEVICE_INSTANCE - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::USB::driver_config_definition::USB.Device::HAL:Driver:USB.Device + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::USB::driver_config_definition::USB.Device::HAL:Driver:USB.Device functionality: USB api: HAL:Driver:USB_Device configuration: @@ -1025,7 +1011,7 @@ usb_ep7_I_CACHE: No cache usbd_arch_max_ep_n: 2 (EP 0x82 or 0x02) usbd_arch_speed: Full speed - usbd_num_ep_sp: Max possible (by "Max Endpoint Number" config) + usbd_num_ep_sp: 4 (EP0 + 3 endpoints) optional_signals: [] variant: specification: default @@ -1044,35 +1030,34 @@ configuration: usb_gclk_selection: Generic clock generator 1 pads: + USBUP_D_N: + name: PA24 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA24 + mode: Advanced + user_label: USBUP_D_N + configuration: null + USBUP_D_P: + name: PA25 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA25 + mode: Advanced + user_label: USBUP_D_P + configuration: null LED_system: - name: PC18 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PC18 + name: PC26 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PC26 mode: Digital output user_label: LED_system - configuration: - pad_initial_level: High - PA24: - name: PA24 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA24 - mode: Advanced - user_label: PA24 - configuration: {} - PA25: - name: PA25 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA25 - mode: Advanced - user_label: PA25 - configuration: {} - PB24: - name: PB24 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB24 - mode: Peripheral IO - user_label: PB24 configuration: null - PB25: - name: PB25 - definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB25 + UART_TX: + name: PB30 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PB30 mode: Peripheral IO - user_label: PB25 + user_label: UART_TX + configuration: null + UART_RX: + name: PB31 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PB31 + mode: Peripheral IO + user_label: UART_RX configuration: null toolchain_options: [] diff --git a/sysmoOCTSIM/atmel_start_pins.h b/sysmoOCTSIM/atmel_start_pins.h index 7c774ed..884a562 100644 --- a/sysmoOCTSIM/atmel_start_pins.h +++ b/sysmoOCTSIM/atmel_start_pins.h @@ -27,10 +27,10 @@ #define GPIO_PIN_FUNCTION_M 12 #define GPIO_PIN_FUNCTION_N 13 -#define PA24 GPIO(GPIO_PORTA, 24) -#define PA25 GPIO(GPIO_PORTA, 25) -#define PB24 GPIO(GPIO_PORTB, 24) -#define PB25 GPIO(GPIO_PORTB, 25) -#define LED_system GPIO(GPIO_PORTC, 18) +#define USBUP_D_N GPIO(GPIO_PORTA, 24) +#define USBUP_D_P GPIO(GPIO_PORTA, 25) +#define UART_TX GPIO(GPIO_PORTB, 30) +#define UART_RX GPIO(GPIO_PORTB, 31) +#define LED_system GPIO(GPIO_PORTC, 26) #endif // ATMEL_START_PINS_H_INCLUDED diff --git a/sysmoOCTSIM/config/hpl_gclk_config.h b/sysmoOCTSIM/config/hpl_gclk_config.h index 12c1539..d16af6f 100644 --- a/sysmoOCTSIM/config/hpl_gclk_config.h +++ b/sysmoOCTSIM/config/hpl_gclk_config.h @@ -328,7 +328,7 @@ // <i> This defines the clock source for generic clock generator 4 // <id> gclk_gen_4_oscillator #ifndef CONF_GCLK_GEN_4_SOURCE -#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC0 +#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC1 #endif // <q> Run in Standby @@ -404,7 +404,7 @@ // <i> This defines the clock source for generic clock generator 5 // <id> gclk_gen_5_oscillator #ifndef CONF_GCLK_GEN_5_SOURCE -#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC0 +#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC1 #endif // <q> Run in Standby @@ -480,7 +480,7 @@ // <i> This defines the clock source for generic clock generator 6 // <id> gclk_gen_6_oscillator #ifndef CONF_GCLK_GEN_6_SOURCE -#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC0 +#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC1 #endif // <q> Run in Standby @@ -556,7 +556,7 @@ // <i> This defines the clock source for generic clock generator 7 // <id> gclk_gen_7_oscillator #ifndef CONF_GCLK_GEN_7_SOURCE -#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC0 +#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1 #endif // <q> Run in Standby @@ -632,7 +632,7 @@ // <i> This defines the clock source for generic clock generator 8 // <id> gclk_gen_8_oscillator #ifndef CONF_GCLK_GEN_8_SOURCE -#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC0 +#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1 #endif // <q> Run in Standby @@ -708,7 +708,7 @@ // <i> This defines the clock source for generic clock generator 9 // <id> gclk_gen_9_oscillator #ifndef CONF_GCLK_GEN_9_SOURCE -#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC0 +#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1 #endif // <q> Run in Standby @@ -784,7 +784,7 @@ // <i> This defines the clock source for generic clock generator 10 // <id> gclk_gen_10_oscillator #ifndef CONF_GCLK_GEN_10_SOURCE -#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC0 +#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1 #endif // <q> Run in Standby diff --git a/sysmoOCTSIM/config/hpl_port_config.h b/sysmoOCTSIM/config/hpl_port_config.h index b5315f0..a7bd379 100644 --- a/sysmoOCTSIM/config/hpl_port_config.h +++ b/sysmoOCTSIM/config/hpl_port_config.h @@ -94,34 +94,6 @@ #endif // </h> -// <h> PORT Input Event 0 configuration on PORT D - -// <q> PORTD Input Event 0 Enable -// <i> The event action will be triggered on any incoming event if PORT D Input Event 0 configuration is enabled -// <id> portd_input_event_enable_0 -#ifndef CONF_PORTD_EVCTRL_PORTEI_0 -#define CONF_PORTD_EVCTRL_PORTEI_0 0x0 -#endif - -// <o> PORTD Event 0 Pin Identifier <0x00-0x1F> -// <i> These bits define the I/O pin from port D on which the event action will be performed -// <id> portd_event_pin_identifier_0 -#ifndef CONF_PORTD_EVCTRL_PID_0 -#define CONF_PORTD_EVCTRL_PID_0 0x0 -#endif - -// <o> PORTD Event 0 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// <i> These bits define the event action the PORT D will perform on event input 0 -// <id> portd_event_action_0 -#ifndef CONF_PORTD_EVCTRL_EVACT_0 -#define CONF_PORTD_EVCTRL_EVACT_0 0 -#endif - -// </h> // </e> @@ -215,34 +187,6 @@ #endif // </h> -// <h> PORT Input Event 1 configuration on PORT D - -// <q> PORTD Input Event 1 Enable -// <i> The event action will be triggered on any incoming event if PORT D Input Event 1 configuration is enabled -// <id> portd_input_event_enable_1 -#ifndef CONF_PORTD_EVCTRL_PORTEI_1 -#define CONF_PORTD_EVCTRL_PORTEI_1 0x0 -#endif - -// <o> PORTD Event 1 Pin Identifier <0x00-0x1F> -// <i> These bits define the I/O pin from port D on which the event action will be performed -// <id> portd_event_pin_identifier_1 -#ifndef CONF_PORTD_EVCTRL_PID_1 -#define CONF_PORTD_EVCTRL_PID_1 0x0 -#endif - -// <o> PORTD Event 1 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// <i> These bits define the event action the PORT D will perform on event input 1 -// <id> portd_event_action_1 -#ifndef CONF_PORTD_EVCTRL_EVACT_1 -#define CONF_PORTD_EVCTRL_EVACT_1 0 -#endif - -// </h> // </e> @@ -336,34 +280,6 @@ #endif // </h> -// <h> PORT Input Event 2 configuration on PORT D - -// <q> PORTD Input Event 2 Enable -// <i> The event action will be triggered on any incoming event if PORT D Input Event 2 configuration is enabled -// <id> portd_input_event_enable_2 -#ifndef CONF_PORTD_EVCTRL_PORTEI_2 -#define CONF_PORTD_EVCTRL_PORTEI_2 0x0 -#endif - -// <o> PORTD Event 2 Pin Identifier <0x00-0x1F> -// <i> These bits define the I/O pin from port D on which the event action will be performed -// <id> portd_event_pin_identifier_2 -#ifndef CONF_PORTD_EVCTRL_PID_2 -#define CONF_PORTD_EVCTRL_PID_2 0x0 -#endif - -// <o> PORTD Event 2 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// <i> These bits define the event action the PORT D will perform on event input 2 -// <id> portd_event_action_2 -#ifndef CONF_PORTD_EVCTRL_EVACT_2 -#define CONF_PORTD_EVCTRL_EVACT_2 0 -#endif - -// </h> // </e> @@ -457,34 +373,6 @@ #endif // </h> -// <h> PORT Input Event 3 configuration on PORT D - -// <q> PORTD Input Event 3 Enable -// <i> The event action will be triggered on any incoming event if PORT D Input Event 3 configuration is enabled -// <id> portd_input_event_enable_3 -#ifndef CONF_PORTD_EVCTRL_PORTEI_3 -#define CONF_PORTD_EVCTRL_PORTEI_3 0x0 -#endif - -// <o> PORTD Event 3 Pin Identifier <0x00-0x1F> -// <i> These bits define the I/O pin from port D on which the event action will be performed -// <id> portd_event_pin_identifier_3 -#ifndef CONF_PORTD_EVCTRL_PID_3 -#define CONF_PORTD_EVCTRL_PID_3 0x0 -#endif - -// <o> PORTD Event 3 Action -// <0=> Output register of pin will be set to level of event -// <1=> Set output register of pin on event -// <2=> Clear output register of pin on event -// <3=> Toggle output register of pin on event -// <i> These bits define the event action the PORT D will perform on event input 3 -// <id> portd_event_action_3 -#ifndef CONF_PORTD_EVCTRL_EVACT_3 -#define CONF_PORTD_EVCTRL_EVACT_3 0 -#endif - -// </h> // </e> @@ -509,13 +397,6 @@ | PORT_EVCTRL_EVACT2(CONF_PORTC_EVCTRL_EVACT_2) | CONF_PORTC_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ | PORT_EVCTRL_PID2(CONF_PORTC_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTC_EVCTRL_EVACT_3) \ | CONF_PORTC_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTC_EVCTRL_PID_3)) -#define CONF_PORTD_EVCTRL \ - (0 | PORT_EVCTRL_EVACT0(CONF_PORTD_EVCTRL_EVACT_0) | CONF_PORTD_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ - | PORT_EVCTRL_PID0(CONF_PORTD_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTD_EVCTRL_EVACT_1) \ - | CONF_PORTD_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTD_EVCTRL_PID_1) \ - | PORT_EVCTRL_EVACT2(CONF_PORTD_EVCTRL_EVACT_2) | CONF_PORTD_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ - | PORT_EVCTRL_PID2(CONF_PORTD_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTD_EVCTRL_EVACT_3) \ - | CONF_PORTD_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTD_EVCTRL_PID_3)) // <<< end of configuration section >>> diff --git a/sysmoOCTSIM/config/hpl_sercom_config.h b/sysmoOCTSIM/config/hpl_sercom_config.h index e154ce2..2a8c023 100644 --- a/sysmoOCTSIM/config/hpl_sercom_config.h +++ b/sysmoOCTSIM/config/hpl_sercom_config.h @@ -6,8 +6,8 @@ #include <peripheral_clk_config.h> -#ifndef CONF_SERCOM_2_USART_ENABLE -#define CONF_SERCOM_2_USART_ENABLE 1 +#ifndef CONF_SERCOM_7_USART_ENABLE +#define CONF_SERCOM_7_USART_ENABLE 1 #endif // <h> Basic Configuration @@ -15,15 +15,15 @@ // <q> Receive buffer enable // <i> Enable input buffer in SERCOM module // <id> usart_rx_enable -#ifndef CONF_SERCOM_2_USART_RXEN -#define CONF_SERCOM_2_USART_RXEN 1 +#ifndef CONF_SERCOM_7_USART_RXEN +#define CONF_SERCOM_7_USART_RXEN 1 #endif // <q> Transmitt buffer enable // <i> Enable output buffer in SERCOM module // <id> usart_tx_enable -#ifndef CONF_SERCOM_2_USART_TXEN -#define CONF_SERCOM_2_USART_TXEN 1 +#ifndef CONF_SERCOM_7_USART_TXEN +#define CONF_SERCOM_7_USART_TXEN 1 #endif // <o> Frame parity @@ -32,8 +32,8 @@ // <0x2=>Odd parity // <i> Parity bit mode for USART frame // <id> usart_parity -#ifndef CONF_SERCOM_2_USART_PARITY -#define CONF_SERCOM_2_USART_PARITY 0x0 +#ifndef CONF_SERCOM_7_USART_PARITY +#define CONF_SERCOM_7_USART_PARITY 0x0 #endif // <o> Character Size @@ -44,8 +44,8 @@ // <0x7=>7 bits // <i> Data character size in USART frame // <id> usart_character_size -#ifndef CONF_SERCOM_2_USART_CHSIZE -#define CONF_SERCOM_2_USART_CHSIZE 0x0 +#ifndef CONF_SERCOM_7_USART_CHSIZE +#define CONF_SERCOM_7_USART_CHSIZE 0x0 #endif // <o> Stop Bit @@ -53,51 +53,51 @@ // <1=>Two stop bits // <i> Number of stop bits in USART frame // <id> usart_stop_bit -#ifndef CONF_SERCOM_2_USART_SBMODE -#define CONF_SERCOM_2_USART_SBMODE 0 +#ifndef CONF_SERCOM_7_USART_SBMODE +#define CONF_SERCOM_7_USART_SBMODE 0 #endif // <o> Baud rate <1-6250000> // <i> USART baud rate setting // <id> usart_baud_rate -#ifndef CONF_SERCOM_2_USART_BAUD -#define CONF_SERCOM_2_USART_BAUD 921600 +#ifndef CONF_SERCOM_7_USART_BAUD +#define CONF_SERCOM_7_USART_BAUD 921600 #endif // </h> // <e> Advanced configuration // <id> usart_advanced -#ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG -#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0 +#ifndef CONF_SERCOM_7_USART_ADVANCED_CONFIG +#define CONF_SERCOM_7_USART_ADVANCED_CONFIG 0 #endif // <q> Run in stand-by // <i> Keep the module running in standby sleep mode // <id> usart_arch_runstdby -#ifndef CONF_SERCOM_2_USART_RUNSTDBY -#define CONF_SERCOM_2_USART_RUNSTDBY 0 +#ifndef CONF_SERCOM_7_USART_RUNSTDBY +#define CONF_SERCOM_7_USART_RUNSTDBY 0 #endif // <q> Immediate Buffer Overflow Notification // <i> Controls when the BUFOVF status bit is asserted // <id> usart_arch_ibon -#ifndef CONF_SERCOM_2_USART_IBON -#define CONF_SERCOM_2_USART_IBON 0 +#ifndef CONF_SERCOM_7_USART_IBON +#define CONF_SERCOM_7_USART_IBON 0 #endif // <q> Start of Frame Detection Enable // <i> Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) // <id> usart_arch_sfde -#ifndef CONF_SERCOM_2_USART_SFDE -#define CONF_SERCOM_2_USART_SFDE 0 +#ifndef CONF_SERCOM_7_USART_SFDE +#define CONF_SERCOM_7_USART_SFDE 0 #endif // <q> Collision Detection Enable // <i> Collision detection enable // <id> usart_arch_cloden -#ifndef CONF_SERCOM_2_USART_CLODEN -#define CONF_SERCOM_2_USART_CLODEN 0 +#ifndef CONF_SERCOM_7_USART_CLODEN +#define CONF_SERCOM_7_USART_CLODEN 0 #endif // <o> Operating Mode @@ -105,8 +105,8 @@ // <0x1=>USART with internal clock // <i> Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. // <id> usart_arch_clock_mode -#ifndef CONF_SERCOM_2_USART_MODE -#define CONF_SERCOM_2_USART_MODE 0x1 +#ifndef CONF_SERCOM_7_USART_MODE +#define CONF_SERCOM_7_USART_MODE 0x1 #endif // <o> Sample Rate @@ -117,8 +117,8 @@ // <0x4=>3x arithmetic // <i> How many over-sampling bits used when sampling data state // <id> usart_arch_sampr -#ifndef CONF_SERCOM_2_USART_SAMPR -#define CONF_SERCOM_2_USART_SAMPR 0x0 +#ifndef CONF_SERCOM_7_USART_SAMPR +#define CONF_SERCOM_7_USART_SAMPR 0x0 #endif // <o> Sample Adjustment @@ -128,15 +128,15 @@ // <0x3=>13-14-15 (6-7-8 8-bit over-sampling) // <i> Adjust which samples to use for data sampling in asynchronous mode // <id> usart_arch_sampa -#ifndef CONF_SERCOM_2_USART_SAMPA -#define CONF_SERCOM_2_USART_SAMPA 0x0 +#ifndef CONF_SERCOM_7_USART_SAMPA +#define CONF_SERCOM_7_USART_SAMPA 0x0 #endif // <o> Fractional Part <0-7> // <i> Fractional part of the baud rate if baud rate generator is in fractional mode // <id> usart_arch_fractional -#ifndef CONF_SERCOM_2_USART_FRACTIONAL -#define CONF_SERCOM_2_USART_FRACTIONAL 0x0 +#ifndef CONF_SERCOM_7_USART_FRACTIONAL +#define CONF_SERCOM_7_USART_FRACTIONAL 0x0 #endif // <o> Data Order @@ -144,19 +144,19 @@ // <1=>LSB is transmitted first // <i> Data order of the data bits in the frame // <id> usart_arch_dord -#ifndef CONF_SERCOM_2_USART_DORD -#define CONF_SERCOM_2_USART_DORD 1 +#ifndef CONF_SERCOM_7_USART_DORD +#define CONF_SERCOM_7_USART_DORD 1 #endif // Does not do anything in UART mode -#define CONF_SERCOM_2_USART_CPOL 0 +#define CONF_SERCOM_7_USART_CPOL 0 // <o> Encoding Format // <0=>No encoding // <1=>IrDA encoded // <id> usart_arch_enc -#ifndef CONF_SERCOM_2_USART_ENC -#define CONF_SERCOM_2_USART_ENC 0 +#ifndef CONF_SERCOM_7_USART_ENC +#define CONF_SERCOM_7_USART_ENC 0 #endif // <o> LIN Slave Enable @@ -165,8 +165,8 @@ // <0=>Disable // <1=>Enable // <id> usart_arch_lin_slave_enable -#ifndef CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE -#define CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE 0 +#ifndef CONF_SERCOM_7_USART_LIN_SLAVE_ENABLE +#define CONF_SERCOM_7_USART_LIN_SLAVE_ENABLE 0 #endif // <o> Debug Stop Mode @@ -174,102 +174,102 @@ // <0=>Keep running // <1=>Halt // <id> usart_arch_dbgstop -#ifndef CONF_SERCOM_2_USART_DEBUG_STOP_MODE -#define CONF_SERCOM_2_USART_DEBUG_STOP_MODE 0 +#ifndef CONF_SERCOM_7_USART_DEBUG_STOP_MODE +#define CONF_SERCOM_7_USART_DEBUG_STOP_MODE 0 #endif // </e> -#ifndef CONF_SERCOM_2_USART_INACK -#define CONF_SERCOM_2_USART_INACK 0x0 +#ifndef CONF_SERCOM_7_USART_INACK +#define CONF_SERCOM_7_USART_INACK 0x0 #endif -#ifndef CONF_SERCOM_2_USART_DSNACK -#define CONF_SERCOM_2_USART_DSNACK 0x0 +#ifndef CONF_SERCOM_7_USART_DSNACK +#define CONF_SERCOM_7_USART_DSNACK 0x0 #endif -#ifndef CONF_SERCOM_2_USART_MAXITER -#define CONF_SERCOM_2_USART_MAXITER 0x7 +#ifndef CONF_SERCOM_7_USART_MAXITER +#define CONF_SERCOM_7_USART_MAXITER 0x7 #endif -#ifndef CONF_SERCOM_2_USART_GTIME -#define CONF_SERCOM_2_USART_GTIME 0x2 +#ifndef CONF_SERCOM_7_USART_GTIME +#define CONF_SERCOM_7_USART_GTIME 0x2 #endif -#define CONF_SERCOM_2_USART_RXINV 0x0 -#define CONF_SERCOM_2_USART_TXINV 0x0 +#define CONF_SERCOM_7_USART_RXINV 0x0 +#define CONF_SERCOM_7_USART_TXINV 0x0 -#ifndef CONF_SERCOM_2_USART_CMODE -#define CONF_SERCOM_2_USART_CMODE 0 +#ifndef CONF_SERCOM_7_USART_CMODE +#define CONF_SERCOM_7_USART_CMODE 0 #endif -#ifndef CONF_SERCOM_2_USART_RXPO -#define CONF_SERCOM_2_USART_RXPO 1 /* RX is on PIN_PB24 */ +#ifndef CONF_SERCOM_7_USART_RXPO +#define CONF_SERCOM_7_USART_RXPO 1 /* RX is on PIN_PB31 */ #endif -#ifndef CONF_SERCOM_2_USART_TXPO -#define CONF_SERCOM_2_USART_TXPO 0 /* TX is on PIN_PB25 */ +#ifndef CONF_SERCOM_7_USART_TXPO +#define CONF_SERCOM_7_USART_TXPO 0 /* TX is on PIN_PB30 */ #endif /* Set correct parity settings in register interface based on PARITY setting */ -#if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 1 -#if CONF_SERCOM_2_USART_PARITY == 0 -#define CONF_SERCOM_2_USART_PMODE 0 -#define CONF_SERCOM_2_USART_FORM 4 +#if CONF_SERCOM_7_USART_LIN_SLAVE_ENABLE == 1 +#if CONF_SERCOM_7_USART_PARITY == 0 +#define CONF_SERCOM_7_USART_PMODE 0 +#define CONF_SERCOM_7_USART_FORM 4 #else -#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1 -#define CONF_SERCOM_2_USART_FORM 5 +#define CONF_SERCOM_7_USART_PMODE CONF_SERCOM_7_USART_PARITY - 1 +#define CONF_SERCOM_7_USART_FORM 5 #endif -#else /* #if CONF_SERCOM_2_USART_LIN_SLAVE_ENABLE == 0 */ -#if CONF_SERCOM_2_USART_PARITY == 0 -#define CONF_SERCOM_2_USART_PMODE 0 -#define CONF_SERCOM_2_USART_FORM 0 +#else /* #if CONF_SERCOM_7_USART_LIN_SLAVE_ENABLE == 0 */ +#if CONF_SERCOM_7_USART_PARITY == 0 +#define CONF_SERCOM_7_USART_PMODE 0 +#define CONF_SERCOM_7_USART_FORM 0 #else -#define CONF_SERCOM_2_USART_PMODE CONF_SERCOM_2_USART_PARITY - 1 -#define CONF_SERCOM_2_USART_FORM 1 +#define CONF_SERCOM_7_USART_PMODE CONF_SERCOM_7_USART_PARITY - 1 +#define CONF_SERCOM_7_USART_FORM 1 #endif #endif // Calculate BAUD register value in UART mode -#if CONF_SERCOM_2_USART_SAMPR == 0 -#ifndef CONF_SERCOM_2_USART_BAUD_RATE -#define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 16.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#if CONF_SERCOM_7_USART_SAMPR == 0 +#ifndef CONF_SERCOM_7_USART_BAUD_RATE +#define CONF_SERCOM_7_USART_BAUD_RATE \ + 65536 - ((65536 * 16.0f * CONF_SERCOM_7_USART_BAUD) / CONF_GCLK_SERCOM7_CORE_FREQUENCY) #endif -#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#ifndef CONF_SERCOM_7_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_7_USART_RECEIVE_PULSE_LENGTH 0 #endif -#elif CONF_SERCOM_2_USART_SAMPR == 1 -#ifndef CONF_SERCOM_2_USART_BAUD_RATE -#define CONF_SERCOM_2_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 16)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) +#elif CONF_SERCOM_7_USART_SAMPR == 1 +#ifndef CONF_SERCOM_7_USART_BAUD_RATE +#define CONF_SERCOM_7_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM7_CORE_FREQUENCY) / (CONF_SERCOM_7_USART_BAUD * 16)) - (CONF_SERCOM_7_USART_FRACTIONAL / 8) #endif -#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#ifndef CONF_SERCOM_7_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_7_USART_RECEIVE_PULSE_LENGTH 0 #endif -#elif CONF_SERCOM_2_USART_SAMPR == 2 -#ifndef CONF_SERCOM_2_USART_BAUD_RATE -#define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 8.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#elif CONF_SERCOM_7_USART_SAMPR == 2 +#ifndef CONF_SERCOM_7_USART_BAUD_RATE +#define CONF_SERCOM_7_USART_BAUD_RATE \ + 65536 - ((65536 * 8.0f * CONF_SERCOM_7_USART_BAUD) / CONF_GCLK_SERCOM7_CORE_FREQUENCY) #endif -#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#ifndef CONF_SERCOM_7_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_7_USART_RECEIVE_PULSE_LENGTH 0 #endif -#elif CONF_SERCOM_2_USART_SAMPR == 3 -#ifndef CONF_SERCOM_2_USART_BAUD_RATE -#define CONF_SERCOM_2_USART_BAUD_RATE \ - ((CONF_GCLK_SERCOM2_CORE_FREQUENCY) / (CONF_SERCOM_2_USART_BAUD * 8)) - (CONF_SERCOM_2_USART_FRACTIONAL / 8) +#elif CONF_SERCOM_7_USART_SAMPR == 3 +#ifndef CONF_SERCOM_7_USART_BAUD_RATE +#define CONF_SERCOM_7_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM7_CORE_FREQUENCY) / (CONF_SERCOM_7_USART_BAUD * 8)) - (CONF_SERCOM_7_USART_FRACTIONAL / 8) #endif -#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#ifndef CONF_SERCOM_7_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_7_USART_RECEIVE_PULSE_LENGTH 0 #endif -#elif CONF_SERCOM_2_USART_SAMPR == 4 -#ifndef CONF_SERCOM_2_USART_BAUD_RATE -#define CONF_SERCOM_2_USART_BAUD_RATE \ - 65536 - ((65536 * 3.0f * CONF_SERCOM_2_USART_BAUD) / CONF_GCLK_SERCOM2_CORE_FREQUENCY) +#elif CONF_SERCOM_7_USART_SAMPR == 4 +#ifndef CONF_SERCOM_7_USART_BAUD_RATE +#define CONF_SERCOM_7_USART_BAUD_RATE \ + 65536 - ((65536 * 3.0f * CONF_SERCOM_7_USART_BAUD) / CONF_GCLK_SERCOM7_CORE_FREQUENCY) #endif -#ifndef CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH -#define CONF_SERCOM_2_USART_RECEIVE_PULSE_LENGTH 0 +#ifndef CONF_SERCOM_7_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_7_USART_RECEIVE_PULSE_LENGTH 0 #endif #endif diff --git a/sysmoOCTSIM/config/hpl_usb_config.h b/sysmoOCTSIM/config/hpl_usb_config.h index 02439a3..73a9fea 100644 --- a/sysmoOCTSIM/config/hpl_usb_config.h +++ b/sysmoOCTSIM/config/hpl_usb_config.h @@ -39,7 +39,7 @@ // <CONF_USB_D_N_EP_MAX"> Max possible (by "Max Endpoint Number" config) // <id> usbd_num_ep_sp #ifndef CONF_USB_D_NUM_EP_SP -#define CONF_USB_D_NUM_EP_SP CONF_USB_D_N_EP_MAX +#define CONF_USB_D_NUM_EP_SP CONF_USB_N_4 #endif // </h> diff --git a/sysmoOCTSIM/config/peripheral_clk_config.h b/sysmoOCTSIM/config/peripheral_clk_config.h index c9852b6..ce68abd 100644 --- a/sysmoOCTSIM/config/peripheral_clk_config.h +++ b/sysmoOCTSIM/config/peripheral_clk_config.h @@ -40,8 +40,8 @@ // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 // <i> Select the clock source for CORE. -#ifndef CONF_GCLK_SERCOM2_CORE_SRC -#define CONF_GCLK_SERCOM2_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val +#ifndef CONF_GCLK_SERCOM7_CORE_SRC +#define CONF_GCLK_SERCOM7_CORE_SRC GCLK_PCHCTRL_GEN_GCLK2_Val #endif // <y> Slow Clock Source @@ -72,24 +72,24 @@ // <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11 // <i> Select the slow clock source. -#ifndef CONF_GCLK_SERCOM2_SLOW_SRC -#define CONF_GCLK_SERCOM2_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#ifndef CONF_GCLK_SERCOM7_SLOW_SRC +#define CONF_GCLK_SERCOM7_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val #endif /** - * \def CONF_GCLK_SERCOM2_CORE_FREQUENCY - * \brief SERCOM2's Core Clock frequency + * \def CONF_GCLK_SERCOM7_CORE_FREQUENCY + * \brief SERCOM7's Core Clock frequency */ -#ifndef CONF_GCLK_SERCOM2_CORE_FREQUENCY -#define CONF_GCLK_SERCOM2_CORE_FREQUENCY 100000000 +#ifndef CONF_GCLK_SERCOM7_CORE_FREQUENCY +#define CONF_GCLK_SERCOM7_CORE_FREQUENCY 100000000 #endif /** - * \def CONF_GCLK_SERCOM2_SLOW_FREQUENCY - * \brief SERCOM2's Slow Clock frequency + * \def CONF_GCLK_SERCOM7_SLOW_FREQUENCY + * \brief SERCOM7's Slow Clock frequency */ -#ifndef CONF_GCLK_SERCOM2_SLOW_FREQUENCY -#define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 32768 +#ifndef CONF_GCLK_SERCOM7_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM7_SLOW_FREQUENCY 32768 #endif // <y> USB Clock Source diff --git a/sysmoOCTSIM/driver_init.c b/sysmoOCTSIM/driver_init.c index 9fbc7ed..dea4ebc 100644 --- a/sysmoOCTSIM/driver_init.c +++ b/sysmoOCTSIM/driver_init.c @@ -26,10 +26,10 @@ void UART_debug_CLOCK_init() { - hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM7_GCLK_ID_CORE, CONF_GCLK_SERCOM7_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM7_GCLK_ID_SLOW, CONF_GCLK_SERCOM7_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); - hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK); + hri_mclk_set_APBDMASK_SERCOM7_bit(MCLK); } /** @@ -40,9 +40,9 @@ void UART_debug_PORT_init() { - gpio_set_pin_function(PB25, PINMUX_PB25D_SERCOM2_PAD0); + gpio_set_pin_function(UART_TX, PINMUX_PB30C_SERCOM7_PAD0); - gpio_set_pin_function(PB24, PINMUX_PB24D_SERCOM2_PAD1); + gpio_set_pin_function(UART_RX, PINMUX_PB31C_SERCOM7_PAD1); } /** @@ -53,14 +53,14 @@ void UART_debug_init(void) { UART_debug_CLOCK_init(); - usart_async_init(&UART_debug, SERCOM2, UART_debug_buffer, UART_DEBUG_BUFFER_SIZE, (void *)NULL); + usart_async_init(&UART_debug, SERCOM7, UART_debug_buffer, UART_DEBUG_BUFFER_SIZE, (void *)NULL); UART_debug_PORT_init(); } void USB_DEVICE_INSTANCE_PORT_init(void) { - gpio_set_pin_direction(PA24, + gpio_set_pin_direction(USBUP_D_N, // <y> Pin direction // <id> pad_direction // <GPIO_DIRECTION_OFF"> Off @@ -68,14 +68,14 @@ // <GPIO_DIRECTION_OUT"> Out GPIO_DIRECTION_OUT); - gpio_set_pin_level(PA24, + gpio_set_pin_level(USBUP_D_N, // <y> Initial level // <id> pad_initial_level // <false"> Low // <true"> High false); - gpio_set_pin_pull_mode(PA24, + gpio_set_pin_pull_mode(USBUP_D_N, // <y> Pull configuration // <id> pad_pull_config // <GPIO_PULL_OFF"> Off @@ -83,7 +83,7 @@ // <GPIO_PULL_DOWN"> Pull-down GPIO_PULL_OFF); - gpio_set_pin_function(PA24, + gpio_set_pin_function(USBUP_D_N, // <y> Pin function // <id> pad_function // <i> Auto : use driver pinmux if signal is imported by driver, else turn off function @@ -105,7 +105,7 @@ // <GPIO_PIN_FUNCTION_N"> N PINMUX_PA24H_USB_DM); - gpio_set_pin_direction(PA25, + gpio_set_pin_direction(USBUP_D_P, // <y> Pin direction // <id> pad_direction // <GPIO_DIRECTION_OFF"> Off @@ -113,14 +113,14 @@ // <GPIO_DIRECTION_OUT"> Out GPIO_DIRECTION_OUT); - gpio_set_pin_level(PA25, + gpio_set_pin_level(USBUP_D_P, // <y> Initial level // <id> pad_initial_level // <false"> Low // <true"> High false); - gpio_set_pin_pull_mode(PA25, + gpio_set_pin_pull_mode(USBUP_D_P, // <y> Pull configuration // <id> pad_pull_config // <GPIO_PULL_OFF"> Off @@ -128,7 +128,7 @@ // <GPIO_PULL_DOWN"> Pull-down GPIO_PULL_OFF); - gpio_set_pin_function(PA25, + gpio_set_pin_function(USBUP_D_P, // <y> Pin function // <id> pad_function // <i> Auto : use driver pinmux if signal is imported by driver, else turn off function @@ -176,14 +176,14 @@ { init_mcu(); - // GPIO on PC18 + // GPIO on PC26 gpio_set_pin_level(LED_system, // <y> Initial level // <id> pad_initial_level // <false"> Low // <true"> High - true); + false); // Set pin direction to output gpio_set_pin_direction(LED_system, GPIO_DIRECTION_OUT); diff --git a/sysmoOCTSIM/gcc/Makefile b/sysmoOCTSIM/gcc/Makefile index ff11dd9..7bc5fd3 100644 --- a/sysmoOCTSIM/gcc/Makefile +++ b/sysmoOCTSIM/gcc/Makefile @@ -69,6 +69,7 @@ hal/src/hal_init.o \ gcc/gcc/startup_same54.o \ hal/src/hal_usb_device.o \ +main.o \ hpl/osc32kctrl/hpl_osc32kctrl.o \ examples/driver_examples.o \ driver_init.o \ @@ -81,7 +82,6 @@ hal/src/hal_cache.o \ hpl/cmcc/hpl_cmcc.o \ atmel_start.o \ -main.o \ usb/device/usbdc.o \ hal/src/hal_atomic.o @@ -107,6 +107,7 @@ "hal/src/hal_init.o" \ "gcc/gcc/startup_same54.o" \ "hal/src/hal_usb_device.o" \ +"main.o" \ "hpl/osc32kctrl/hpl_osc32kctrl.o" \ "examples/driver_examples.o" \ "driver_init.o" \ @@ -119,7 +120,6 @@ "hal/src/hal_cache.o" \ "hpl/cmcc/hpl_cmcc.o" \ "atmel_start.o" \ -"main.o" \ "usb/device/usbdc.o" \ "hal/src/hal_atomic.o" @@ -147,11 +147,11 @@ "hal/src/hal_usb_device.d" \ "usb_start.d" \ "hal/src/hal_init.d" \ -"main.d" \ "hpl/mclk/hpl_mclk.d" \ "driver_init.d" \ "hal/src/hal_usart_async.d" \ "hpl/osc32kctrl/hpl_osc32kctrl.d" \ +"main.d" \ "examples/driver_examples.d" \ "hal/src/hal_cache.d" \ "hal/src/hal_sleep.d" \ @@ -184,7 +184,7 @@ $(QUOTE)arm-none-eabi-gcc$(QUOTE) -o $(OUTPUT_FILE_NAME).elf $(OBJS_AS_ARGS) -Wl,--start-group -lm -Wl,--end-group -mthumb \ -Wl,-Map="$(OUTPUT_FILE_NAME).map" --specs=nano.specs -Wl,--gc-sections -mcpu=cortex-m4 \ \ --T"../gcc/gcc/same54p20a_flash.ld" \ +-T"../gcc/gcc/same54n19a_flash.ld" \ -L"../gcc/gcc" @echo Finished building target: $@ @@ -208,7 +208,7 @@ @echo Building file: $< @echo ARM/GNU C Compiler $(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ --D__SAME54P20A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ +-D__SAME54N19A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ -I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/sercom" -I"../hpl/usb" -I"../hri" -I"../" -I"../config" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" @echo Finished building: $< @@ -217,7 +217,7 @@ @echo Building file: $< @echo ARM/GNU Assembler $(QUOTE)arm-none-eabi-as$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ --D__SAME54P20A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ +-D__SAME54N19A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ -I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/sercom" -I"../hpl/usb" -I"../hri" -I"../" -I"../config" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" @echo Finished building: $< @@ -226,7 +226,7 @@ @echo Building file: $< @echo ARM/GNU Preprocessing Assembler $(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ --D__SAME54P20A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ +-D__SAME54N19A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ -I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/sercom" -I"../hpl/usb" -I"../hri" -I"../" -I"../config" -I"../usb" -I"../usb/class/cdc" -I"../usb/class/cdc/device" -I"../usb/device" -I"../" -I"../CMSIS/Include" -I"../include" \ -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" @echo Finished building: $< @@ -247,4 +247,4 @@ rm -f $(DEPS_AS_ARGS) rm -f $(OUTPUT_FILE_NAME).a $(OUTPUT_FILE_NAME).hex $(OUTPUT_FILE_NAME).bin \ $(OUTPUT_FILE_NAME).lss $(OUTPUT_FILE_NAME).eep $(OUTPUT_FILE_NAME).map \ - $(OUTPUT_FILE_NAME).srec + $(OUTPUT_FILE_NAME).srec \ No newline at end of file diff --git a/sysmoOCTSIM/gcc/gcc/same54n19a_flash.ld b/sysmoOCTSIM/gcc/gcc/same54n19a_flash.ld new file mode 100644 index 0000000..eaa6ed6 --- /dev/null +++ b/sysmoOCTSIM/gcc/gcc/same54n19a_flash.ld @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAME54N19A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/sysmoOCTSIM/gcc/gcc/same54n19a_sram.ld b/sysmoOCTSIM/gcc/gcc/same54n19a_sram.ld new file mode 100644 index 0000000..fa2c47c --- /dev/null +++ b/sysmoOCTSIM/gcc/gcc/same54n19a_sram.ld @@ -0,0 +1,162 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAME54N19A + * + * Copyright (c) 2018 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/sysmoOCTSIM/hpl/port/hpl_gpio_base.h b/sysmoOCTSIM/hpl/port/hpl_gpio_base.h index f32c40f..12ff6f7 100644 --- a/sysmoOCTSIM/hpl/port/hpl_gpio_base.h +++ b/sysmoOCTSIM/hpl/port/hpl_gpio_base.h @@ -168,5 +168,4 @@ hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL); hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL); hri_port_set_EVCTRL_reg(PORT, 2, CONF_PORTC_EVCTRL); - hri_port_set_EVCTRL_reg(PORT, 3, CONF_PORTD_EVCTRL); } diff --git a/sysmoOCTSIM/hpl/sercom/hpl_sercom.c b/sysmoOCTSIM/hpl/sercom/hpl_sercom.c index 11192d0..535ebc6 100644 --- a/sysmoOCTSIM/hpl/sercom/hpl_sercom.c +++ b/sysmoOCTSIM/hpl/sercom/hpl_sercom.c @@ -163,7 +163,7 @@ }; #endif -static struct _usart_async_device *_sercom2_dev = NULL; +static struct _usart_async_device *_sercom7_dev = NULL; static uint8_t _get_sercom_index(const void *const hw); static uint8_t _sercom_get_irq_num(const void *const hw); @@ -626,8 +626,8 @@ static void _sercom_init_irq_param(const void *const hw, void *dev) { - if (hw == SERCOM2) { - _sercom2_dev = (struct _usart_async_device *)dev; + if (hw == SERCOM7) { + _sercom7_dev = (struct _usart_async_device *)dev; } } @@ -2392,30 +2392,30 @@ /** * \internal Sercom interrupt handler */ -void SERCOM2_0_Handler(void) +void SERCOM7_0_Handler(void) { - _sercom_usart_interrupt_handler(_sercom2_dev); + _sercom_usart_interrupt_handler(_sercom7_dev); } /** * \internal Sercom interrupt handler */ -void SERCOM2_1_Handler(void) +void SERCOM7_1_Handler(void) { - _sercom_usart_interrupt_handler(_sercom2_dev); + _sercom_usart_interrupt_handler(_sercom7_dev); } /** * \internal Sercom interrupt handler */ -void SERCOM2_2_Handler(void) +void SERCOM7_2_Handler(void) { - _sercom_usart_interrupt_handler(_sercom2_dev); + _sercom_usart_interrupt_handler(_sercom7_dev); } /** * \internal Sercom interrupt handler */ -void SERCOM2_3_Handler(void) +void SERCOM7_3_Handler(void) { - _sercom_usart_interrupt_handler(_sercom2_dev); + _sercom_usart_interrupt_handler(_sercom7_dev); } int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw) diff --git a/sysmoOCTSIM/hpl/usb/hpl_usb.c b/sysmoOCTSIM/hpl/usb/hpl_usb.c index 6bf09ab..b5efe6c 100644 --- a/sysmoOCTSIM/hpl/usb/hpl_usb.c +++ b/sysmoOCTSIM/hpl/usb/hpl_usb.c @@ -154,7 +154,7 @@ * \param[in] s Buffer size, in number of bytes. * \return \c true If the buffer is in RAM. */ -#define _IN_RAM(a, s) ((0x20000000 <= (uint32_t)(a)) && (((uint32_t)(a) + (s)) < (0x20000000 + 0x00042000))) +#define _IN_RAM(a, s) ((0x20000000 <= (uint32_t)(a)) && (((uint32_t)(a) + (s)) < (0x20000000 + 0x00032000))) /** Check if the address should be placed in RAM. */ #define _usb_is_addr4dma(addr, size) _IN_RAM((addr), (size)) -- To view, visit https://gerrit.osmocom.org/12808 To unsubscribe, or for help writing mail filters, visit https://gerrit.osmocom.org/settings Gerrit-Project: osmo-ccid-firmware Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifd15f6759c51b42a8d11b09f9f495d7e7a5b6afc Gerrit-Change-Number: 12808 Gerrit-PatchSet: 1 Gerrit-Owner: Kévin Redon <kredon at sysmocom.de> -------------- next part -------------- An HTML attachment was scrubbed... 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