Change in osmocom-bb[master]: trxcon/scheduler: add CCCH/SDCCH mframe layouts with CBCH

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Harald Welte gerrit-no-reply at lists.osmocom.org
Wed Oct 3 08:37:12 UTC 2018 

Harald Welte has submitted this change and it was merged. ( https://gerrit.osmocom.org/11182 )

Change subject: trxcon/scheduler: add CCCH/SDCCH mframe layouts with CBCH
......................................................................

trxcon/scheduler: add CCCH/SDCCH mframe layouts with CBCH

According to GSM TS 05.02, section 3.3.5, Cell Broadcast Channel
(CBCH) is a downlink only channel, which is used to carry the
short message service cell broadcast (SMSCB). CBCH is optional,
and uses the same physical channel as SDCCH. More precisely,
CBCH replaces sub-slot number 2 of SDCCH channels when enabled.

This change introduces the CBCH enabled multi-frame layouts,
and two separate logical channel types:

  - GSM_PCHAN_CCCH_SDCCH4_CBCH (lchan TRXC_SDCCH4_CBCH),
  - GSM_PCHAN_SDCCH8_SACCH8C_CBCH (lchan TRXC_SDCCH8_CBCH).

Both logical channels are separately identified using
the following Osmocom specific cbits:

  - TRXC_SDCCH4_CBCH - 0x18 (0b11000),
  - TRXC_SDCCH8_CBCH - 0x19 (0b11001).

The reason of this separation is that we somehow need to
distinguish between CBCH on C0/TS0, and CBCH on CX/TS0.

Unlike TRXC_SDCCH8_CBCH, TRXC_SDCCH4_CBCH is enabled
automatically (TRX_CH_FLAG_AUTO), so CBCH messages
can be decoded on C0 while being in idle mode.

Change-Id: Iad9905fc3a8a012ff1ada26ff95af384816f9873
---
M src/host/trxcon/sched_lchan_desc.c
M src/host/trxcon/sched_mframe.c
M src/host/trxcon/sched_trx.h
3 files changed, 238 insertions(+), 0 deletions(-)

Approvals:
  Harald Welte: Looks good to me, approved
  Jenkins Builder: Verified



diff --git a/src/host/trxcon/sched_lchan_desc.c b/src/host/trxcon/sched_lchan_desc.c
index 05443f6..8b2b5e1 100644
--- a/src/host/trxcon/sched_lchan_desc.c
+++ b/src/host/trxcon/sched_lchan_desc.c
@@ -300,4 +300,16 @@
 		4 * GSM_BURST_PL_LEN,	TRX_CH_FLAG_PDCH,
 		rx_data_fn,		tx_data_fn,
 	},
+	[TRXC_SDCCH4_CBCH] = {
+		TRXC_SDCCH4_CBCH,	"SDCCH/4(CBCH)",
+		0xc0,			TRX_CH_LID_DEDIC,
+		4 * GSM_BURST_PL_LEN,	TRX_CH_FLAG_AUTO,
+		rx_data_fn,		NULL,
+	},
+	[TRXC_SDCCH8_CBCH] = {
+		TRXC_SDCCH8_CBCH,	"SDCCH/8(CBCH)",
+		0xc8,			TRX_CH_LID_DEDIC,
+		4 * GSM_BURST_PL_LEN,	0x00,
+		rx_data_fn,		NULL,
+	},
 };
diff --git a/src/host/trxcon/sched_mframe.c b/src/host/trxcon/sched_mframe.c
index 25e7c29..0dcf3e7 100644
--- a/src/host/trxcon/sched_mframe.c
+++ b/src/host/trxcon/sched_mframe.c
@@ -191,6 +191,113 @@
 	{ TRXC_IDLE,		0,	TRXC_SDCCH4_2,	3 },
 };
 
+static const struct trx_frame frame_bcch_sdcch4_cbch[102] = {
+	/* dl_chan		dl_bid	ul_chan		ul_bid */
+	{ TRXC_FCCH,		0,	TRXC_SDCCH4_3,	0 },
+	{ TRXC_SCH,		0,	TRXC_SDCCH4_3,	1 },
+	{ TRXC_BCCH,		0,	TRXC_SDCCH4_3,	2 },
+	{ TRXC_BCCH,		1,	TRXC_SDCCH4_3,	3 },
+	{ TRXC_BCCH,		2,	TRXC_RACH,	0 },
+	{ TRXC_BCCH,		3,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		0,	TRXC_IDLE,	0 },
+	{ TRXC_CCCH,		1,	TRXC_IDLE,	1 },
+	{ TRXC_CCCH,		2,	TRXC_IDLE,	2 },
+	{ TRXC_CCCH,		3,	TRXC_IDLE,	3 },
+	{ TRXC_FCCH,		0,	TRXC_SACCH4_3,	0 },
+	{ TRXC_SCH,		0,	TRXC_SACCH4_3,	1 },
+	{ TRXC_CCCH,		0,	TRXC_SACCH4_3,	2 },
+	{ TRXC_CCCH,		1,	TRXC_SACCH4_3,	3 },
+	{ TRXC_CCCH,		2,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		3,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		0,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		1,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		2,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		3,	TRXC_RACH,	0 },
+	{ TRXC_FCCH,		0,	TRXC_RACH,	0 },
+	{ TRXC_SCH,		0,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_0,	0,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_0,	1,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_0,	2,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_0,	3,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_1,	0,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_1,	1,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_1,	2,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_1,	3,	TRXC_RACH,	0 },
+	{ TRXC_FCCH,		0,	TRXC_RACH,	0 },
+	{ TRXC_SCH,		0,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_CBCH,	0,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_CBCH,	1,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_CBCH,	2,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_CBCH,	3,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_3,	0,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_3,	1,	TRXC_SDCCH4_0,	0 },
+	{ TRXC_SDCCH4_3,	2,	TRXC_SDCCH4_0,	1 },
+	{ TRXC_SDCCH4_3,	3,	TRXC_SDCCH4_0,	2 },
+	{ TRXC_FCCH,		0,	TRXC_SDCCH4_0,	3 },
+	{ TRXC_SCH,		0,	TRXC_SDCCH4_1,	0 },
+	{ TRXC_SACCH4_0,	0,	TRXC_SDCCH4_1,	1 },
+	{ TRXC_SACCH4_0,	1,	TRXC_SDCCH4_1,	2 },
+	{ TRXC_SACCH4_0,	2,	TRXC_SDCCH4_1,	3 },
+	{ TRXC_SACCH4_0,	3,	TRXC_RACH,	0 },
+	{ TRXC_SACCH4_1,	0,	TRXC_RACH,	0 },
+	{ TRXC_SACCH4_1,	1,	TRXC_IDLE,	0 },
+	{ TRXC_SACCH4_1,	2,	TRXC_IDLE,	1 },
+	{ TRXC_SACCH4_1,	3,	TRXC_IDLE,	2 },
+	{ TRXC_IDLE,		0,	TRXC_IDLE,	3 },
+
+	{ TRXC_FCCH,		0,	TRXC_SDCCH4_3,	0 },
+	{ TRXC_SCH,		0,	TRXC_SDCCH4_3,	1 },
+	{ TRXC_BCCH,		0,	TRXC_SDCCH4_3,	2 },
+	{ TRXC_BCCH,		1,	TRXC_SDCCH4_3,	3 },
+	{ TRXC_BCCH,		2,	TRXC_RACH,	0 },
+	{ TRXC_BCCH,		3,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		0,	TRXC_SACCH4_0,	0 },
+	{ TRXC_CCCH,		1,	TRXC_SACCH4_0,	1 },
+	{ TRXC_CCCH,		2,	TRXC_SACCH4_0,	2 },
+	{ TRXC_CCCH,		3,	TRXC_SACCH4_0,	3 },
+	{ TRXC_FCCH,		0,	TRXC_SACCH4_1,	0 },
+	{ TRXC_SCH,		0,	TRXC_SACCH4_1,	1 },
+	{ TRXC_CCCH,		0,	TRXC_SACCH4_1,	2 },
+	{ TRXC_CCCH,		1,	TRXC_SACCH4_1,	3 },
+	{ TRXC_CCCH,		2,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		3,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		0,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		1,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		2,	TRXC_RACH,	0 },
+	{ TRXC_CCCH,		3,	TRXC_RACH,	0 },
+	{ TRXC_FCCH,		0,	TRXC_RACH,	0 },
+	{ TRXC_SCH,		0,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_0,	0,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_0,	1,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_0,	2,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_0,	3,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_1,	0,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_1,	1,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_1,	2,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_1,	3,	TRXC_RACH,	0 },
+	{ TRXC_FCCH,		0,	TRXC_RACH,	0 },
+	{ TRXC_SCH,		0,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_CBCH,	0,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_CBCH,	1,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_CBCH,	2,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_CBCH,	3,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_3,	0,	TRXC_RACH,	0 },
+	{ TRXC_SDCCH4_3,	1,	TRXC_SDCCH4_0,	0 },
+	{ TRXC_SDCCH4_3,	2,	TRXC_SDCCH4_0,	1 },
+	{ TRXC_SDCCH4_3,	3,	TRXC_SDCCH4_0,	2 },
+	{ TRXC_FCCH,		0,	TRXC_SDCCH4_0,	3 },
+	{ TRXC_SCH,		0,	TRXC_SDCCH4_1,	0 },
+	{ TRXC_IDLE,		0,	TRXC_SDCCH4_1,	1 },
+	{ TRXC_IDLE,		1,	TRXC_SDCCH4_1,	2 },
+	{ TRXC_IDLE,		2,	TRXC_SDCCH4_1,	3 },
+	{ TRXC_IDLE,		3,	TRXC_RACH,	0 },
+	{ TRXC_SACCH4_3,	0,	TRXC_RACH,	0 },
+	{ TRXC_SACCH4_3,	1,	TRXC_SDCCH4_2,	0 },
+	{ TRXC_SACCH4_3,	2,	TRXC_SDCCH4_2,	1 },
+	{ TRXC_SACCH4_3,	3,	TRXC_SDCCH4_2,	2 },
+	{ TRXC_IDLE,		0,	TRXC_SDCCH4_2,	3 },
+};
+
 static const struct trx_frame frame_sdcch8[102] = {
 	/* dl_chan		dl_bid	ul_chan		ul_bid */
 	{ TRXC_SDCCH8_0,	0,	TRXC_SACCH8_5,	0 },
@@ -298,6 +405,113 @@
 	{ TRXC_IDLE,		0,	TRXC_SACCH8_4,	3 },
 };
 
+static const struct trx_frame frame_sdcch8_cbch[102] = {
+	/* dl_chan		dl_bid	ul_chan		ul_bid */
+	{ TRXC_SDCCH8_0,	0,	TRXC_SACCH8_5,	0 },
+	{ TRXC_SDCCH8_0,	1,	TRXC_SACCH8_5,	1 },
+	{ TRXC_SDCCH8_0,	2,	TRXC_SACCH8_5,	2 },
+	{ TRXC_SDCCH8_0,	3,	TRXC_SACCH8_5,	3 },
+	{ TRXC_SDCCH8_1,	0,	TRXC_SACCH8_6,	0 },
+	{ TRXC_SDCCH8_1,	1,	TRXC_SACCH8_6,	1 },
+	{ TRXC_SDCCH8_1,	2,	TRXC_SACCH8_6,	2 },
+	{ TRXC_SDCCH8_1,	3,	TRXC_SACCH8_6,	3 },
+	{ TRXC_SDCCH8_CBCH,	0,	TRXC_SACCH8_7,	0 },
+	{ TRXC_SDCCH8_CBCH,	1,	TRXC_SACCH8_7,	1 },
+	{ TRXC_SDCCH8_CBCH,	2,	TRXC_SACCH8_7,	2 },
+	{ TRXC_SDCCH8_CBCH,	3,	TRXC_SACCH8_7,	3 },
+	{ TRXC_SDCCH8_3,	0,	TRXC_IDLE,	0 },
+	{ TRXC_SDCCH8_3,	1,	TRXC_IDLE,	0 },
+	{ TRXC_SDCCH8_3,	2,	TRXC_IDLE,	0 },
+	{ TRXC_SDCCH8_3,	3,	TRXC_SDCCH8_0,	0 },
+	{ TRXC_SDCCH8_4,	0,	TRXC_SDCCH8_0,	1 },
+	{ TRXC_SDCCH8_4,	1,	TRXC_SDCCH8_0,	2 },
+	{ TRXC_SDCCH8_4,	2,	TRXC_SDCCH8_0,	3 },
+	{ TRXC_SDCCH8_4,	3,	TRXC_SDCCH8_1,	0 },
+	{ TRXC_SDCCH8_5,	0,	TRXC_SDCCH8_1,	1 },
+	{ TRXC_SDCCH8_5,	1,	TRXC_SDCCH8_1,	2 },
+	{ TRXC_SDCCH8_5,	2,	TRXC_SDCCH8_1,	3 },
+	{ TRXC_SDCCH8_5,	3,	TRXC_IDLE,	0 },
+	{ TRXC_SDCCH8_6,	0,	TRXC_IDLE,	1 },
+	{ TRXC_SDCCH8_6,	1,	TRXC_IDLE,	2 },
+	{ TRXC_SDCCH8_6,	2,	TRXC_IDLE,	3 },
+	{ TRXC_SDCCH8_6,	3,	TRXC_SDCCH8_3,	0 },
+	{ TRXC_SDCCH8_7,	0,	TRXC_SDCCH8_3,	1 },
+	{ TRXC_SDCCH8_7,	1,	TRXC_SDCCH8_3,	2 },
+	{ TRXC_SDCCH8_7,	2,	TRXC_SDCCH8_3,	3 },
+	{ TRXC_SDCCH8_7,	3,	TRXC_SDCCH8_4,	0 },
+	{ TRXC_SACCH8_0,	0,	TRXC_SDCCH8_4,	1 },
+	{ TRXC_SACCH8_0,	1,	TRXC_SDCCH8_4,	2 },
+	{ TRXC_SACCH8_0,	2,	TRXC_SDCCH8_4,	3 },
+	{ TRXC_SACCH8_0,	3,	TRXC_SDCCH8_5,	0 },
+	{ TRXC_SACCH8_1,	0,	TRXC_SDCCH8_5,	1 },
+	{ TRXC_SACCH8_1,	1,	TRXC_SDCCH8_5,	2 },
+	{ TRXC_SACCH8_1,	2,	TRXC_SDCCH8_5,	3 },
+	{ TRXC_SACCH8_1,	3,	TRXC_SDCCH8_6,	0 },
+	{ TRXC_IDLE,		0,	TRXC_SDCCH8_6,	1 },
+	{ TRXC_IDLE,		1,	TRXC_SDCCH8_6,	2 },
+	{ TRXC_IDLE,		2,	TRXC_SDCCH8_6,	3 },
+	{ TRXC_IDLE,		3,	TRXC_SDCCH8_7,	0 },
+	{ TRXC_SACCH8_3,	0,	TRXC_SDCCH8_7,	1 },
+	{ TRXC_SACCH8_3,	1,	TRXC_SDCCH8_7,	2 },
+	{ TRXC_SACCH8_3,	2,	TRXC_SDCCH8_7,	3 },
+	{ TRXC_SACCH8_3,	3,	TRXC_SACCH8_0,	0 },
+	{ TRXC_IDLE,		0,	TRXC_SACCH8_0,	1 },
+	{ TRXC_IDLE,		0,	TRXC_SACCH8_0,	2 },
+	{ TRXC_IDLE,		0,	TRXC_SACCH8_0,	3 },
+
+	{ TRXC_SDCCH8_0,	0,	TRXC_SACCH8_1,	0 },
+	{ TRXC_SDCCH8_0,	1,	TRXC_SACCH8_1,	1 },
+	{ TRXC_SDCCH8_0,	2,	TRXC_SACCH8_1,	2 },
+	{ TRXC_SDCCH8_0,	3,	TRXC_SACCH8_1,	3 },
+	{ TRXC_SDCCH8_1,	0,	TRXC_IDLE,	0 },
+	{ TRXC_SDCCH8_1,	1,	TRXC_IDLE,	1 },
+	{ TRXC_SDCCH8_1,	2,	TRXC_IDLE,	2 },
+	{ TRXC_SDCCH8_1,	3,	TRXC_IDLE,	3 },
+	{ TRXC_SDCCH8_CBCH,	0,	TRXC_SACCH8_3,	0 },
+	{ TRXC_SDCCH8_CBCH,	1,	TRXC_SACCH8_3,	1 },
+	{ TRXC_SDCCH8_CBCH,	2,	TRXC_SACCH8_3,	2 },
+	{ TRXC_SDCCH8_CBCH,	3,	TRXC_SACCH8_3,	3 },
+	{ TRXC_SDCCH8_3,	0,	TRXC_IDLE,	0 },
+	{ TRXC_SDCCH8_3,	1,	TRXC_IDLE,	0 },
+	{ TRXC_SDCCH8_3,	2,	TRXC_IDLE,	0 },
+	{ TRXC_SDCCH8_3,	3,	TRXC_SDCCH8_0,	0 },
+	{ TRXC_SDCCH8_4,	0,	TRXC_SDCCH8_0,	1 },
+	{ TRXC_SDCCH8_4,	1,	TRXC_SDCCH8_0,	2 },
+	{ TRXC_SDCCH8_4,	2,	TRXC_SDCCH8_0,	3 },
+	{ TRXC_SDCCH8_4,	3,	TRXC_SDCCH8_1,	0 },
+	{ TRXC_SDCCH8_5,	0,	TRXC_SDCCH8_1,	1 },
+	{ TRXC_SDCCH8_5,	1,	TRXC_SDCCH8_1,	2 },
+	{ TRXC_SDCCH8_5,	2,	TRXC_SDCCH8_1,	3 },
+	{ TRXC_SDCCH8_5,	3,	TRXC_IDLE,	0 },
+	{ TRXC_SDCCH8_6,	0,	TRXC_IDLE,	1 },
+	{ TRXC_SDCCH8_6,	1,	TRXC_IDLE,	2 },
+	{ TRXC_SDCCH8_6,	2,	TRXC_IDLE,	3 },
+	{ TRXC_SDCCH8_6,	3,	TRXC_SDCCH8_3,	0 },
+	{ TRXC_SDCCH8_7,	0,	TRXC_SDCCH8_3,	1 },
+	{ TRXC_SDCCH8_7,	1,	TRXC_SDCCH8_3,	2 },
+	{ TRXC_SDCCH8_7,	2,	TRXC_SDCCH8_3,	3 },
+	{ TRXC_SDCCH8_7,	3,	TRXC_SDCCH8_4,	0 },
+	{ TRXC_SACCH8_4,	0,	TRXC_SDCCH8_4,	1 },
+	{ TRXC_SACCH8_4,	1,	TRXC_SDCCH8_4,	2 },
+	{ TRXC_SACCH8_4,	2,	TRXC_SDCCH8_4,	3 },
+	{ TRXC_SACCH8_4,	3,	TRXC_SDCCH8_5,	0 },
+	{ TRXC_SACCH8_5,	0,	TRXC_SDCCH8_5,	1 },
+	{ TRXC_SACCH8_5,	1,	TRXC_SDCCH8_5,	2 },
+	{ TRXC_SACCH8_5,	2,	TRXC_SDCCH8_5,	3 },
+	{ TRXC_SACCH8_5,	3,	TRXC_SDCCH8_6,	0 },
+	{ TRXC_SACCH8_6,	0,	TRXC_SDCCH8_6,	1 },
+	{ TRXC_SACCH8_6,	1,	TRXC_SDCCH8_6,	2 },
+	{ TRXC_SACCH8_6,	2,	TRXC_SDCCH8_6,	3 },
+	{ TRXC_SACCH8_6,	3,	TRXC_SDCCH8_7,	0 },
+	{ TRXC_SACCH8_7,	0,	TRXC_SDCCH8_7,	1 },
+	{ TRXC_SACCH8_7,	1,	TRXC_SDCCH8_7,	2 },
+	{ TRXC_SACCH8_7,	2,	TRXC_SDCCH8_7,	3 },
+	{ TRXC_SACCH8_7,	3,	TRXC_SACCH8_4,	0 },
+	{ TRXC_IDLE,		0,	TRXC_SACCH8_4,	1 },
+	{ TRXC_IDLE,		0,	TRXC_SACCH8_4,	2 },
+	{ TRXC_IDLE,		0,	TRXC_SACCH8_4,	3 },
+};
+
 static const struct trx_frame frame_tchf_ts0[104] = {
 	/* dl_chan	dl_bid	ul_chan		ul_bid */
 	{ TRXC_TCHF,	0,	TRXC_TCHF,	0 },
@@ -1728,11 +1942,21 @@
 		frame_bcch_sdcch4
 	},
 	{
+		GSM_PCHAN_CCCH_SDCCH4_CBCH, "BCCH+CCCH+SDCCH/4+SACCH/4+CBCH",
+		102,	0xff,	(uint64_t) 0x400f001e3e,
+		frame_bcch_sdcch4_cbch
+	},
+	{
 		GSM_PCHAN_SDCCH8_SACCH8C, "SDCCH/8+SACCH/8",
 		102,	0xff,	(uint64_t) 0xff01fe000,
 		frame_sdcch8
 	},
 	{
+		GSM_PCHAN_SDCCH8_SACCH8C_CBCH, "SDCCH/8+SACCH/8+CBCH",
+		102,	0xff,	(uint64_t) 0x8ff01fe000,
+		frame_sdcch8_cbch
+	},
+	{
 		GSM_PCHAN_TCH_F, "TCH/F+SACCH",
 		104,	0x01,	(uint64_t) 0x200040,
 		frame_tchf_ts0
diff --git a/src/host/trxcon/sched_trx.h b/src/host/trxcon/sched_trx.h
index 10ae256..1f0dbc2 100644
--- a/src/host/trxcon/sched_trx.h
+++ b/src/host/trxcon/sched_trx.h
@@ -83,6 +83,8 @@
 	TRXC_SACCH8_7,
 	TRXC_PDTCH,
 	TRXC_PTCCH,
+	TRXC_SDCCH4_CBCH,
+	TRXC_SDCCH8_CBCH,
 	_TRX_CHAN_MAX
 };
 

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Gerrit-Project: osmocom-bb
Gerrit-Branch: master
Gerrit-MessageType: merged
Gerrit-Change-Id: Iad9905fc3a8a012ff1ada26ff95af384816f9873
Gerrit-Change-Number: 11182
Gerrit-PatchSet: 4
Gerrit-Owner: Vadim Yanitskiy <axilirator at gmail.com>
Gerrit-Reviewer: Harald Welte <laforge at gnumonks.org>
Gerrit-Reviewer: Jenkins Builder (1000002)
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