Hi Alexander. Yes, I'd definitely be interested in participating in a hardware debug session. I have a long-term FPGA consulting gig for Analog Devices and may be able to get permission to use some of their high-end test Agilent equipment in the lab on evenings and weekends if I ask nicely.
I just e-mailed my outside sales guy at Avnet and requested a quote for the
XC6SLX75-2FGG484C qty. 100 and 1000.
(I'll also get a quote from Arrow for a comparable Altera part, which will be useful in negotiating a better price than the one they will initially offer.)
In my spare time over the next couple of months, I'm going to attempt to add support for a 10/100 Ethernet MAC in the USRP N210 FPGA image.
-Robin
On Tue, Oct 4, 2011 at 5:45 PM, Alexander Chemeris
<alexander.chemeris@gmail.com> wrote:
Hi all,
Attached is a new version of our schematics and PCB layout (note, they
may differ a bit with schematics being more recent).
Btw, I found diffpdf tool very useful for schematics comparison:
http://www.qtrac.eu/diffpdf.html
It nicely highlights changes, so you don't miss something.
Our current plan for hardware prototyping is like this:
1. Most important parts of PCB layout should be done by the end of this week
2. Then we have 1 week (maximum!) to do any small changes to layout we
may want and fix bugs we (hopefully) find.
3. Then 1 week for the final layout polishing, adding labels, etc.
4. Final ACK for the layout and we push it to the fab for printing.
Manufacturing and delivery to Moscow will take 2-3 weeks.
5. 1 week for assembly
This is about 5-7 weeks and then we will have a lot of fun with
hardware and software debug.
Robin, do you want to get an assembled board to participate in the
hardware debug session? :)
Btw, could you get a quote for the FPGA from Xilinx for 100pcs?
--
Regards,
Alexander Chemeris.
--
Robin Coxe | Close-Haul Communications, Inc. | Boston, MA
+1-617-470-8825