[BNDS]
I=1
II=1
III=1
IV=1
V=1
VI=1
VII=1
VIII=1
IX=1
X=1
XI=1
XII=1
XIII=1
XIV=1
[0]
cmbDCCalAddr=0
cmbCalVal=31
LPF_dco_CAL=31
rgrDecode=0
rgrDsmRst=1
chbPwrTopMods=1
chbPwrSoftTx=1
chbPwrSoftRx=0
rgrSpiMode=1
rgrCLKSEL_LPFCAL=1
chbPD_CLKLPFCAL=1
chkLpfCalEnEnf=0
chkLpfCalRst=1
chkLpfCalEn=0
cmbLpfCalCode=0
cmbLpfCalBw=0
chbRxTestModeEn=0
rgrBBLB=0
rgrRFLB=0
rgrRXOUTSW=1
chbSpiClkBuf_0=1
chbSpiClkBuf_1=0
chbSpiClkBuf_2=0
chbSpiClkBuf_3=0
chbSpiClkBuf_4=0
chbSpiClkBuf_5=0
chbSpiClkBuf_6=0
rgrFDDTDD=0
rgrTDDMOD=0
chbPDXCOBUF=0
chbSLFBXCOBUF=1
chbBYPXCOBUF=0
chbPwrLpfCal=1
chbPwrRfLbsw=0
[3]
cmbDCCalAddr=1
cmbCalVal=31
LPF_dco_I=31
LPF_dco_Q=31
cmbLpfBw=0
chbPwrLpfMods=1
rgrDecode=0
rgrLpfByp=0
cmbDCOffset=12
chbTX_DACBUF_EN=1
cmbRcCal=3
chbPwrDCCmpr=1
chbPwrDCDac=1
chbPwrDCRef=1
chbPwrLpf=1
[5]
cmbDCCalAddr=0
cmbCalVal=31
LPF_dco_I=31
LPF_dco_Q=31
cmbLpfBw=0
chbPwrLpfMods=1
rgrDecode=0
rgrLpfByp=0
cmbDCOffset=12
chbTX_DACBUF_EN=0
cmbRcCal=3
chbPwrDCCmpr=1
chbPwrDCDac=1
chbPwrDCRef=1
chbPwrLpf=1
[4]
chbPwrTxRfMods=1
rgrDecode=0
cmbVga1G_u=31
cmbVga1DcI=128
cmbVga1DcQ=128
rgrPA=2
chbPD_DRVAUX=1
chbPD_PKDET=1
cmbVga2G_u=25
cmbENVD=0
cmbENVD2=0
cmbPKDBW=0
rgrLOOPBBEN=0
chbFST_PKDET=0
chbFST_TXHFBIAS=0
cmbICT_TXLOBUF=4
cmbVBCAS_TXDRV=0
cmbICT_TXMIX=12
cmbICT_TXDRV=12
chbPwrVga1_I=1
chbPwrVga1_Q=1
chbPD_TXDRV=0
chbPD_TXLOBUF=0
chbPwrVga2=0
cmbVga1G_t=21
cmbVga2G_t=0
[6]
cmbDCCalAddr=0
cmbCalVal=31
dc_ref=31
dc2a_I=31
dc2a_Q=31
dc2b_I=31
dc2b_Q=31
cmbVCM=12
chbPwrVGA2Mods=1
rgrDecode=0
cmbVga2G_u=1
chbPwrDCCurrR=1
chbPwrDCDACB=1
chbPwrDCCmpB=1
chbPwrDCDACA=1
chbPwrDCCmpA=1
chbPwrBG=1
chbPwrBypAB=1
chbPwrBypB=1
chbPwrBypA=1
chbPwrCurrRef=1
cmbVga2GB_t=0
cmbVga2GA_t=1
[7]
rgrDecode=0
chbPwrRxFeMods=1
cmbIN1SEL_MIX_RXFE=1
cmbDCOFF_I_RXFE=63
chkINLOAD_LNA_RXFE=1
cmbDCOFF_Q_RXFE=63
chkXLOAD_LNA_RXFE=0
cmbIP2TRIM_I_RXFE=63
cmbIP2TRIM_Q_RXFE=63
cmbG_LNA_RXFE=2
cmbLNASEL_RXFE=1
cmbCBE_LNA_RXFE=0
cmbRFB_TIA_RXFE=120
cmbCFB_TIA_RXFE=0
cmbRDLEXT_LNA_RXFE=28
cmbRDLINT_LNA_RXFE=55
cmbICT_MIX_RXFE=7
cmbICT_LNA_RXFE=7
cmbICT_TIA_RXFE=7
cmbICT_MXLOB_RXFE=7
cmbLOBN_MIX_RXFE=3
chkRINEN_MIX_RXFE=0
cmbG_FINE_LNA3_RXFE=0
chkPD_TIA_RXFE=1
chkPD_MXLOB_RXFE=1
chkPD_MIX_RXFE=1
chkPD_LNA_RXFE=1
[1]
txtDesFreq=3.2
chkDITHEN=1
cmbDITHN=0
chbPwrPllMods=1
chbAUTOBYP=0
rgrDecode=0
rgrMODE=0
rgrSELVCO=3
rgrFRANGE=1
cmbSELOUT=1
chbEN_PFD_UP=1
chkOEN_TSTD_SX=0
chkPASSEN_TSTOD_SD=0
cmbICHP=14
chbBYPVCOREG=1
chbPDVCOREG=1
chbFSTVCOBG=1
cmbOFFUP=0
cmbVOVCOREG=5
cmbOFFDOWN=3
cmbVCOCAP=36
cmbBCODE=5
cmbACODE=0
cmbPD_VCOCOMP_SX=0
chkENLOBUF=1
chkENLAMP=1
chkTRI=0
chkPOL=0
chkPFDPD=1
chkENFEEDDIV=1
chkPFDCLKP=1
rgrBCLKSEL=2
rgrBINSEL=0
RefClk=40000000
[2]
txtDesFreq=1.95
chkDITHEN=1
cmbDITHN=0
chbPwrPllMods=1
chbAUTOBYP=0
rgrDecode=0
rgrMODE=0
rgrSELVCO=1
rgrFRANGE=1
cmbSELOUT=1
chbEN_PFD_UP=1
chkOEN_TSTD_SX=0
chkPASSEN_TSTOD_SD=0
cmbICHP=12
chbBYPVCOREG=1
chbPDVCOREG=1
chbFSTVCOBG=1
cmbOFFUP=3
cmbVOVCOREG=5
cmbOFFDOWN=0
cmbVCOCAP=16
cmbBCODE=5
cmbACODE=0
cmbPD_VCOCOMP_SX=1
chkENLOBUF=1
chkENLAMP=1
chkTRI=0
chkPOL=0
chkPFDPD=1
chkENFEEDDIV=1
chkPFDCLKP=1
rgrBCLKSEL=2
rgrBINSEL=0
RefClk=40000000
[15]
chbEN_ADC_DAC=0
rgrDecode=0
cmbDACInternalOutputLoadResistor=2
rgrDACReferenceCurrentResistor=1
cmbDACFullScaleOutputCurrent=0
cmbRefResistorBiasAdj=0
cmbRefBiasUp=0
cmbRefBiasDn=0
cmbRefGainAdj=0
cmbCoomonModeAdj=1
cmbRefBufferBoost=0
chkInputBufferDisable=1
rgrRX_FSYNC_P=0
rgrRX_INTER=0
rgrDAC_CLK_P=1
rgrTX_FSYNC_P=0
rgrTX_INTER=0
cmbADCSamplingPhase=0
cmbClockNonOverlapAdjust=0
rgrADCBiasResistorAdjust=0
cmbMainBiasDN=0
rgrADCAmp1Stage1BasUp=0
rgrADCAmp24Stage1BasUp=0
rgrADCAmp1Stage2BasUp=0
rgrADCAmp24Stage2BasUp=0
rgrQuantizerBiasUp=0
rgrInputBufferBiasUp=0
cmbBandgapTemp=8
cmbBandgapGain=8
cmbRefAmpsBiasAdj=0
cmbRefAmpsBiasUp=0
cmbRefAmpsBiasDn=0
chkEN_DAC=1
chkEN_ADC_I=1
chkEN_ADC_Q=1
chkEN_ADC_REF=1
chkEN_M_REF=1