Hi Alexander,

We usually do chip tests as close to the defaults as possible. All the changes from the defaults which lead to significant improvement would be recorded and shared with customers. Below is test description. I do not see any major changes from the defaults.

We do not have register dump. However, Lime GUI project file used in this experiment is attached. You can use GUI File->Open Project option to import it. I see Ichp and Ichp offset currents are different from defaults but these still do not justify 5-12dB worse PN in your reports. You can give it a try though before changing TCXCO.

Best regards, Srdjan

Test Description:

Dr Srdjan Milenkovic

On 22/07/2012 15:16, Alexander Chemeris wrote:
On Sun, Jul 22, 2012 at 3:11 PM, Srdjan Milenkovic
<s.milenkovic@limemicro.com> wrote:

On 21/07/2012 16:28, Alexander Chemeris wrote:

Hi Srdjan,

On Sat, Jul 21, 2012 at 4:33 PM, Srdjan Milenkovic
<s.milenkovic@limemicro.com> wrote:

Hi all,

As far as I am aware, you are currently discussing how to improve LMS6002
PLL phase noise. Below are some inputs from my side which may help.

Yes, here are some pictures of phase noise we have at UmTRX right now:
http://lists.osmocom.org/pipermail/umtrx/2012-July/000030.html

It looks like they're 5-12dB higher then data I saw in your
temperature measurement report. First thought is that this could be
due to a clock source. Did you use your EVB board for those
measurements?

Yes, we used Lime EVB, 30.72MHz TCXCO. However, using 26MHz instead of
30.72MHz TCXCO should not affect phase noise so much (5-12dB). Do you have
an alternative 26MHz TCXCO with better PN? As you quite rightly mentioned,
you are probably limited by TCXCO PN at the moment.

Could you please share LMS configuration you used during this test, so
we could re-create it locally with the EVB we have. A full register
dump of the chip would be ideal.