21.07.2012 0:23 пользователь "Thomas Tsou" <thomastsou@gmail.com> написал:

On Fri, Jul 20, 2012 at 1:14 PM, Andrey Sviyazov
<andrey.sviyazov@fairwaves.ru> wrote:
> Hi Thomas.
>
> I couldn't wait your reply and start to implement 10kHz BW of PLL.
> You can find here two pictures with results.
> First of all I found that PLL tuning algorithm doesn't work properly at low
> PLL BW.
> VCOCAP register (r0x19) should contain higher value at least for +3 units
> (to make CAP lower), otherwise freq's above 950MHz never locked.
> Note, that you should read and change register 0x19 after autotuning.
> Second, you can see some noise difference for the 925MHz because of used
> DIV=8 of  the VCO, instead of DIV=4 for 942 and 960MHz.
> Third, you can see PLL noice dependance with the charge pump current
> (r0x16).
>
> On the other two pictures you can find which components have to be changed.
> Thomas, please make one more measure of LO noise and jitter at PLL BW=10kHz
> by your instrument.
> We need to know, is it real to reach modulation accuracy of 1.5 degrees RMS
> or impossible, just because of LMS PLL have bigger jitter.

Here are phase noise plots with following settings measured at 925 MHz
and 945 MHz.

--reg 0x16 --data 0x93
--reg 0x26 --data 0x98

Charge pump current had a definite effect as did changing the
frequency. Measured on the E4406A, phase error is quite high. There
are still other calibration issues, but phase noise is probably still
a concern. I also still have errors with auto calibration.

Note that USRP1 - with better phase noise - does not reach < 1.5
degree error, but is close at < 2.0 degrees RMS.

I'm currently going through the previous issues. If there is anything
else I should examine or test, let me know.

  Thomas