We do not have register dump. However, Lime GUI
project file used in this experiment is attached. You
can use GUI File->Open Project option to import it. I
see Ichp and Ichp offset currents are different from
defaults but these still do not justify 5-12dB worse PN
in your reports. You can give it a try though before
changing TCXCO.
We will try to adjust Ichp and offset first off
all. Thank you for hint.
Test Description:
- DC MAX applied through
analogue inputs, DACs off
It is quite important detail too.
- TXVGA1 and TXVGA2 at max
gain
Similar.
- Loop filter redesigned for
100kHz loop bandwidth and 40MHz reference
- Icp and Icp offset optimized
at 25 deg. Same set up used at all other
temperatures
Please inform us values of components for 100kHz BW
filter.
But we are forced to use one clock 26MHz for all because
of target price.
- Cap code and VCO picked up
by PLL tune routine
I implemented 10kHz BW filter for PLL and found that
frequency locking become unstable because of calculated
VCOCAP value a bit lower then required (too high capacity).
If VCOCAP incremented manualy (after auto-tuned) then no
any problems.
What do you think about it.
And could you please inform me values for 10 kHz BW
filter, just to compare with my calculations.
Best regards,
Andrey Sviyazov.