Thank you. You and another forum member have helped me understand the situation. I am beginning to see the attraction of SDR platforms that integrate an FPGA immediately after the ADC. You can have wide analog filtering going to an ADC running fast, and then apply digital filters in the FPGA before downsampling to a lower rate for consumption by what-have-you.

I can accomplish the same completely in software; I'll set the sample rate high, then filter and decimate, probably in a few stages to keep the filters reasonable. I tried it this evening with some raw IQ recordings I made this afternoon and it works pretty well -- on a modern PC.

Regards,

Dave J

On Tue, Oct 22, 2013 at 1:29 AM, Sylvain Munaut <246tnt@gmail.com> wrote:

Hi,

> I don't understand what is happening here. 1 MHz is an even multiple of
> 250kHz, so maybe I'm getting an image of OAK overpowering the relatively
> weaker SFO signal. But should there not be filters that manage this?

Yes most likely an image.

> I guess I was expecting that if the device is set to 250ksps, then it would
> "close down" filters appropriately to reject signals out of that band. But
> maybe the filters don't work properly below a certain sample rate? Like the
> rtl2832 can sample down to 250ksps, but the 820T tuner was not designed for
> it?

The filters you'd need wouldn't be in the R820T anyway (it has filters
but not that narrow).
IIRC, the rtl2832 always sample at a fixed high frequency but it has
an internal downconverter + FIR filter inside to convert the sample
rate down. But that FIR probably can't handle such a big reduction ...

> Can I control the filters directly?

If you find out, let us know, but AFAIK all attempts so far didn't
succeed to get it more narrow than this.

Cheers,

Sylvain