We do plan to have large PCIe card type format to test the UE side, so we will probably end up
using your setup first. W are also using the ADR xcvr for our GPS/IRNSS design.
For MS apps, we are evaluating the various parts used in mid range handsets.
Will select the one that has the most open documentation. No sure how
open silicon motion is.
I have no illusions about the difficulty of our project ! But high speed digital design is
our bread and butter, so hopefully we should be able to make progress. L1 processing is the
tricky part. The main RISCV CPU core is already developed and online in our repository.
Probably 2-4 cores with
a vector processor accelerator will suffice for the L2/L3 stack. Will use a ringbus or a crossbar
as the interconnect.
It would help if folks in this forum had any opinions on the UCB VP. See
hwacha.org.